?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Add linux-next specific files for 20110831
[linux-2.6/next.git] / arch / arm / mach-exynos4 / mct.c
blobf3638fa73e6286461bb19a2aee3de0c66b79c991
1 /* linux/arch/arm/mach-exynos4/mct.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 MCT(Multi-Core Timer) support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/sched.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
18 #include <linux/clockchips.h>
19 #include <linux/platform_device.h>
20 #include <linux/delay.h>
21 #include <linux/percpu.h>
22
23 #include <mach/map.h>
24 #include <mach/regs-mct.h>
25 #include <asm/mach/time.h>
26
27 static unsigned long clk_cnt_per_tick;
28 static unsigned long clk_rate;
29
30 struct mct_clock_event_device {
31 struct clock_event_device *evt;
32 void __iomem *base;
33 };
34
35 struct mct_clock_event_device mct_tick[2];
36
37 static void exynos4_mct_write(unsigned int value, void *addr)
38 {
39 void __iomem *stat_addr;
40 u32 mask;
41 u32 i;
42
43 __raw_writel(value, addr);
44
45 switch ((u32) addr) {
46 case (u32) EXYNOS4_MCT_G_TCON:
47 stat_addr = EXYNOS4_MCT_G_WSTAT;
48 mask = 1 << 16; /* G_TCON write status */
49 break;
50 case (u32) EXYNOS4_MCT_G_COMP0_L:
51 stat_addr = EXYNOS4_MCT_G_WSTAT;
52 mask = 1 << 0; /* G_COMP0_L write status */
53 break;
54 case (u32) EXYNOS4_MCT_G_COMP0_U:
55 stat_addr = EXYNOS4_MCT_G_WSTAT;
56 mask = 1 << 1; /* G_COMP0_U write status */
57 break;
58 case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
59 stat_addr = EXYNOS4_MCT_G_WSTAT;
60 mask = 1 << 2; /* G_COMP0_ADD_INCR write status */
61 break;
62 case (u32) EXYNOS4_MCT_G_CNT_L:
63 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
64 mask = 1 << 0; /* G_CNT_L write status */
65 break;
66 case (u32) EXYNOS4_MCT_G_CNT_U:
67 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
68 mask = 1 << 1; /* G_CNT_U write status */
69 break;
70 case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_TCON_OFFSET):
71 stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
72 mask = 1 << 3; /* L0_TCON write status */
73 break;
74 case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_TCON_OFFSET):
75 stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
76 mask = 1 << 3; /* L1_TCON write status */
77 break;
78 case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_TCNTB_OFFSET):
79 stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
80 mask = 1 << 0; /* L0_TCNTB write status */
81 break;
82 case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_TCNTB_OFFSET):
83 stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
84 mask = 1 << 0; /* L1_TCNTB write status */
85 break;
86 case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_ICNTB_OFFSET):
87 stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
88 mask = 1 << 1; /* L0_ICNTB write status */
89 break;
90 case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_ICNTB_OFFSET):
91 stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
92 mask = 1 << 1; /* L1_ICNTB write status */
93 break;
94 default:
95 return;
96 }
97
98 /* Wait maximum 1 ms until written values are applied */
99 for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
100 if (__raw_readl(stat_addr) & mask) {
101 __raw_writel(mask, stat_addr);
102 return;
103 }
104
105 panic("MCT hangs after writing %d (addr:0x%08x)\n", value, (u32)addr);
106 }
107
108 /* Clocksource handling */
109 static void exynos4_mct_frc_start(u32 hi, u32 lo)
110 {
111 u32 reg;
112
113 exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
114 exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
115
116 reg = __raw_readl(EXYNOS4_MCT_G_TCON);
117 reg |= MCT_G_TCON_START;
118 exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
119 }
120
121 static cycle_t exynos4_frc_read(struct clocksource *cs)
122 {
123 unsigned int lo, hi;
124 u32 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
125
126 do {
127 hi = hi2;
128 lo = __raw_readl(EXYNOS4_MCT_G_CNT_L);
129 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
130 } while (hi != hi2);
131
132 return ((cycle_t)hi << 32) | lo;
133 }
134
135 struct clocksource mct_frc = {
136 .name = "mct-frc",
137 .rating = 400,
138 .read = exynos4_frc_read,
139 .mask = CLOCKSOURCE_MASK(64),
140 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
141 };
142
143 static void __init exynos4_clocksource_init(void)
144 {
145 exynos4_mct_frc_start(0, 0);
146
147 if (clocksource_register_hz(&mct_frc, clk_rate))
148 panic("%s: can't register clocksource\n", mct_frc.name);
149 }
150
151 static void exynos4_mct_comp0_stop(void)
152 {
153 unsigned int tcon;
154
155 tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
156 tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
157
158 exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
159 exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
160 }
161
162 static void exynos4_mct_comp0_start(enum clock_event_mode mode,
163 unsigned long cycles)
164 {
165 unsigned int tcon;
166 cycle_t comp_cycle;
167
168 tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
169
170 if (mode == CLOCK_EVT_MODE_PERIODIC) {
171 tcon |= MCT_G_TCON_COMP0_AUTO_INC;
172 exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
173 }
174
175 comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
176 exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
177 exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
178
179 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
180
181 tcon |= MCT_G_TCON_COMP0_ENABLE;
182 exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
183 }
184
185 static int exynos4_comp_set_next_event(unsigned long cycles,
186 struct clock_event_device *evt)
187 {
188 exynos4_mct_comp0_start(evt->mode, cycles);
189
190 return 0;
191 }
192
193 static void exynos4_comp_set_mode(enum clock_event_mode mode,
194 struct clock_event_device *evt)
195 {
196 exynos4_mct_comp0_stop();
197
198 switch (mode) {
199 case CLOCK_EVT_MODE_PERIODIC:
200 exynos4_mct_comp0_start(mode, clk_cnt_per_tick);
201 break;
202
203 case CLOCK_EVT_MODE_ONESHOT:
204 case CLOCK_EVT_MODE_UNUSED:
205 case CLOCK_EVT_MODE_SHUTDOWN:
206 case CLOCK_EVT_MODE_RESUME:
207 break;
208 }
209 }
210
211 static struct clock_event_device mct_comp_device = {
212 .name = "mct-comp",
213 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
214 .rating = 250,
215 .set_next_event = exynos4_comp_set_next_event,
216 .set_mode = exynos4_comp_set_mode,
217 };
218
219 static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
220 {
221 struct clock_event_device *evt = dev_id;
222
223 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
224
225 evt->event_handler(evt);
226
227 return IRQ_HANDLED;
228 }
229
230 static struct irqaction mct_comp_event_irq = {
231 .name = "mct_comp_irq",
232 .flags = IRQF_TIMER | IRQF_IRQPOLL,
233 .handler = exynos4_mct_comp_isr,
234 .dev_id = &mct_comp_device,
235 };
236
237 static void exynos4_clockevent_init(void)
238 {
239 clk_cnt_per_tick = clk_rate / 2 / HZ;
240
241 clockevents_calc_mult_shift(&mct_comp_device, clk_rate / 2, 5);
242 mct_comp_device.max_delta_ns =
243 clockevent_delta2ns(0xffffffff, &mct_comp_device);
244 mct_comp_device.min_delta_ns =
245 clockevent_delta2ns(0xf, &mct_comp_device);
246 mct_comp_device.cpumask = cpumask_of(0);
247 clockevents_register_device(&mct_comp_device);
248
249 setup_irq(IRQ_MCT_G0, &mct_comp_event_irq);
250 }
251
252 #ifdef CONFIG_LOCAL_TIMERS
253 /* Clock event handling */
254 static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
255 {
256 unsigned long tmp;
257 unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
258 void __iomem *addr = mevt->base + MCT_L_TCON_OFFSET;
259
260 tmp = __raw_readl(addr);
261 if (tmp & mask) {
262 tmp &= ~mask;
263 exynos4_mct_write(tmp, addr);
264 }
265 }
266
267 static void exynos4_mct_tick_start(unsigned long cycles,
268 struct mct_clock_event_device *mevt)
269 {
270 unsigned long tmp;
271
272 exynos4_mct_tick_stop(mevt);
273
274 tmp = (1 << 31) | cycles; /* MCT_L_UPDATE_ICNTB */
275
276 /* update interrupt count buffer */
277 exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
278
279 /* enable MCT tick interrupt */
280 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
281
282 tmp = __raw_readl(mevt->base + MCT_L_TCON_OFFSET);
283 tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
284 MCT_L_TCON_INTERVAL_MODE;
285 exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
286 }
287
288 static int exynos4_tick_set_next_event(unsigned long cycles,
289 struct clock_event_device *evt)
290 {
291 struct mct_clock_event_device *mevt = &mct_tick[smp_processor_id()];
292
293 exynos4_mct_tick_start(cycles, mevt);
294
295 return 0;
296 }
297
298 static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
299 struct clock_event_device *evt)
300 {
301 struct mct_clock_event_device *mevt = &mct_tick[smp_processor_id()];
302
303 exynos4_mct_tick_stop(mevt);
304
305 switch (mode) {
306 case CLOCK_EVT_MODE_PERIODIC:
307 exynos4_mct_tick_start(clk_cnt_per_tick, mevt);
308 break;
309
310 case CLOCK_EVT_MODE_ONESHOT:
311 case CLOCK_EVT_MODE_UNUSED:
312 case CLOCK_EVT_MODE_SHUTDOWN:
313 case CLOCK_EVT_MODE_RESUME:
314 break;
315 }
316 }
317
318 static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
319 {
320 struct mct_clock_event_device *mevt = dev_id;
321 struct clock_event_device *evt = mevt->evt;
322
323 /*
324 * This is for supporting oneshot mode.
325 * Mct would generate interrupt periodically
326 * without explicit stopping.
327 */
328 if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
329 exynos4_mct_tick_stop(mevt);
330
331 /* Clear the MCT tick interrupt */
332 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
333
334 evt->event_handler(evt);
335
336 return IRQ_HANDLED;
337 }
338
339 static struct irqaction mct_tick0_event_irq = {
340 .name = "mct_tick0_irq",
341 .flags = IRQF_TIMER | IRQF_NOBALANCING,
342 .handler = exynos4_mct_tick_isr,
343 };
344
345 static struct irqaction mct_tick1_event_irq = {
346 .name = "mct_tick1_irq",
347 .flags = IRQF_TIMER | IRQF_NOBALANCING,
348 .handler = exynos4_mct_tick_isr,
349 };
350
351 static void exynos4_mct_tick_init(struct clock_event_device *evt)
352 {
353 unsigned int cpu = smp_processor_id();
354
355 mct_tick[cpu].evt = evt;
356
357 if (cpu == 0) {
358 mct_tick[cpu].base = EXYNOS4_MCT_L0_BASE;
359 evt->name = "mct_tick0";
360 } else {
361 mct_tick[cpu].base = EXYNOS4_MCT_L1_BASE;
362 evt->name = "mct_tick1";
363 }
364
365 evt->cpumask = cpumask_of(cpu);
366 evt->set_next_event = exynos4_tick_set_next_event;
367 evt->set_mode = exynos4_tick_set_mode;
368 evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
369 evt->rating = 450;
370
371 clockevents_calc_mult_shift(evt, clk_rate / 2, 5);
372 evt->max_delta_ns =
373 clockevent_delta2ns(0x7fffffff, evt);
374 evt->min_delta_ns =
375 clockevent_delta2ns(0xf, evt);
376
377 clockevents_register_device(evt);
378
379 exynos4_mct_write(0x1, mct_tick[cpu].base + MCT_L_TCNTB_OFFSET);
380
381 if (cpu == 0) {
382 mct_tick0_event_irq.dev_id = &mct_tick[cpu];
383 setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
384 } else {
385 mct_tick1_event_irq.dev_id = &mct_tick[cpu];
386 setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
387 irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
388 }
389 }
390
391 /* Setup the local clock events for a CPU */
392 int __cpuinit local_timer_setup(struct clock_event_device *evt)
393 {
394 exynos4_mct_tick_init(evt);
395
396 return 0;
397 }
398
399 int local_timer_ack(void)
400 {
401 return 0;
402 }
403
404 #endif /* CONFIG_LOCAL_TIMERS */
405
406 static void __init exynos4_timer_resources(void)
407 {
408 struct clk *mct_clk;
409 mct_clk = clk_get(NULL, "xtal");
410
411 clk_rate = clk_get_rate(mct_clk);
412 }
413
414 static void __init exynos4_timer_init(void)
415 {
416 exynos4_timer_resources();
417 exynos4_clocksource_init();
418 exynos4_clockevent_init();
419 }
420
421 struct sys_timer exynos4_timer = {
422 .init = exynos4_timer_init,
423 };
linux-next