arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h

   1 /*
   2  * PTP 1588 clock using the IXP46X
   3  *
   4  * Copyright (C) 2010 OMICRON electronics GmbH
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20
  21 #ifndef _IXP46X_TS_H_
  22 #define _IXP46X_TS_H_
  23
  24 #define DEFAULT_ADDEND 0xF0000029
  25 #define TICKS_NS_SHIFT 4
  26
  27 struct ixp46x_channel_ctl {
  28         u32 ch_control;  /* 0x40 Time Synchronization Channel Control */
  29         u32 ch_event;    /* 0x44 Time Synchronization Channel Event */
  30         u32 tx_snap_lo;  /* 0x48 Transmit Snapshot Low Register */
  31         u32 tx_snap_hi;  /* 0x4C Transmit Snapshot High Register */
  32         u32 rx_snap_lo;  /* 0x50 Receive Snapshot Low Register */
  33         u32 rx_snap_hi;  /* 0x54 Receive Snapshot High Register */
  34         u32 src_uuid_lo; /* 0x58 Source UUID0 Low Register */
  35         u32 src_uuid_hi; /* 0x5C Sequence Identifier/Source UUID0 High */
  36 };
  37
  38 struct ixp46x_ts_regs {
  39         u32 control;     /* 0x00 Time Sync Control Register */
  40         u32 event;       /* 0x04 Time Sync Event Register */
  41         u32 addend;      /* 0x08 Time Sync Addend Register */
  42         u32 accum;       /* 0x0C Time Sync Accumulator Register */
  43         u32 test;        /* 0x10 Time Sync Test Register */
  44         u32 unused;      /* 0x14 */
  45         u32 rsystime_lo; /* 0x18 RawSystemTime_Low Register */
  46         u32 rsystime_hi; /* 0x1C RawSystemTime_High Register */
  47         u32 systime_lo;  /* 0x20 SystemTime_Low Register */
  48         u32 systime_hi;  /* 0x24 SystemTime_High Register */
  49         u32 trgt_lo;     /* 0x28 TargetTime_Low Register */
  50         u32 trgt_hi;     /* 0x2C TargetTime_High Register */
  51         u32 asms_lo;     /* 0x30 Auxiliary Slave Mode Snapshot Low  */
  52         u32 asms_hi;     /* 0x34 Auxiliary Slave Mode Snapshot High */
  53         u32 amms_lo;     /* 0x38 Auxiliary Master Mode Snapshot Low */
  54         u32 amms_hi;     /* 0x3C Auxiliary Master Mode Snapshot High */
  55
  56         struct ixp46x_channel_ctl channel[3];
  57 };
  58
  59 /* 0x00 Time Sync Control Register Bits */
  60 #define TSCR_AMM (1<<3)
  61 #define TSCR_ASM (1<<2)
  62 #define TSCR_TTM (1<<1)
  63 #define TSCR_RST (1<<0)
  64
  65 /* 0x04 Time Sync Event Register Bits */
  66 #define TSER_SNM (1<<3)
  67 #define TSER_SNS (1<<2)
  68 #define TTIPEND  (1<<1)
  69
  70 /* 0x40 Time Synchronization Channel Control Register Bits */
  71 #define MASTER_MODE   (1<<0)
  72 #define TIMESTAMP_ALL (1<<1)
  73
  74 /* 0x44 Time Synchronization Channel Event Register Bits */
  75 #define TX_SNAPSHOT_LOCKED (1<<0)
  76 #define RX_SNAPSHOT_LOCKED (1<<1)
  77
  78 #endif