arch/arm/mach-kirkwood/cpuidle.c

   1 /*
   2  * arch/arm/mach-kirkwood/cpuidle.c
   3  *
   4  * CPU idle Marvell Kirkwood SoCs
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2.  This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  *
  10  * The cpu idle uses wait-for-interrupt and DDR self refresh in order
  11  * to implement two idle states -
  12  * #1 wait-for-interrupt
  13  * #2 wait-for-interrupt and DDR self refresh
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/cpuidle.h>
  20 #include <linux/io.h>
  21 #include <linux/export.h>
  22 #include <asm/proc-fns.h>
  23 #include <mach/kirkwood.h>
  24
  25 #define KIRKWOOD_MAX_STATES     2
  26
  27 static struct cpuidle_driver kirkwood_idle_driver = {
  28         .name =         "kirkwood_idle",
  29         .owner =        THIS_MODULE,
  30 };
  31
  32 static DEFINE_PER_CPU(struct cpuidle_device, kirkwood_cpuidle_device);
  33
  34 /* Actual code that puts the SoC in different idle states */
  35 static int kirkwood_enter_idle(struct cpuidle_device *dev,
  36                                struct cpuidle_state *state)
  37 {
  38         struct timeval before, after;
  39         int idle_time;
  40
  41         local_irq_disable();
  42         do_gettimeofday(&before);
  43         if (state == &dev->states[0])
  44                 /* Wait for interrupt state */
  45                 cpu_do_idle();
  46         else if (state == &dev->states[1]) {
  47                 /*
  48                  * Following write will put DDR in self refresh.
  49                  * Note that we have 256 cycles before DDR puts it
  50                  * self in self-refresh, so the wait-for-interrupt
  51                  * call afterwards won't get the DDR from self refresh
  52                  * mode.
  53                  */
  54                 writel(0x7, DDR_OPERATION_BASE);
  55                 cpu_do_idle();
  56         }
  57         do_gettimeofday(&after);
  58         local_irq_enable();
  59         idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
  60                         (after.tv_usec - before.tv_usec);
  61         return idle_time;
  62 }
  63
  64 /* Initialize CPU idle by registering the idle states */
  65 static int kirkwood_init_cpuidle(void)
  66 {
  67         struct cpuidle_device *device;
  68
  69         cpuidle_register_driver(&kirkwood_idle_driver);
  70
  71         device = &per_cpu(kirkwood_cpuidle_device, smp_processor_id());
  72         device->state_count = KIRKWOOD_MAX_STATES;
  73
  74         /* Wait for interrupt state */
  75         device->states[0].enter = kirkwood_enter_idle;
  76         device->states[0].exit_latency = 1;
  77         device->states[0].target_residency = 10000;
  78         device->states[0].flags = CPUIDLE_FLAG_TIME_VALID;
  79         strcpy(device->states[0].name, "WFI");
  80         strcpy(device->states[0].desc, "Wait for interrupt");
  81
  82         /* Wait for interrupt and DDR self refresh state */
  83         device->states[1].enter = kirkwood_enter_idle;
  84         device->states[1].exit_latency = 10;
  85         device->states[1].target_residency = 10000;
  86         device->states[1].flags = CPUIDLE_FLAG_TIME_VALID;
  87         strcpy(device->states[1].name, "DDR SR");
  88         strcpy(device->states[1].desc, "WFI and DDR Self Refresh");
  89
  90         if (cpuidle_register_device(device)) {
  91                 printk(KERN_ERR "kirkwood_init_cpuidle: Failed registering\n");
  92                 return -EIO;
  93         }
  94         return 0;
  95 }
  96
  97 device_initcall(kirkwood_init_cpuidle);