2 * linux/arch/arm/mach-mmp/pxa910.c
4 * Code specific to PXA910
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/gpio.h>
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/list.h>
17 #include <asm/mach/time.h>
18 #include <mach/addr-map.h>
19 #include <mach/regs-apbc.h>
20 #include <mach/regs-apmu.h>
21 #include <mach/cputype.h>
22 #include <mach/irqs.h>
25 #include <mach/devices.h>
30 #define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000)
32 static struct mfp_addr_map pxa910_mfp_addr_map
[] __initdata
=
34 MFP_ADDR_X(GPIO0
, GPIO54
, 0xdc),
35 MFP_ADDR_X(GPIO67
, GPIO98
, 0x1b8),
36 MFP_ADDR_X(GPIO100
, GPIO109
, 0x238),
38 MFP_ADDR(GPIO123
, 0xcc),
39 MFP_ADDR(GPIO124
, 0xd0),
41 MFP_ADDR(DF_IO0
, 0x40),
42 MFP_ADDR(DF_IO1
, 0x3c),
43 MFP_ADDR(DF_IO2
, 0x38),
44 MFP_ADDR(DF_IO3
, 0x34),
45 MFP_ADDR(DF_IO4
, 0x30),
46 MFP_ADDR(DF_IO5
, 0x2c),
47 MFP_ADDR(DF_IO6
, 0x28),
48 MFP_ADDR(DF_IO7
, 0x24),
49 MFP_ADDR(DF_IO8
, 0x20),
50 MFP_ADDR(DF_IO9
, 0x1c),
51 MFP_ADDR(DF_IO10
, 0x18),
52 MFP_ADDR(DF_IO11
, 0x14),
53 MFP_ADDR(DF_IO12
, 0x10),
54 MFP_ADDR(DF_IO13
, 0xc),
55 MFP_ADDR(DF_IO14
, 0x8),
56 MFP_ADDR(DF_IO15
, 0x4),
58 MFP_ADDR(DF_nCS0_SM_nCS2
, 0x44),
59 MFP_ADDR(DF_nCS1_SM_nCS3
, 0x48),
60 MFP_ADDR(SM_nCS0
, 0x4c),
61 MFP_ADDR(SM_nCS1
, 0x50),
62 MFP_ADDR(DF_WEn
, 0x54),
63 MFP_ADDR(DF_REn
, 0x58),
64 MFP_ADDR(DF_CLE_SM_OEn
, 0x5c),
65 MFP_ADDR(DF_ALE_SM_WEn
, 0x60),
66 MFP_ADDR(SM_SCLK
, 0x64),
67 MFP_ADDR(DF_RDY0
, 0x68),
68 MFP_ADDR(SM_BE0
, 0x6c),
69 MFP_ADDR(SM_BE1
, 0x70),
70 MFP_ADDR(SM_ADV
, 0x74),
71 MFP_ADDR(DF_RDY1
, 0x78),
72 MFP_ADDR(SM_ADVMUX
, 0x7c),
73 MFP_ADDR(SM_RDY
, 0x80),
75 MFP_ADDR_X(MMC1_DAT7
, MMC1_WP
, 0x84),
80 #define APMASK(i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x09c)
82 static void __init
pxa910_init_gpio(void)
86 /* enable GPIO clock */
87 __raw_writel(APBC_APBCLK
| APBC_FNCLK
, APBC_PXA910_GPIO
);
89 /* unmask GPIO edge detection for all 4 banks - APMASKx */
90 for (i
= 0; i
< 4; i
++)
91 __raw_writel(0xffffffff, APMASK(i
));
93 pxa_init_gpio(IRQ_PXA910_AP_GPIO
, 0, 127, NULL
);
96 void __init
pxa910_init_irq(void)
102 /* APB peripheral clocks */
103 static APBC_CLK(uart1
, PXA910_UART0
, 1, 14745600);
104 static APBC_CLK(uart2
, PXA910_UART1
, 1, 14745600);
105 static APBC_CLK(twsi0
, PXA168_TWSI0
, 1, 33000000);
106 static APBC_CLK(twsi1
, PXA168_TWSI1
, 1, 33000000);
107 static APBC_CLK(pwm1
, PXA910_PWM1
, 1, 13000000);
108 static APBC_CLK(pwm2
, PXA910_PWM2
, 1, 13000000);
109 static APBC_CLK(pwm3
, PXA910_PWM3
, 1, 13000000);
110 static APBC_CLK(pwm4
, PXA910_PWM4
, 1, 13000000);
112 static APMU_CLK(nand
, NAND
, 0x19b, 156000000);
113 static APMU_CLK(u2o
, USB
, 0x1b, 480000000);
115 /* device and clock bindings */
116 static struct clk_lookup pxa910_clkregs
[] = {
117 INIT_CLKREG(&clk_uart1
, "pxa2xx-uart.0", NULL
),
118 INIT_CLKREG(&clk_uart2
, "pxa2xx-uart.1", NULL
),
119 INIT_CLKREG(&clk_twsi0
, "pxa2xx-i2c.0", NULL
),
120 INIT_CLKREG(&clk_twsi1
, "pxa2xx-i2c.1", NULL
),
121 INIT_CLKREG(&clk_pwm1
, "pxa910-pwm.0", NULL
),
122 INIT_CLKREG(&clk_pwm2
, "pxa910-pwm.1", NULL
),
123 INIT_CLKREG(&clk_pwm3
, "pxa910-pwm.2", NULL
),
124 INIT_CLKREG(&clk_pwm4
, "pxa910-pwm.3", NULL
),
125 INIT_CLKREG(&clk_nand
, "pxa3xx-nand", NULL
),
126 INIT_CLKREG(&clk_u2o
, "pxa-u2o", "U2OCLK"),
129 static int __init
pxa910_init(void)
131 if (cpu_is_pxa910()) {
132 mfp_init_base(MFPR_VIRT_BASE
);
133 mfp_init_addr(pxa910_mfp_addr_map
);
134 pxa_init_dma(IRQ_PXA910_DMA_INT0
, 32);
135 clkdev_add_table(ARRAY_AND_SIZE(pxa910_clkregs
));
140 postcore_initcall(pxa910_init
);
142 /* system timer - clock enabled, 3.25MHz */
143 #define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3))
145 static void __init
pxa910_timer_init(void)
147 /* reset and configure */
148 __raw_writel(APBC_APBCLK
| APBC_RST
, APBC_PXA910_TIMERS
);
149 __raw_writel(TIMER_CLK_RST
, APBC_PXA910_TIMERS
);
151 timer_init(IRQ_PXA910_AP1_TIMER1
);
154 struct sys_timer pxa910_timer
= {
155 .init
= pxa910_timer_init
,
158 /* on-chip devices */
160 /* NOTE: there are totally 3 UARTs on PXA910:
162 * UART1 - Slow UART (can be used both by AP and CP)
163 * UART2/3 - Fast UART
165 * To be backward compatible with the legacy FFUART/BTUART/STUART sequence,
166 * they are re-ordered as:
168 * pxa910_device_uart1 - UART2 as FFUART
169 * pxa910_device_uart2 - UART3 as BTUART
171 * UART1 is not used by AP for the moment.
173 PXA910_DEVICE(uart1
, "pxa2xx-uart", 0, UART2
, 0xd4017000, 0x30, 21, 22);
174 PXA910_DEVICE(uart2
, "pxa2xx-uart", 1, UART3
, 0xd4018000, 0x30, 23, 24);
175 PXA910_DEVICE(twsi0
, "pxa2xx-i2c", 0, TWSI0
, 0xd4011000, 0x28);
176 PXA910_DEVICE(twsi1
, "pxa2xx-i2c", 1, TWSI1
, 0xd4025000, 0x28);
177 PXA910_DEVICE(pwm1
, "pxa910-pwm", 0, NONE
, 0xd401a000, 0x10);
178 PXA910_DEVICE(pwm2
, "pxa910-pwm", 1, NONE
, 0xd401a400, 0x10);
179 PXA910_DEVICE(pwm3
, "pxa910-pwm", 2, NONE
, 0xd401a800, 0x10);
180 PXA910_DEVICE(pwm4
, "pxa910-pwm", 3, NONE
, 0xd401ac00, 0x10);
181 PXA910_DEVICE(nand
, "pxa3xx-nand", -1, NAND
, 0xd4283000, 0x80, 97, 99);