arch/arm/mach-omap2/include/mach/entry-macro.S

   1 /*
   2  * arch/arm/plat-omap/include/mach/entry-macro.S
   3  *
   4  * Low-level IRQ helper macros for OMAP-based platforms
   5  *
   6  * Copyright (C) 2009 Texas Instruments
   7  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
   8  *
   9  * This file is licensed under  the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13 #include <mach/hardware.h>
  14 #include <mach/io.h>
  15 #include <mach/irqs.h>
  16 #include <asm/hardware/gic.h>
  17
  18 #include <plat/omap24xx.h>
  19 #include <plat/omap34xx.h>
  20 #include <plat/omap44xx.h>
  21
  22 #include <plat/multi.h>
  23
  24 #define OMAP2_IRQ_BASE          OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
  25 #define OMAP3_IRQ_BASE          OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
  26 #define OMAP4_IRQ_BASE          OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
  27 #define INTCPS_SIR_IRQ_OFFSET   0x0040  /* omap2/3 active interrupt offset */
  28 #define ACTIVEIRQ_MASK          0x7f    /* omap2/3 active interrupt bits */
  29
  30                 .macro  disable_fiq
  31                 .endm
  32
  33                 .macro  arch_ret_to_user, tmp1, tmp2
  34                 .endm
  35
  36 /*
  37  * Unoptimized irq functions for multi-omap2, 3 and 4
  38  */
  39
  40 #ifdef MULTI_OMAP2
  41                 /*
  42                  * Configure the interrupt base on the first interrupt.
  43                  * See also omap_irq_base_init for setting omap_irq_base.
  44                  */
  45                 .macro  get_irqnr_preamble, base, tmp
  46                 ldr     \base, =omap_irq_base   @ irq base address
  47                 ldr     \base, [\base, #0]      @ irq base value
  48                 .endm
  49
  50                 /* Check the pending interrupts. Note that base already set */
  51                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
  52                 tst     \base, #0x100           @ gic address?
  53                 bne     4401f                   @ found gic
  54
  55                 /* Handle omap2 and omap3 */
  56                 ldr     \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
  57                 cmp     \irqnr, #0x0
  58                 bne     9998f
  59                 ldr     \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
  60                 cmp     \irqnr, #0x0
  61                 bne     9998f
  62                 ldr     \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
  63                 cmp     \irqnr, #0x0
  64                 bne     9998f
  65
  66                 /*
  67                  * ti816x has additional IRQ pending register. Checking this
  68                  * register on omap2 & omap3 has no effect (read as 0).
  69                  */
  70                 ldr     \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
  71                 cmp     \irqnr, #0x0
  72 9998:
  73                 ldrne   \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
  74                 and     \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
  75                 b       9999f
  76
  77                 /* Handle omap4 */
  78 4401:           ldr     \irqstat, [\base, #GIC_CPU_INTACK]
  79                 ldr     \tmp, =1021
  80                 bic     \irqnr, \irqstat, #0x1c00
  81                 cmp     \irqnr, #29
  82                 cmpcc   \irqnr, \irqnr
  83                 cmpne   \irqnr, \tmp
  84                 cmpcs   \irqnr, \irqnr
  85 9999:
  86                 .endm
  87
  88 #ifdef CONFIG_SMP
  89                 /* We assume that irqstat (the raw value of the IRQ acknowledge
  90                  * register) is preserved from the macro above.
  91                  * If there is an IPI, we immediately signal end of interrupt
  92                  * on the controller, since this requires the original irqstat
  93                  * value which we won't easily be able to recreate later.
  94                  */
  95
  96                 .macro test_for_ipi, irqnr, irqstat, base, tmp
  97                 bic     \irqnr, \irqstat, #0x1c00
  98                 cmp     \irqnr, #16
  99                 it      cc
 100                 strcc   \irqstat, [\base, #GIC_CPU_EOI]
 101                 it      cs
 102                 cmpcs   \irqnr, \irqnr
 103                 .endm
 104
 105                 /* As above, this assumes that irqstat and base are preserved */
 106
 107                 .macro test_for_ltirq, irqnr, irqstat, base, tmp
 108                 bic     \irqnr, \irqstat, #0x1c00
 109                 mov     \tmp, #0
 110                 cmp     \irqnr, #29
 111                 itt     eq
 112                 moveq   \tmp, #1
 113                 streq   \irqstat, [\base, #GIC_CPU_EOI]
 114                 cmp     \tmp, #0
 115                 .endm
 116 #endif  /* CONFIG_SMP */
 117
 118 #else   /* MULTI_OMAP2 */
 119
 120
 121 /*
 122  * Optimized irq functions for omap2, 3 and 4
 123  */
 124
 125 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
 126                 .macro  get_irqnr_preamble, base, tmp
 127 #ifdef CONFIG_ARCH_OMAP2
 128                 ldr     \base, =OMAP2_IRQ_BASE
 129 #else
 130                 ldr     \base, =OMAP3_IRQ_BASE
 131 #endif
 132                 .endm
 133
 134                 /* Check the pending interrupts. Note that base already set */
 135                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
 136                 ldr     \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
 137                 cmp     \irqnr, #0x0
 138                 bne     9999f
 139                 ldr     \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
 140                 cmp     \irqnr, #0x0
 141                 bne     9999f
 142                 ldr     \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
 143                 cmp     \irqnr, #0x0
 144 #ifdef CONFIG_SOC_OMAPTI816X
 145                 bne     9999f
 146                 ldr     \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
 147                 cmp     \irqnr, #0x0
 148 #endif
 149 9999:
 150                 ldrne   \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
 151                 and     \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
 152
 153                 .endm
 154 #endif
 155
 156
 157 #ifdef CONFIG_ARCH_OMAP4
 158 #define HAVE_GET_IRQNR_PREAMBLE
 159 #include <asm/hardware/entry-macro-gic.S>
 160
 161                 .macro  get_irqnr_preamble, base, tmp
 162                 ldr     \base, =OMAP4_IRQ_BASE
 163                 .endm
 164
 165 #endif
 166
 167 #endif  /* MULTI_OMAP2 */