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[linux-2.6/next.git] / arch / arm / mach-pxa / include / mach / hardware.h
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1 /*
2 * arch/arm/mach-pxa/include/mach/hardware.h
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #ifndef __ASM_ARCH_HARDWARE_H
14 #define __ASM_ARCH_HARDWARE_H
16 #include <mach/addr-map.h>
19 * Workarounds for at least 2 errata so far require this.
20 * The mapping is set in mach-pxa/generic.c.
22 #define UNCACHED_PHYS_0 0xff000000
23 #define UNCACHED_ADDR UNCACHED_PHYS_0
26 * Intel PXA2xx internal register mapping:
28 * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
29 * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
30 * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
31 * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
32 * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
33 * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
34 * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
36 * Note that not all PXA2xx chips implement all those addresses, and the
37 * kernel only maps the minimum needed range of this mapping.
39 #define io_p2v(x) (0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1))
40 #define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
42 #ifndef __ASSEMBLY__
44 # define __REG(x) (*((volatile u32 *)io_p2v(x)))
46 /* With indexed regs we don't want to feed the index through io_p2v()
47 especially if it is a variable, otherwise horrible code will result. */
48 # define __REG2(x,y) \
49 (*(volatile u32 *)((u32)&__REG(x) + (y)))
51 # define __PREG(x) (io_v2p((u32)&(x)))
53 #else
55 # define __REG(x) io_p2v(x)
56 # define __PREG(x) io_v2p(x)
58 #endif
60 #ifndef __ASSEMBLY__
62 #include <asm/cputype.h>
65 * CPU Stepping CPU_ID JTAG_ID
67 * PXA210 B0 0x69052922 0x2926C013
68 * PXA210 B1 0x69052923 0x3926C013
69 * PXA210 B2 0x69052924 0x4926C013
70 * PXA210 C0 0x69052D25 0x5926C013
72 * PXA250 A0 0x69052100 0x09264013
73 * PXA250 A1 0x69052101 0x19264013
74 * PXA250 B0 0x69052902 0x29264013
75 * PXA250 B1 0x69052903 0x39264013
76 * PXA250 B2 0x69052904 0x49264013
77 * PXA250 C0 0x69052D05 0x59264013
79 * PXA255 A0 0x69052D06 0x69264013
81 * PXA26x A0 0x69052903 0x39264013
82 * PXA26x B0 0x69052D05 0x59264013
84 * PXA27x A0 0x69054110 0x09265013
85 * PXA27x A1 0x69054111 0x19265013
86 * PXA27x B0 0x69054112 0x29265013
87 * PXA27x B1 0x69054113 0x39265013
88 * PXA27x C0 0x69054114 0x49265013
89 * PXA27x C5 0x69054117 0x79265013
91 * PXA30x A0 0x69056880 0x0E648013
92 * PXA30x A1 0x69056881 0x1E648013
93 * PXA31x A0 0x69056890 0x0E649013
94 * PXA31x A1 0x69056891 0x1E649013
95 * PXA31x A2 0x69056892 0x2E649013
96 * PXA32x B1 0x69056825 0x5E642013
97 * PXA32x B2 0x69056826 0x6E642013
99 * PXA930 B0 0x69056835 0x5E643013
100 * PXA930 B1 0x69056837 0x7E643013
101 * PXA930 B2 0x69056838 0x8E643013
103 * PXA935 A0 0x56056931 0x1E653013
104 * PXA935 B0 0x56056936 0x6E653013
105 * PXA935 B1 0x56056938 0x8E653013
107 #ifdef CONFIG_PXA25x
108 #define __cpu_is_pxa210(id) \
109 ({ \
110 unsigned int _id = (id) & 0xf3f0; \
111 _id == 0x2120; \
114 #define __cpu_is_pxa250(id) \
115 ({ \
116 unsigned int _id = (id) & 0xf3ff; \
117 _id <= 0x2105; \
120 #define __cpu_is_pxa255(id) \
121 ({ \
122 unsigned int _id = (id) & 0xffff; \
123 _id == 0x2d06; \
126 #define __cpu_is_pxa25x(id) \
127 ({ \
128 unsigned int _id = (id) & 0xf300; \
129 _id == 0x2100; \
131 #else
132 #define __cpu_is_pxa210(id) (0)
133 #define __cpu_is_pxa250(id) (0)
134 #define __cpu_is_pxa255(id) (0)
135 #define __cpu_is_pxa25x(id) (0)
136 #endif
138 #ifdef CONFIG_PXA27x
139 #define __cpu_is_pxa27x(id) \
140 ({ \
141 unsigned int _id = (id) >> 4 & 0xfff; \
142 _id == 0x411; \
144 #else
145 #define __cpu_is_pxa27x(id) (0)
146 #endif
148 #ifdef CONFIG_CPU_PXA300
149 #define __cpu_is_pxa300(id) \
150 ({ \
151 unsigned int _id = (id) >> 4 & 0xfff; \
152 _id == 0x688; \
154 #else
155 #define __cpu_is_pxa300(id) (0)
156 #endif
158 #ifdef CONFIG_CPU_PXA310
159 #define __cpu_is_pxa310(id) \
160 ({ \
161 unsigned int _id = (id) >> 4 & 0xfff; \
162 _id == 0x689; \
164 #else
165 #define __cpu_is_pxa310(id) (0)
166 #endif
168 #ifdef CONFIG_CPU_PXA320
169 #define __cpu_is_pxa320(id) \
170 ({ \
171 unsigned int _id = (id) >> 4 & 0xfff; \
172 _id == 0x603 || _id == 0x682; \
174 #else
175 #define __cpu_is_pxa320(id) (0)
176 #endif
178 #ifdef CONFIG_CPU_PXA930
179 #define __cpu_is_pxa930(id) \
180 ({ \
181 unsigned int _id = (id) >> 4 & 0xfff; \
182 _id == 0x683; \
184 #else
185 #define __cpu_is_pxa930(id) (0)
186 #endif
188 #ifdef CONFIG_CPU_PXA935
189 #define __cpu_is_pxa935(id) \
190 ({ \
191 unsigned int _id = (id) >> 4 & 0xfff; \
192 _id == 0x693; \
194 #else
195 #define __cpu_is_pxa935(id) (0)
196 #endif
198 #ifdef CONFIG_CPU_PXA955
199 #define __cpu_is_pxa955(id) \
200 ({ \
201 unsigned int _id = (id) >> 4 & 0xfff; \
202 _id == 0x581 || _id == 0xc08 \
203 || _id == 0xb76; \
205 #else
206 #define __cpu_is_pxa955(id) (0)
207 #endif
209 #define cpu_is_pxa210() \
210 ({ \
211 __cpu_is_pxa210(read_cpuid_id()); \
214 #define cpu_is_pxa250() \
215 ({ \
216 __cpu_is_pxa250(read_cpuid_id()); \
219 #define cpu_is_pxa255() \
220 ({ \
221 __cpu_is_pxa255(read_cpuid_id()); \
224 #define cpu_is_pxa25x() \
225 ({ \
226 __cpu_is_pxa25x(read_cpuid_id()); \
229 #define cpu_is_pxa27x() \
230 ({ \
231 __cpu_is_pxa27x(read_cpuid_id()); \
234 #define cpu_is_pxa300() \
235 ({ \
236 __cpu_is_pxa300(read_cpuid_id()); \
239 #define cpu_is_pxa310() \
240 ({ \
241 __cpu_is_pxa310(read_cpuid_id()); \
244 #define cpu_is_pxa320() \
245 ({ \
246 __cpu_is_pxa320(read_cpuid_id()); \
249 #define cpu_is_pxa930() \
250 ({ \
251 __cpu_is_pxa930(read_cpuid_id()); \
254 #define cpu_is_pxa935() \
255 ({ \
256 __cpu_is_pxa935(read_cpuid_id()); \
259 #define cpu_is_pxa955() \
260 ({ \
261 __cpu_is_pxa955(read_cpuid_id()); \
266 * CPUID Core Generation Bit
267 * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
269 #if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
270 #define __cpu_is_pxa2xx(id) \
271 ({ \
272 unsigned int _id = (id) >> 13 & 0x7; \
273 _id <= 0x2; \
275 #else
276 #define __cpu_is_pxa2xx(id) (0)
277 #endif
279 #ifdef CONFIG_PXA3xx
280 #define __cpu_is_pxa3xx(id) \
281 ({ \
282 __cpu_is_pxa300(id) \
283 || __cpu_is_pxa310(id) \
284 || __cpu_is_pxa320(id) \
285 || __cpu_is_pxa93x(id); \
287 #else
288 #define __cpu_is_pxa3xx(id) (0)
289 #endif
291 #if defined(CONFIG_CPU_PXA930) || defined(CONFIG_CPU_PXA935)
292 #define __cpu_is_pxa93x(id) \
293 ({ \
294 __cpu_is_pxa930(id) \
295 || __cpu_is_pxa935(id); \
297 #else
298 #define __cpu_is_pxa93x(id) (0)
299 #endif
301 #ifdef CONFIG_PXA95x
302 #define __cpu_is_pxa95x(id) \
303 ({ \
304 __cpu_is_pxa955(id); \
306 #else
307 #define __cpu_is_pxa95x(id) (0)
308 #endif
310 #define cpu_is_pxa2xx() \
311 ({ \
312 __cpu_is_pxa2xx(read_cpuid_id()); \
315 #define cpu_is_pxa3xx() \
316 ({ \
317 __cpu_is_pxa3xx(read_cpuid_id()); \
320 #define cpu_is_pxa93x() \
321 ({ \
322 __cpu_is_pxa93x(read_cpuid_id()); \
325 #define cpu_is_pxa95x() \
326 ({ \
327 __cpu_is_pxa95x(read_cpuid_id()); \
331 * return current memory and LCD clock frequency in units of 10kHz
333 extern unsigned int get_memclk_frequency_10khz(void);
335 /* return the clock tick rate of the OS timer */
336 extern unsigned long get_clock_tick_rate(void);
337 #endif
339 #if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
340 #define ARCH_HAS_DMA_SET_COHERENT_MASK
341 #endif
343 #endif /* _ASM_ARCH_HARDWARE_H */