Add linux-next specific files for 20110831
[linux-2.6/next.git] / arch / arm / mach-s3c64xx / mach-real6410.c
blob93170d4834e7dd2bc45e6dd33581816ed3ecd2f7
1 /* linux/arch/arm/mach-s3c64xx/mach-real6410.c
3 * Copyright 2010 Darius Augulis <augulis.darius@gmail.com>
4 * Copyright 2008 Openmoko, Inc.
5 * Copyright 2008 Simtec Electronics
6 * Ben Dooks <ben@simtec.co.uk>
7 * http://armlinux.simtec.co.uk/
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/fb.h>
18 #include <linux/gpio.h>
19 #include <linux/kernel.h>
20 #include <linux/list.h>
21 #include <linux/dm9000.h>
22 #include <linux/mtd/mtd.h>
23 #include <linux/mtd/partitions.h>
24 #include <linux/platform_device.h>
25 #include <linux/serial_core.h>
26 #include <linux/types.h>
28 #include <asm/mach-types.h>
29 #include <asm/mach/arch.h>
30 #include <asm/mach/map.h>
32 #include <mach/map.h>
33 #include <mach/regs-gpio.h>
34 #include <mach/regs-modem.h>
35 #include <mach/regs-srom.h>
36 #include <mach/s3c6410.h>
38 #include <plat/adc.h>
39 #include <plat/cpu.h>
40 #include <plat/devs.h>
41 #include <plat/fb.h>
42 #include <plat/nand.h>
43 #include <plat/regs-serial.h>
44 #include <plat/ts.h>
45 #include <plat/regs-fb-v4.h>
47 #include <video/platform_lcd.h>
49 #define UCON S3C2410_UCON_DEFAULT
50 #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
51 #define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
53 static struct s3c2410_uartcfg real6410_uartcfgs[] __initdata = {
54 [0] = {
55 .hwport = 0,
56 .flags = 0,
57 .ucon = UCON,
58 .ulcon = ULCON,
59 .ufcon = UFCON,
61 [1] = {
62 .hwport = 1,
63 .flags = 0,
64 .ucon = UCON,
65 .ulcon = ULCON,
66 .ufcon = UFCON,
68 [2] = {
69 .hwport = 2,
70 .flags = 0,
71 .ucon = UCON,
72 .ulcon = ULCON,
73 .ufcon = UFCON,
75 [3] = {
76 .hwport = 3,
77 .flags = 0,
78 .ucon = UCON,
79 .ulcon = ULCON,
80 .ufcon = UFCON,
84 /* DM9000AEP 10/100 ethernet controller */
86 static struct resource real6410_dm9k_resource[] = {
87 [0] = {
88 .start = S3C64XX_PA_XM0CSN1,
89 .end = S3C64XX_PA_XM0CSN1 + 1,
90 .flags = IORESOURCE_MEM
92 [1] = {
93 .start = S3C64XX_PA_XM0CSN1 + 4,
94 .end = S3C64XX_PA_XM0CSN1 + 5,
95 .flags = IORESOURCE_MEM
97 [2] = {
98 .start = S3C_EINT(7),
99 .end = S3C_EINT(7),
100 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL
104 static struct dm9000_plat_data real6410_dm9k_pdata = {
105 .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
108 static struct platform_device real6410_device_eth = {
109 .name = "dm9000",
110 .id = -1,
111 .num_resources = ARRAY_SIZE(real6410_dm9k_resource),
112 .resource = real6410_dm9k_resource,
113 .dev = {
114 .platform_data = &real6410_dm9k_pdata,
118 static struct s3c_fb_pd_win real6410_fb_win[] = {
120 .win_mode = { /* 4.3" 480x272 */
121 .left_margin = 3,
122 .right_margin = 2,
123 .upper_margin = 1,
124 .lower_margin = 1,
125 .hsync_len = 40,
126 .vsync_len = 1,
127 .xres = 480,
128 .yres = 272,
130 .max_bpp = 32,
131 .default_bpp = 16,
132 }, {
133 .win_mode = { /* 7.0" 800x480 */
134 .left_margin = 8,
135 .right_margin = 13,
136 .upper_margin = 7,
137 .lower_margin = 5,
138 .hsync_len = 3,
139 .vsync_len = 1,
140 .xres = 800,
141 .yres = 480,
143 .max_bpp = 32,
144 .default_bpp = 16,
148 static struct s3c_fb_platdata real6410_lcd_pdata __initdata = {
149 .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
150 .win[0] = &real6410_fb_win[0],
151 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
152 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
155 static struct mtd_partition real6410_nand_part[] = {
156 [0] = {
157 .name = "uboot",
158 .size = SZ_1M,
159 .offset = 0,
161 [1] = {
162 .name = "kernel",
163 .size = SZ_2M,
164 .offset = SZ_1M,
166 [2] = {
167 .name = "rootfs",
168 .size = MTDPART_SIZ_FULL,
169 .offset = SZ_1M + SZ_2M,
173 static struct s3c2410_nand_set real6410_nand_sets[] = {
174 [0] = {
175 .name = "nand",
176 .nr_chips = 1,
177 .nr_partitions = ARRAY_SIZE(real6410_nand_part),
178 .partitions = real6410_nand_part,
182 static struct s3c2410_platform_nand real6410_nand_info = {
183 .tacls = 25,
184 .twrph0 = 55,
185 .twrph1 = 40,
186 .nr_sets = ARRAY_SIZE(real6410_nand_sets),
187 .sets = real6410_nand_sets,
190 static struct platform_device *real6410_devices[] __initdata = {
191 &real6410_device_eth,
192 &s3c_device_hsmmc0,
193 &s3c_device_hsmmc1,
194 &s3c_device_fb,
195 &s3c_device_nand,
196 &s3c_device_adc,
197 &s3c_device_ts,
198 &s3c_device_ohci,
201 static void __init real6410_map_io(void)
203 u32 tmp;
205 s3c64xx_init_io(NULL, 0);
206 s3c24xx_init_clocks(12000000);
207 s3c24xx_init_uarts(real6410_uartcfgs, ARRAY_SIZE(real6410_uartcfgs));
209 /* set the LCD type */
210 tmp = __raw_readl(S3C64XX_SPCON);
211 tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
212 tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
213 __raw_writel(tmp, S3C64XX_SPCON);
215 /* remove the LCD bypass */
216 tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
217 tmp &= ~MIFPCON_LCD_BYPASS;
218 __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
222 * real6410_features string
224 * 0-9 LCD configuration
227 static char real6410_features_str[12] __initdata = "0";
229 static int __init real6410_features_setup(char *str)
231 if (str)
232 strlcpy(real6410_features_str, str,
233 sizeof(real6410_features_str));
234 return 1;
237 __setup("real6410=", real6410_features_setup);
239 #define FEATURE_SCREEN (1 << 0)
241 struct real6410_features_t {
242 int done;
243 int lcd_index;
246 static void real6410_parse_features(
247 struct real6410_features_t *features,
248 const char *features_str)
250 const char *fp = features_str;
252 features->done = 0;
253 features->lcd_index = 0;
255 while (*fp) {
256 char f = *fp++;
258 switch (f) {
259 case '0'...'9': /* tft screen */
260 if (features->done & FEATURE_SCREEN) {
261 printk(KERN_INFO "REAL6410: '%c' ignored, "
262 "screen type already set\n", f);
263 } else {
264 int li = f - '0';
265 if (li >= ARRAY_SIZE(real6410_fb_win))
266 printk(KERN_INFO "REAL6410: '%c' out "
267 "of range LCD mode\n", f);
268 else {
269 features->lcd_index = li;
272 features->done |= FEATURE_SCREEN;
273 break;
278 static void __init real6410_machine_init(void)
280 u32 cs1;
281 struct real6410_features_t features = { 0 };
283 printk(KERN_INFO "REAL6410: Option string real6410=%s\n",
284 real6410_features_str);
286 /* Parse the feature string */
287 real6410_parse_features(&features, real6410_features_str);
289 real6410_lcd_pdata.win[0] = &real6410_fb_win[features.lcd_index];
291 printk(KERN_INFO "REAL6410: selected LCD display is %dx%d\n",
292 real6410_lcd_pdata.win[0]->win_mode.xres,
293 real6410_lcd_pdata.win[0]->win_mode.yres);
295 s3c_fb_set_platdata(&real6410_lcd_pdata);
296 s3c_nand_set_platdata(&real6410_nand_info);
297 s3c24xx_ts_set_platdata(NULL);
299 /* configure nCS1 width to 16 bits */
301 cs1 = __raw_readl(S3C64XX_SROM_BW) &
302 ~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
303 cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) |
304 (1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) |
305 (1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
306 S3C64XX_SROM_BW__NCS1__SHIFT;
307 __raw_writel(cs1, S3C64XX_SROM_BW);
309 /* set timing for nCS1 suitable for ethernet chip */
311 __raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
312 (6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
313 (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
314 (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
315 (13 << S3C64XX_SROM_BCX__TACC__SHIFT) |
316 (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
317 (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
319 gpio_request(S3C64XX_GPF(15), "LCD power");
321 platform_add_devices(real6410_devices, ARRAY_SIZE(real6410_devices));
324 MACHINE_START(REAL6410, "REAL6410")
325 /* Maintainer: Darius Augulis <augulis.darius@gmail.com> */
326 .atag_offset = 0x100,
328 .init_irq = s3c6410_init_irq,
329 .map_io = real6410_map_io,
330 .init_machine = real6410_machine_init,
331 .timer = &s3c24xx_timer,
332 MACHINE_END