arch/arm/mach-s5p64x0/dev-spi.c

   1 /* linux/arch/arm/mach-s5p64x0/dev-spi.c
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * Copyright (C) 2010 Samsung Electronics Co. Ltd.
   7  *      Jaswinder Singh <jassi.brar@samsung.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12 */
  13
  14 #include <linux/platform_device.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/gpio.h>
  17
  18 #include <mach/dma.h>
  19 #include <mach/map.h>
  20 #include <mach/irqs.h>
  21 #include <mach/regs-clock.h>
  22 #include <mach/spi-clocks.h>
  23
  24 #include <plat/cpu.h>
  25 #include <plat/s3c64xx-spi.h>
  26 #include <plat/gpio-cfg.h>
  27
  28 static char *s5p64x0_spi_src_clks[] = {
  29         [S5P64X0_SPI_SRCCLK_PCLK] = "pclk",
  30         [S5P64X0_SPI_SRCCLK_SCLK] = "sclk_spi",
  31 };
  32
  33 /* SPI Controller platform_devices */
  34
  35 /* Since we emulate multi-cs capability, we do not touch the CS.
  36  * The emulated CS is toggled by board specific mechanism, as it can
  37  * be either some immediate GPIO or some signal out of some other
  38  * chip in between ... or some yet another way.
  39  * We simply do not assume anything about CS.
  40  */
  41 static int s5p6440_spi_cfg_gpio(struct platform_device *pdev)
  42 {
  43         unsigned int base;
  44
  45         switch (pdev->id) {
  46         case 0:
  47                 base = S5P6440_GPC(0);
  48                 break;
  49
  50         case 1:
  51                 base = S5P6440_GPC(4);
  52                 break;
  53
  54         default:
  55                 dev_err(&pdev->dev, "Invalid SPI Controller number!");
  56                 return -EINVAL;
  57         }
  58
  59         s3c_gpio_cfgall_range(base, 3,
  60                               S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
  61
  62         return 0;
  63 }
  64
  65 static int s5p6450_spi_cfg_gpio(struct platform_device *pdev)
  66 {
  67         unsigned int base;
  68
  69         switch (pdev->id) {
  70         case 0:
  71                 base = S5P6450_GPC(0);
  72                 break;
  73
  74         case 1:
  75                 base = S5P6450_GPC(4);
  76                 break;
  77
  78         default:
  79                 dev_err(&pdev->dev, "Invalid SPI Controller number!");
  80                 return -EINVAL;
  81         }
  82
  83         s3c_gpio_cfgall_range(base, 3,
  84                               S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
  85
  86         return 0;
  87 }
  88
  89 static struct resource s5p64x0_spi0_resource[] = {
  90         [0] = {
  91                 .start  = S5P64X0_PA_SPI0,
  92                 .end    = S5P64X0_PA_SPI0 + 0x100 - 1,
  93                 .flags  = IORESOURCE_MEM,
  94         },
  95         [1] = {
  96                 .start  = DMACH_SPI0_TX,
  97                 .end    = DMACH_SPI0_TX,
  98                 .flags  = IORESOURCE_DMA,
  99         },
 100         [2] = {
 101                 .start  = DMACH_SPI0_RX,
 102                 .end    = DMACH_SPI0_RX,
 103                 .flags  = IORESOURCE_DMA,
 104         },
 105         [3] = {
 106                 .start  = IRQ_SPI0,
 107                 .end    = IRQ_SPI0,
 108                 .flags  = IORESOURCE_IRQ,
 109         },
 110 };
 111
 112 static struct s3c64xx_spi_info s5p6440_spi0_pdata = {
 113         .cfg_gpio       = s5p6440_spi_cfg_gpio,
 114         .fifo_lvl_mask  = 0x1ff,
 115         .rx_lvl_offset  = 15,
 116         .tx_st_done     = 25,
 117 };
 118
 119 static struct s3c64xx_spi_info s5p6450_spi0_pdata = {
 120         .cfg_gpio       = s5p6450_spi_cfg_gpio,
 121         .fifo_lvl_mask  = 0x1ff,
 122         .rx_lvl_offset  = 15,
 123         .tx_st_done     = 25,
 124 };
 125
 126 static u64 spi_dmamask = DMA_BIT_MASK(32);
 127
 128 struct platform_device s5p64x0_device_spi0 = {
 129         .name           = "s3c64xx-spi",
 130         .id             = 0,
 131         .num_resources  = ARRAY_SIZE(s5p64x0_spi0_resource),
 132         .resource       = s5p64x0_spi0_resource,
 133         .dev = {
 134                 .dma_mask               = &spi_dmamask,
 135                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 136         },
 137 };
 138
 139 static struct resource s5p64x0_spi1_resource[] = {
 140         [0] = {
 141                 .start  = S5P64X0_PA_SPI1,
 142                 .end    = S5P64X0_PA_SPI1 + 0x100 - 1,
 143                 .flags  = IORESOURCE_MEM,
 144         },
 145         [1] = {
 146                 .start  = DMACH_SPI1_TX,
 147                 .end    = DMACH_SPI1_TX,
 148                 .flags  = IORESOURCE_DMA,
 149         },
 150         [2] = {
 151                 .start  = DMACH_SPI1_RX,
 152                 .end    = DMACH_SPI1_RX,
 153                 .flags  = IORESOURCE_DMA,
 154         },
 155         [3] = {
 156                 .start  = IRQ_SPI1,
 157                 .end    = IRQ_SPI1,
 158                 .flags  = IORESOURCE_IRQ,
 159         },
 160 };
 161
 162 static struct s3c64xx_spi_info s5p6440_spi1_pdata = {
 163         .cfg_gpio       = s5p6440_spi_cfg_gpio,
 164         .fifo_lvl_mask  = 0x7f,
 165         .rx_lvl_offset  = 15,
 166         .tx_st_done     = 25,
 167 };
 168
 169 static struct s3c64xx_spi_info s5p6450_spi1_pdata = {
 170         .cfg_gpio       = s5p6450_spi_cfg_gpio,
 171         .fifo_lvl_mask  = 0x7f,
 172         .rx_lvl_offset  = 15,
 173         .tx_st_done     = 25,
 174 };
 175
 176 struct platform_device s5p64x0_device_spi1 = {
 177         .name           = "s3c64xx-spi",
 178         .id             = 1,
 179         .num_resources  = ARRAY_SIZE(s5p64x0_spi1_resource),
 180         .resource       = s5p64x0_spi1_resource,
 181         .dev = {
 182                 .dma_mask               = &spi_dmamask,
 183                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 184         },
 185 };
 186
 187 void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
 188 {
 189         struct s3c64xx_spi_info *pd;
 190
 191         /* Reject invalid configuration */
 192         if (!num_cs || src_clk_nr < 0
 193                         || src_clk_nr > S5P64X0_SPI_SRCCLK_SCLK) {
 194                 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
 195                 return;
 196         }
 197
 198         switch (cntrlr) {
 199         case 0:
 200                 if (soc_is_s5p6450())
 201                         pd = &s5p6450_spi0_pdata;
 202                 else
 203                         pd = &s5p6440_spi0_pdata;
 204
 205                 s5p64x0_device_spi0.dev.platform_data = pd;
 206                 break;
 207         case 1:
 208                 if (soc_is_s5p6450())
 209                         pd = &s5p6450_spi1_pdata;
 210                 else
 211                         pd = &s5p6440_spi1_pdata;
 212
 213                 s5p64x0_device_spi1.dev.platform_data = pd;
 214                 break;
 215         default:
 216                 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
 217                                                         __func__, cntrlr);
 218                 return;
 219         }
 220
 221         pd->num_cs = num_cs;
 222         pd->src_clk_nr = src_clk_nr;
 223         pd->src_clk_name = s5p64x0_spi_src_clks[src_clk_nr];
 224 }