arch/arm/mach-u300/include/mach/gpio-u300.h

   1 /*
   2  * Copyright (C) 2007-2011 ST-Ericsson AB
   3  * License terms: GNU General Public License (GPL) version 2
   4  * GPIO block resgister definitions and inline macros for
   5  * U300 GPIO COH 901 335 or COH 901 571/3
   6  * Author: Linus Walleij <linus.walleij@stericsson.com>
   7  */
   8
   9 #ifndef __MACH_U300_GPIO_U300_H
  10 #define __MACH_U300_GPIO_U300_H
  11
  12 #include <linux/kernel.h>
  13 #include <linux/io.h>
  14 #include <mach/hardware.h>
  15 #include <asm/irq.h>
  16
  17 /* Switch type depending on platform/chip variant */
  18 #if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
  19 #define U300_COH901335
  20 #endif
  21 #if defined(CONFIG_MACH_U300_BS365) || defined(CONFIG_MACH_U300_BS335)
  22 #define U300_COH901571_3
  23 #endif
  24
  25 /* Get base address for regs here */
  26 #include "u300-regs.h"
  27 /* IRQ numbers */
  28 #include "irqs.h"
  29
  30 /*
  31  * This is the GPIO block definitions. GPIO (General Purpose I/O) can be
  32  * used for anything, and often is. The event/enable etc figures are for
  33  * the lowermost pin (pin 0 on each port), shift this left to match your
  34  * pin if you're gonna use these values.
  35  */
  36 #ifdef U300_COH901335
  37 #define U300_GPIO_PORTX_SPACING                         (0x1C)
  38 /* Port X Pin Data Register 32bit, this is both input and output (R/W) */
  39 #define U300_GPIO_PXPDIR                                (0x00)
  40 #define U300_GPIO_PXPDOR                                (0x00)
  41 /* Port X Pin Config Register 32bit (R/W) */
  42 #define U300_GPIO_PXPCR                                 (0x04)
  43 #define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK              (0x0000FFFFUL)
  44 #define U300_GPIO_PXPCR_PIN_MODE_MASK                   (0x00000003UL)
  45 #define U300_GPIO_PXPCR_PIN_MODE_SHIFT                  (0x00000002UL)
  46 #define U300_GPIO_PXPCR_PIN_MODE_INPUT                  (0x00000000UL)
  47 #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL       (0x00000001UL)
  48 #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN      (0x00000002UL)
  49 #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE     (0x00000003UL)
  50 /* Port X Interrupt Event Register 32bit (R/W) */
  51 #define U300_GPIO_PXIEV                                 (0x08)
  52 #define U300_GPIO_PXIEV_ALL_IRQ_EVENT_MASK              (0x000000FFUL)
  53 #define U300_GPIO_PXIEV_IRQ_EVENT                       (0x00000001UL)
  54 /* Port X Interrupt Enable Register 32bit (R/W) */
  55 #define U300_GPIO_PXIEN                                 (0x0C)
  56 #define U300_GPIO_PXIEN_ALL_IRQ_ENABLE_MASK             (0x000000FFUL)
  57 #define U300_GPIO_PXIEN_IRQ_ENABLE                      (0x00000001UL)
  58 /* Port X Interrupt Force Register 32bit (R/W) */
  59 #define U300_GPIO_PXIFR                                 (0x10)
  60 #define U300_GPIO_PXIFR_ALL_IRQ_FORCE_MASK              (0x000000FFUL)
  61 #define U300_GPIO_PXIFR_IRQ_FORCE                       (0x00000001UL)
  62 /* Port X Interrupt Config Register 32bit (R/W) */
  63 #define U300_GPIO_PXICR                                 (0x14)
  64 #define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK             (0x000000FFUL)
  65 #define U300_GPIO_PXICR_IRQ_CONFIG_MASK                 (0x00000001UL)
  66 #define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE         (0x00000000UL)
  67 #define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE          (0x00000001UL)
  68 /* Port X Pull-up Enable Register 32bit (R/W) */
  69 #define U300_GPIO_PXPER                                 (0x18)
  70 #define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK        (0x000000FFUL)
  71 #define U300_GPIO_PXPER_PULL_UP_DISABLE                 (0x00000001UL)
  72 /* Control Register 32bit (R/W) */
  73 #define U300_GPIO_CR                                    (0x54)
  74 #define U300_GPIO_CR_BLOCK_CLOCK_ENABLE                 (0x00000001UL)
  75 /* three ports of 8 bits each = GPIO pins 0..23 */
  76 #define U300_GPIO_NUM_PORTS 3
  77 #define U300_GPIO_PINS_PER_PORT 8
  78 #define U300_GPIO_MAX   (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS - 1)
  79 #endif
  80
  81 #ifdef U300_COH901571_3
  82 /*
  83  * Control Register 32bit (R/W)
  84  * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
  85  * gives the number of GPIO pins.
  86  * bit 8-2  (mask 0x000001FC) contains the core version ID.
  87  */
  88 #define U300_GPIO_CR                                    (0x00)
  89 #define U300_GPIO_CR_SYNC_SEL_ENABLE                    (0x00000002UL)
  90 #define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE                 (0x00000001UL)
  91 #define U300_GPIO_PORTX_SPACING                         (0x30)
  92 /* Port X Pin Data INPUT Register 32bit (R/W) */
  93 #define U300_GPIO_PXPDIR                                (0x04)
  94 /* Port X Pin Data OUTPUT Register 32bit (R/W) */
  95 #define U300_GPIO_PXPDOR                                (0x08)
  96 /* Port X Pin Config Register 32bit (R/W) */
  97 #define U300_GPIO_PXPCR                                 (0x0C)
  98 #define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK              (0x0000FFFFUL)
  99 #define U300_GPIO_PXPCR_PIN_MODE_MASK                   (0x00000003UL)
 100 #define U300_GPIO_PXPCR_PIN_MODE_SHIFT                  (0x00000002UL)
 101 #define U300_GPIO_PXPCR_PIN_MODE_INPUT                  (0x00000000UL)
 102 #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL       (0x00000001UL)
 103 #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN      (0x00000002UL)
 104 #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE     (0x00000003UL)
 105 /* Port X Pull-up Enable Register 32bit (R/W) */
 106 #define U300_GPIO_PXPER                                 (0x10)
 107 #define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK        (0x000000FFUL)
 108 #define U300_GPIO_PXPER_PULL_UP_DISABLE                 (0x00000001UL)
 109 /* Port X Interrupt Event Register 32bit (R/W) */
 110 #define U300_GPIO_PXIEV                                 (0x14)
 111 #define U300_GPIO_PXIEV_ALL_IRQ_EVENT_MASK              (0x000000FFUL)
 112 #define U300_GPIO_PXIEV_IRQ_EVENT                       (0x00000001UL)
 113 /* Port X Interrupt Enable Register 32bit (R/W) */
 114 #define U300_GPIO_PXIEN                                 (0x18)
 115 #define U300_GPIO_PXIEN_ALL_IRQ_ENABLE_MASK             (0x000000FFUL)
 116 #define U300_GPIO_PXIEN_IRQ_ENABLE                      (0x00000001UL)
 117 /* Port X Interrupt Force Register 32bit (R/W) */
 118 #define U300_GPIO_PXIFR                                 (0x1C)
 119 #define U300_GPIO_PXIFR_ALL_IRQ_FORCE_MASK              (0x000000FFUL)
 120 #define U300_GPIO_PXIFR_IRQ_FORCE                       (0x00000001UL)
 121 /* Port X Interrupt Config Register 32bit (R/W) */
 122 #define U300_GPIO_PXICR                                 (0x20)
 123 #define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK             (0x000000FFUL)
 124 #define U300_GPIO_PXICR_IRQ_CONFIG_MASK                 (0x00000001UL)
 125 #define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE         (0x00000000UL)
 126 #define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE          (0x00000001UL)
 127 #ifdef CONFIG_MACH_U300_BS335
 128 /* seven ports of 8 bits each = GPIO pins 0..55 */
 129 #define U300_GPIO_NUM_PORTS 7
 130 #else
 131 /* five ports of 8 bits each = GPIO pins 0..39 */
 132 #define U300_GPIO_NUM_PORTS 5
 133 #endif
 134 #define U300_GPIO_PINS_PER_PORT 8
 135 #define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS - 1)
 136 #endif
 137
 138 /*
 139  * Individual pin assignments for the B26/S26. Notice that the
 140  * actual usage of these pins depends on the PAD MUX settings, that
 141  * is why the same number can potentially appear several times.
 142  * In the reference design each pin is only used for one purpose.
 143  * These were determined by inspecting the B26/S26 schematic:
 144  * 2/1911-ROA 128 1603
 145  */
 146 #ifdef CONFIG_MACH_U300_BS2X
 147 #define U300_GPIO_PIN_UART_RX           0
 148 #define U300_GPIO_PIN_UART_TX           1
 149 #define U300_GPIO_PIN_GPIO02            2  /* Unrouted */
 150 #define U300_GPIO_PIN_GPIO03            3  /* Unrouted */
 151 #define U300_GPIO_PIN_CAM_SLEEP         4
 152 #define U300_GPIO_PIN_CAM_REG_EN        5
 153 #define U300_GPIO_PIN_GPIO06            6  /* Unrouted */
 154 #define U300_GPIO_PIN_GPIO07            7  /* Unrouted */
 155
 156 #define U300_GPIO_PIN_GPIO08            8  /* Service point SP2321 */
 157 #define U300_GPIO_PIN_GPIO09            9  /* Service point SP2322 */
 158 #define U300_GPIO_PIN_PHFSENSE          10 /* Headphone jack sensing */
 159 #define U300_GPIO_PIN_MMC_CLKRET        11 /* Clock return from MMC/SD card */
 160 #define U300_GPIO_PIN_MMC_CD            12 /* MMC Card insertion detection */
 161 #define U300_GPIO_PIN_FLIPSENSE         13 /* Mechanical flip sensing */
 162 #define U300_GPIO_PIN_GPIO14            14 /* DSP JTAG Port RTCK */
 163 #define U300_GPIO_PIN_GPIO15            15 /* Unrouted */
 164
 165 #define U300_GPIO_PIN_GPIO16            16 /* Unrouted */
 166 #define U300_GPIO_PIN_GPIO17            17 /* Unrouted */
 167 #define U300_GPIO_PIN_GPIO18            18 /* Unrouted */
 168 #define U300_GPIO_PIN_GPIO19            19 /* Unrouted */
 169 #define U300_GPIO_PIN_GPIO20            20 /* Unrouted */
 170 #define U300_GPIO_PIN_GPIO21            21 /* Unrouted */
 171 #define U300_GPIO_PIN_GPIO22            22 /* Unrouted */
 172 #define U300_GPIO_PIN_GPIO23            23 /* Unrouted */
 173 #endif
 174
 175 /*
 176  * Individual pin assignments for the B330/S330 and B365/S365.
 177  * Notice that the actual usage of these pins depends on the
 178  * PAD MUX settings, that is why the same number can potentially
 179  * appear several times. In the reference design each pin is only
 180  * used for one purpose. These were determined by inspecting the
 181  * S365 schematic.
 182  */
 183 #if defined(CONFIG_MACH_U300_BS330) || defined(CONFIG_MACH_U300_BS365) || \
 184     defined(CONFIG_MACH_U300_BS335)
 185 #define U300_GPIO_PIN_UART_RX           0
 186 #define U300_GPIO_PIN_UART_TX           1
 187 #define U300_GPIO_PIN_UART_CTS          2
 188 #define U300_GPIO_PIN_UART_RTS          3
 189 #define U300_GPIO_PIN_CAM_MAIN_STANDBY  4 /* Camera MAIN standby */
 190 #define U300_GPIO_PIN_GPIO05            5 /* Unrouted */
 191 #define U300_GPIO_PIN_MS_CD             6 /* Memory Stick Card insertion */
 192 #define U300_GPIO_PIN_GPIO07            7 /* Test point TP2430 */
 193
 194 #define U300_GPIO_PIN_GPIO08            8 /* Test point TP2437 */
 195 #define U300_GPIO_PIN_GPIO09            9 /* Test point TP2431 */
 196 #define U300_GPIO_PIN_GPIO10            10 /* Test point TP2432 */
 197 #define U300_GPIO_PIN_MMC_CLKRET        11 /* Clock return from MMC/SD card */
 198 #define U300_GPIO_PIN_MMC_CD            12 /* MMC Card insertion detection */
 199 #define U300_GPIO_PIN_CAM_SUB_STANDBY   13 /* Camera SUB standby */
 200 #define U300_GPIO_PIN_GPIO14            14 /* Test point TP2436 */
 201 #define U300_GPIO_PIN_GPIO15            15 /* Unrouted */
 202
 203 #define U300_GPIO_PIN_GPIO16            16 /* Test point TP2438 */
 204 #define U300_GPIO_PIN_PHFSENSE          17 /* Headphone jack sensing */
 205 #define U300_GPIO_PIN_GPIO18            18 /* Test point TP2439 */
 206 #define U300_GPIO_PIN_GPIO19            19 /* Routed somewhere */
 207 #define U300_GPIO_PIN_GPIO20            20 /* Unrouted */
 208 #define U300_GPIO_PIN_GPIO21            21 /* Unrouted */
 209 #define U300_GPIO_PIN_GPIO22            22 /* Unrouted */
 210 #define U300_GPIO_PIN_GPIO23            23 /* Unrouted */
 211
 212 #define U300_GPIO_PIN_GPIO24            24 /* Unrouted */
 213 #define U300_GPIO_PIN_GPIO25            25 /* Unrouted */
 214 #define U300_GPIO_PIN_GPIO26            26 /* Unrouted */
 215 #define U300_GPIO_PIN_GPIO27            27 /* Unrouted */
 216 #define U300_GPIO_PIN_GPIO28            28 /* Unrouted */
 217 #define U300_GPIO_PIN_GPIO29            29 /* Unrouted */
 218 #define U300_GPIO_PIN_GPIO30            30 /* Unrouted */
 219 #define U300_GPIO_PIN_GPIO31            31 /* Unrouted */
 220
 221 #define U300_GPIO_PIN_GPIO32            32 /* Unrouted */
 222 #define U300_GPIO_PIN_GPIO33            33 /* Unrouted */
 223 #define U300_GPIO_PIN_GPIO34            34 /* Unrouted */
 224 #define U300_GPIO_PIN_GPIO35            35 /* Unrouted */
 225 #define U300_GPIO_PIN_GPIO36            36 /* Unrouted */
 226 #define U300_GPIO_PIN_GPIO37            37 /* Unrouted */
 227 #define U300_GPIO_PIN_GPIO38            38 /* Unrouted */
 228 #define U300_GPIO_PIN_GPIO39            39 /* Unrouted */
 229
 230 #ifdef CONFIG_MACH_U300_BS335
 231
 232 #define U300_GPIO_PIN_GPIO40            40 /* Unrouted */
 233 #define U300_GPIO_PIN_GPIO41            41 /* Unrouted */
 234 #define U300_GPIO_PIN_GPIO42            42 /* Unrouted */
 235 #define U300_GPIO_PIN_GPIO43            43 /* Unrouted */
 236 #define U300_GPIO_PIN_GPIO44            44 /* Unrouted */
 237 #define U300_GPIO_PIN_GPIO45            45 /* Unrouted */
 238 #define U300_GPIO_PIN_GPIO46            46 /* Unrouted */
 239 #define U300_GPIO_PIN_GPIO47            47 /* Unrouted */
 240
 241 #define U300_GPIO_PIN_GPIO48            48 /* Unrouted */
 242 #define U300_GPIO_PIN_GPIO49            49 /* Unrouted */
 243 #define U300_GPIO_PIN_GPIO50            50 /* Unrouted */
 244 #define U300_GPIO_PIN_GPIO51            51 /* Unrouted */
 245 #define U300_GPIO_PIN_GPIO52            52 /* Unrouted */
 246 #define U300_GPIO_PIN_GPIO53            53 /* Unrouted */
 247 #define U300_GPIO_PIN_GPIO54            54 /* Unrouted */
 248 #define U300_GPIO_PIN_GPIO55            55 /* Unrouted */
 249 #endif
 250
 251 #endif
 252
 253 #endif /* __MACH_U300_GPIO_U300_H */