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Add linux-next specific files for 20110831
[linux-2.6/next.git] / arch / mips / include / asm / io.h
bloba58f22998a86507729e3d72d379ef6e23ddad019
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995 Waldorf GmbH
7 * Copyright (C) 1994 - 2000, 06 Ralf Baechle
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
10 * Author: Maciej W. Rozycki <macro@mips.com>
11 */
12 #ifndef _ASM_IO_H
13 #define _ASM_IO_H
14
15 #include <linux/compiler.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18
19 #include <asm/addrspace.h>
20 #include <asm/byteorder.h>
21 #include <asm/cpu.h>
22 #include <asm/cpu-features.h>
23 #include <asm-generic/iomap.h>
24 #include <asm/page.h>
25 #include <asm/pgtable-bits.h>
26 #include <asm/processor.h>
27 #include <asm/string.h>
28
29 #include <ioremap.h>
30 #include <mangle-port.h>
31
32 /*
33 * Slowdown I/O port space accesses for antique hardware.
34 */
35 #undef CONF_SLOWDOWN_IO
36
37 /*
38 * Raw operations are never swapped in software. OTOH values that raw
39 * operations are working on may or may not have been swapped by the bus
40 * hardware. An example use would be for flash memory that's used for
41 * execute in place.
42 */
43 # define __raw_ioswabb(a, x) (x)
44 # define __raw_ioswabw(a, x) (x)
45 # define __raw_ioswabl(a, x) (x)
46 # define __raw_ioswabq(a, x) (x)
47 # define ____raw_ioswabq(a, x) (x)
48
49 /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
50
51 #define IO_SPACE_LIMIT 0xffff
52
53 /*
54 * On MIPS I/O ports are memory mapped, so we access them using normal
55 * load/store instructions. mips_io_port_base is the virtual address to
56 * which all ports are being mapped. For sake of efficiency some code
57 * assumes that this is an address that can be loaded with a single lui
58 * instruction, so the lower 16 bits must be zero. Should be true on
59 * on any sane architecture; generic code does not use this assumption.
60 */
61 extern const unsigned long mips_io_port_base;
62
63 /*
64 * Gcc will generate code to load the value of mips_io_port_base after each
65 * function call which may be fairly wasteful in some cases. So we don't
66 * play quite by the book. We tell gcc mips_io_port_base is a long variable
67 * which solves the code generation issue. Now we need to violate the
68 * aliasing rules a little to make initialization possible and finally we
69 * will need the barrier() to fight side effects of the aliasing chat.
70 * This trickery will eventually collapse under gcc's optimizer. Oh well.
71 */
72 static inline void set_io_port_base(unsigned long base)
73 {
74 * (unsigned long *) &mips_io_port_base = base;
75 barrier();
76 }
77
78 /*
79 * Thanks to James van Artsdalen for a better timing-fix than
80 * the two short jumps: using outb's to a nonexistent port seems
81 * to guarantee better timings even on fast machines.
82 *
83 * On the other hand, I'd like to be sure of a non-existent port:
84 * I feel a bit unsafe about using 0x80 (should be safe, though)
85 *
86 * Linus
87 *
88 */
89
90 #define __SLOW_DOWN_IO \
91 __asm__ __volatile__( \
92 "sb\t$0,0x80(%0)" \
93 : : "r" (mips_io_port_base));
94
95 #ifdef CONF_SLOWDOWN_IO
96 #ifdef REALLY_SLOW_IO
97 #define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
98 #else
99 #define SLOW_DOWN_IO __SLOW_DOWN_IO
100 #endif
101 #else
102 #define SLOW_DOWN_IO
103 #endif
104
105 /*
106 * virt_to_phys - map virtual addresses to physical
107 * @address: address to remap
108 *
109 * The returned physical address is the physical (CPU) mapping for
110 * the memory address given. It is only valid to use this function on
111 * addresses directly mapped or allocated via kmalloc.
112 *
113 * This function does not give bus mappings for DMA transfers. In
114 * almost all conceivable cases a device driver should not be using
115 * this function
116 */
117 static inline unsigned long virt_to_phys(volatile const void *address)
118 {
119 return (unsigned long)address - PAGE_OFFSET + PHYS_OFFSET;
120 }
121
122 /*
123 * phys_to_virt - map physical address to virtual
124 * @address: address to remap
125 *
126 * The returned virtual address is a current CPU mapping for
127 * the memory address given. It is only valid to use this function on
128 * addresses that have a kernel mapping
129 *
130 * This function does not handle bus mappings for DMA transfers. In
131 * almost all conceivable cases a device driver should not be using
132 * this function
133 */
134 static inline void * phys_to_virt(unsigned long address)
135 {
136 return (void *)(address + PAGE_OFFSET - PHYS_OFFSET);
137 }
138
139 /*
140 * ISA I/O bus memory addresses are 1:1 with the physical address.
141 */
142 static inline unsigned long isa_virt_to_bus(volatile void * address)
143 {
144 return (unsigned long)address - PAGE_OFFSET;
145 }
146
147 static inline void * isa_bus_to_virt(unsigned long address)
148 {
149 return (void *)(address + PAGE_OFFSET);
150 }
151
152 #define isa_page_to_bus page_to_phys
153
154 /*
155 * However PCI ones are not necessarily 1:1 and therefore these interfaces
156 * are forbidden in portable PCI drivers.
157 *
158 * Allow them for x86 for legacy drivers, though.
159 */
160 #define virt_to_bus virt_to_phys
161 #define bus_to_virt phys_to_virt
162
163 /*
164 * Change "struct page" to physical address.
165 */
166 #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
167
168 extern void __iomem * __ioremap(phys_t offset, phys_t size, unsigned long flags);
169 extern void __iounmap(const volatile void __iomem *addr);
170
171 static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
172 unsigned long flags)
173 {
174 void __iomem *addr = plat_ioremap(offset, size, flags);
175
176 if (addr)
177 return addr;
178
179 #define __IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL))
180
181 if (cpu_has_64bit_addresses) {
182 u64 base = UNCAC_BASE;
183
184 /*
185 * R10000 supports a 2 bit uncached attribute therefore
186 * UNCAC_BASE may not equal IO_BASE.
187 */
188 if (flags == _CACHE_UNCACHED)
189 base = (u64) IO_BASE;
190 return (void __iomem *) (unsigned long) (base + offset);
191 } else if (__builtin_constant_p(offset) &&
192 __builtin_constant_p(size) && __builtin_constant_p(flags)) {
193 phys_t phys_addr, last_addr;
194
195 phys_addr = fixup_bigphys_addr(offset, size);
196
197 /* Don't allow wraparound or zero size. */
198 last_addr = phys_addr + size - 1;
199 if (!size || last_addr < phys_addr)
200 return NULL;
201
202 /*
203 * Map uncached objects in the low 512MB of address
204 * space using KSEG1.
205 */
206 if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) &&
207 flags == _CACHE_UNCACHED)
208 return (void __iomem *)
209 (unsigned long)CKSEG1ADDR(phys_addr);
210 }
211
212 return __ioremap(offset, size, flags);
213
214 #undef __IS_LOW512
215 }
216
217 /*
218 * ioremap - map bus memory into CPU space
219 * @offset: bus address of the memory
220 * @size: size of the resource to map
221 *
222 * ioremap performs a platform specific sequence of operations to
223 * make bus memory CPU accessible via the readb/readw/readl/writeb/
224 * writew/writel functions and the other mmio helpers. The returned
225 * address is not guaranteed to be usable directly as a virtual
226 * address.
227 */
228 #define ioremap(offset, size) \
229 __ioremap_mode((offset), (size), _CACHE_UNCACHED)
230
231 /*
232 * ioremap_nocache - map bus memory into CPU space
233 * @offset: bus address of the memory
234 * @size: size of the resource to map
235 *
236 * ioremap_nocache performs a platform specific sequence of operations to
237 * make bus memory CPU accessible via the readb/readw/readl/writeb/
238 * writew/writel functions and the other mmio helpers. The returned
239 * address is not guaranteed to be usable directly as a virtual
240 * address.
241 *
242 * This version of ioremap ensures that the memory is marked uncachable
243 * on the CPU as well as honouring existing caching rules from things like
244 * the PCI bus. Note that there are other caches and buffers on many
245 * busses. In particular driver authors should read up on PCI writes
246 *
247 * It's useful if some control registers are in such an area and
248 * write combining or read caching is not desirable:
249 */
250 #define ioremap_nocache(offset, size) \
251 __ioremap_mode((offset), (size), _CACHE_UNCACHED)
252
253 /*
254 * ioremap_cachable - map bus memory into CPU space
255 * @offset: bus address of the memory
256 * @size: size of the resource to map
257 *
258 * ioremap_nocache performs a platform specific sequence of operations to
259 * make bus memory CPU accessible via the readb/readw/readl/writeb/
260 * writew/writel functions and the other mmio helpers. The returned
261 * address is not guaranteed to be usable directly as a virtual
262 * address.
263 *
264 * This version of ioremap ensures that the memory is marked cachable by
265 * the CPU. Also enables full write-combining. Useful for some
266 * memory-like regions on I/O busses.
267 */
268 #define ioremap_cachable(offset, size) \
269 __ioremap_mode((offset), (size), _page_cachable_default)
270
271 /*
272 * These two are MIPS specific ioremap variant. ioremap_cacheable_cow
273 * requests a cachable mapping, ioremap_uncached_accelerated requests a
274 * mapping using the uncached accelerated mode which isn't supported on
275 * all processors.
276 */
277 #define ioremap_cacheable_cow(offset, size) \
278 __ioremap_mode((offset), (size), _CACHE_CACHABLE_COW)
279 #define ioremap_uncached_accelerated(offset, size) \
280 __ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED)
281
282 static inline void iounmap(const volatile void __iomem *addr)
283 {
284 if (plat_iounmap(addr))
285 return;
286
287 #define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1)
288
289 if (cpu_has_64bit_addresses ||
290 (__builtin_constant_p(addr) && __IS_KSEG1(addr)))
291 return;
292
293 __iounmap(addr);
294
295 #undef __IS_KSEG1
296 }
297
298 #ifdef CONFIG_CPU_CAVIUM_OCTEON
299 #define war_octeon_io_reorder_wmb() wmb()
300 #else
301 #define war_octeon_io_reorder_wmb() do { } while (0)
302 #endif
303
304 #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \
305 \
306 static inline void pfx##write##bwlq(type val, \
307 volatile void __iomem *mem) \
308 { \
309 volatile type *__mem; \
310 type __val; \
311 \
312 war_octeon_io_reorder_wmb(); \
313 \
314 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
315 \
316 __val = pfx##ioswab##bwlq(__mem, val); \
317 \
318 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
319 *__mem = __val; \
320 else if (cpu_has_64bits) { \
321 unsigned long __flags; \
322 type __tmp; \
323 \
324 if (irq) \
325 local_irq_save(__flags); \
326 __asm__ __volatile__( \
327 ".set mips3" "\t\t# __writeq""\n\t" \
328 "dsll32 %L0, %L0, 0" "\n\t" \
329 "dsrl32 %L0, %L0, 0" "\n\t" \
330 "dsll32 %M0, %M0, 0" "\n\t" \
331 "or %L0, %L0, %M0" "\n\t" \
332 "sd %L0, %2" "\n\t" \
333 ".set mips0" "\n" \
334 : "=r" (__tmp) \
335 : "0" (__val), "m" (*__mem)); \
336 if (irq) \
337 local_irq_restore(__flags); \
338 } else \
339 BUG(); \
340 } \
341 \
342 static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
343 { \
344 volatile type *__mem; \
345 type __val; \
346 \
347 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
348 \
349 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
350 __val = *__mem; \
351 else if (cpu_has_64bits) { \
352 unsigned long __flags; \
353 \
354 if (irq) \
355 local_irq_save(__flags); \
356 __asm__ __volatile__( \
357 ".set mips3" "\t\t# __readq" "\n\t" \
358 "ld %L0, %1" "\n\t" \
359 "dsra32 %M0, %L0, 0" "\n\t" \
360 "sll %L0, %L0, 0" "\n\t" \
361 ".set mips0" "\n" \
362 : "=r" (__val) \
363 : "m" (*__mem)); \
364 if (irq) \
365 local_irq_restore(__flags); \
366 } else { \
367 __val = 0; \
368 BUG(); \
369 } \
370 \
371 return pfx##ioswab##bwlq(__mem, __val); \
372 }
373
374 #define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \
375 \
376 static inline void pfx##out##bwlq##p(type val, unsigned long port) \
377 { \
378 volatile type *__addr; \
379 type __val; \
380 \
381 war_octeon_io_reorder_wmb(); \
382 \
383 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
384 \
385 __val = pfx##ioswab##bwlq(__addr, val); \
386 \
387 /* Really, we want this to be atomic */ \
388 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
389 \
390 *__addr = __val; \
391 slow; \
392 } \
393 \
394 static inline type pfx##in##bwlq##p(unsigned long port) \
395 { \
396 volatile type *__addr; \
397 type __val; \
398 \
399 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
400 \
401 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
402 \
403 __val = *__addr; \
404 slow; \
405 \
406 return pfx##ioswab##bwlq(__addr, __val); \
407 }
408
409 #define __BUILD_MEMORY_PFX(bus, bwlq, type) \
410 \
411 __BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)
412
413 #define BUILDIO_MEM(bwlq, type) \
414 \
415 __BUILD_MEMORY_PFX(__raw_, bwlq, type) \
416 __BUILD_MEMORY_PFX(, bwlq, type) \
417 __BUILD_MEMORY_PFX(__mem_, bwlq, type) \
418
419 BUILDIO_MEM(b, u8)
420 BUILDIO_MEM(w, u16)
421 BUILDIO_MEM(l, u32)
422 BUILDIO_MEM(q, u64)
423
424 #define __BUILD_IOPORT_PFX(bus, bwlq, type) \
425 __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \
426 __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
427
428 #define BUILDIO_IOPORT(bwlq, type) \
429 __BUILD_IOPORT_PFX(, bwlq, type) \
430 __BUILD_IOPORT_PFX(__mem_, bwlq, type)
431
432 BUILDIO_IOPORT(b, u8)
433 BUILDIO_IOPORT(w, u16)
434 BUILDIO_IOPORT(l, u32)
435 #ifdef CONFIG_64BIT
436 BUILDIO_IOPORT(q, u64)
437 #endif
438
439 #define __BUILDIO(bwlq, type) \
440 \
441 __BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0)
442
443 __BUILDIO(q, u64)
444
445 #define readb_relaxed readb
446 #define readw_relaxed readw
447 #define readl_relaxed readl
448 #define readq_relaxed readq
449
450 #define readb_be(addr) \
451 __raw_readb((__force unsigned *)(addr))
452 #define readw_be(addr) \
453 be16_to_cpu(__raw_readw((__force unsigned *)(addr)))
454 #define readl_be(addr) \
455 be32_to_cpu(__raw_readl((__force unsigned *)(addr)))
456 #define readq_be(addr) \
457 be64_to_cpu(__raw_readq((__force unsigned *)(addr)))
458
459 #define writeb_be(val, addr) \
460 __raw_writeb((val), (__force unsigned *)(addr))
461 #define writew_be(val, addr) \
462 __raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr))
463 #define writel_be(val, addr) \
464 __raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr))
465 #define writeq_be(val, addr) \
466 __raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr))
467
468 /*
469 * Some code tests for these symbols
470 */
471 #define readq readq
472 #define writeq writeq
473
474 #define __BUILD_MEMORY_STRING(bwlq, type) \
475 \
476 static inline void writes##bwlq(volatile void __iomem *mem, \
477 const void *addr, unsigned int count) \
478 { \
479 const volatile type *__addr = addr; \
480 \
481 while (count--) { \
482 __mem_write##bwlq(*__addr, mem); \
483 __addr++; \
484 } \
485 } \
486 \
487 static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \
488 unsigned int count) \
489 { \
490 volatile type *__addr = addr; \
491 \
492 while (count--) { \
493 *__addr = __mem_read##bwlq(mem); \
494 __addr++; \
495 } \
496 }
497
498 #define __BUILD_IOPORT_STRING(bwlq, type) \
499 \
500 static inline void outs##bwlq(unsigned long port, const void *addr, \
501 unsigned int count) \
502 { \
503 const volatile type *__addr = addr; \
504 \
505 while (count--) { \
506 __mem_out##bwlq(*__addr, port); \
507 __addr++; \
508 } \
509 } \
510 \
511 static inline void ins##bwlq(unsigned long port, void *addr, \
512 unsigned int count) \
513 { \
514 volatile type *__addr = addr; \
515 \
516 while (count--) { \
517 *__addr = __mem_in##bwlq(port); \
518 __addr++; \
519 } \
520 }
521
522 #define BUILDSTRING(bwlq, type) \
523 \
524 __BUILD_MEMORY_STRING(bwlq, type) \
525 __BUILD_IOPORT_STRING(bwlq, type)
526
527 BUILDSTRING(b, u8)
528 BUILDSTRING(w, u16)
529 BUILDSTRING(l, u32)
530 #ifdef CONFIG_64BIT
531 BUILDSTRING(q, u64)
532 #endif
533
534
535 #ifdef CONFIG_CPU_CAVIUM_OCTEON
536 #define mmiowb() wmb()
537 #else
538 /* Depends on MIPS II instruction set */
539 #define mmiowb() asm volatile ("sync" ::: "memory")
540 #endif
541
542 static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
543 {
544 memset((void __force *) addr, val, count);
545 }
546 static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
547 {
548 memcpy(dst, (void __force *) src, count);
549 }
550 static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
551 {
552 memcpy((void __force *) dst, src, count);
553 }
554
555 /*
556 * The caches on some architectures aren't dma-coherent and have need to
557 * handle this in software. There are three types of operations that
558 * can be applied to dma buffers.
559 *
560 * - dma_cache_wback_inv(start, size) makes caches and coherent by
561 * writing the content of the caches back to memory, if necessary.
562 * The function also invalidates the affected part of the caches as
563 * necessary before DMA transfers from outside to memory.
564 * - dma_cache_wback(start, size) makes caches and coherent by
565 * writing the content of the caches back to memory, if necessary.
566 * The function also invalidates the affected part of the caches as
567 * necessary before DMA transfers from outside to memory.
568 * - dma_cache_inv(start, size) invalidates the affected parts of the
569 * caches. Dirty lines of the caches may be written back or simply
570 * be discarded. This operation is necessary before dma operations
571 * to the memory.
572 *
573 * This API used to be exported; it now is for arch code internal use only.
574 */
575 #ifdef CONFIG_DMA_NONCOHERENT
576
577 extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
578 extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
579 extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
580
581 #define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start, size)
582 #define dma_cache_wback(start, size) _dma_cache_wback(start, size)
583 #define dma_cache_inv(start, size) _dma_cache_inv(start, size)
584
585 #else /* Sane hardware */
586
587 #define dma_cache_wback_inv(start,size) \
588 do { (void) (start); (void) (size); } while (0)
589 #define dma_cache_wback(start,size) \
590 do { (void) (start); (void) (size); } while (0)
591 #define dma_cache_inv(start,size) \
592 do { (void) (start); (void) (size); } while (0)
593
594 #endif /* CONFIG_DMA_NONCOHERENT */
595
596 /*
597 * Read a 32-bit register that requires a 64-bit read cycle on the bus.
598 * Avoid interrupt mucking, just adjust the address for 4-byte access.
599 * Assume the addresses are 8-byte aligned.
600 */
601 #ifdef __MIPSEB__
602 #define __CSR_32_ADJUST 4
603 #else
604 #define __CSR_32_ADJUST 0
605 #endif
606
607 #define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
608 #define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
609
610 /*
611 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
612 * access
613 */
614 #define xlate_dev_mem_ptr(p) __va(p)
615
616 /*
617 * Convert a virtual cached pointer to an uncached pointer
618 */
619 #define xlate_dev_kmem_ptr(p) p
620
621 #endif /* _ASM_IO_H */
linux-next