Add linux-next specific files for 20110831
[linux-2.6/next.git] / arch / powerpc / boot / dts / mpc8610_hpcd.dts
blob83c3218cb4da2717b9a375ab904ddc8879e9b038
1 /*
2  * MPC8610 HPCD Device Tree Source
3  *
4  * Copyright 2007-2008 Freescale Semiconductor Inc.
5  *
6  * This program is free software; you can redistribute  it and/or modify it
7  * under the terms of the GNU General Public License Version 2 as published
8  * by the Free Software Foundation.
9  */
11 /dts-v1/;
13 / {
14         model = "MPC8610HPCD";
15         compatible = "fsl,MPC8610HPCD";
16         #address-cells = <1>;
17         #size-cells = <1>;
19         aliases {
20                 serial0 = &serial0;
21                 serial1 = &serial1;
22                 pci0 = &pci0;
23                 pci1 = &pci1;
24                 pci2 = &pci2;
25         };
27         cpus {
28                 #address-cells = <1>;
29                 #size-cells = <0>;
31                 PowerPC,8610@0 {
32                         device_type = "cpu";
33                         reg = <0>;
34                         d-cache-line-size = <32>;
35                         i-cache-line-size = <32>;
36                         d-cache-size = <32768>;         // L1
37                         i-cache-size = <32768>;         // L1
38                         sleep = <&pmc 0x00008000 0      // core
39                                  &pmc 0x00004000 0>;    // timebase
40                         timebase-frequency = <0>;       // From uboot
41                         bus-frequency = <0>;            // From uboot
42                         clock-frequency = <0>;          // From uboot
43                 };
44         };
46         memory {
47                 device_type = "memory";
48                 reg = <0x00000000 0x20000000>;  // 512M at 0x0
49         };
51         localbus@e0005000 {
52                 #address-cells = <2>;
53                 #size-cells = <1>;
54                 compatible = "fsl,mpc8610-elbc", "fsl,elbc", "simple-bus";
55                 reg = <0xe0005000 0x1000>;
56                 interrupts = <19 2>;
57                 interrupt-parent = <&mpic>;
58                 ranges = <0 0 0xf8000000 0x08000000
59                           1 0 0xf0000000 0x08000000
60                           2 0 0xe8400000 0x00008000
61                           4 0 0xe8440000 0x00008000
62                           5 0 0xe8480000 0x00008000
63                           6 0 0xe84c0000 0x00008000
64                           3 0 0xe8000000 0x00000020>;
65                 sleep = <&pmc 0x08000000 0>;
67                 flash@0,0 {
68                         compatible = "cfi-flash";
69                         reg = <0 0 0x8000000>;
70                         bank-width = <2>;
71                         device-width = <1>;
72                 };
74                 flash@1,0 {
75                         compatible = "cfi-flash";
76                         reg = <1 0 0x8000000>;
77                         bank-width = <2>;
78                         device-width = <1>;
79                 };
81                 flash@2,0 {
82                         compatible = "fsl,mpc8610-fcm-nand",
83                                      "fsl,elbc-fcm-nand";
84                         reg = <2 0 0x8000>;
85                 };
87                 flash@4,0 {
88                         compatible = "fsl,mpc8610-fcm-nand",
89                                      "fsl,elbc-fcm-nand";
90                         reg = <4 0 0x8000>;
91                 };
93                 flash@5,0 {
94                         compatible = "fsl,mpc8610-fcm-nand",
95                                      "fsl,elbc-fcm-nand";
96                         reg = <5 0 0x8000>;
97                 };
99                 flash@6,0 {
100                         compatible = "fsl,mpc8610-fcm-nand",
101                                      "fsl,elbc-fcm-nand";
102                         reg = <6 0 0x8000>;
103                 };
105                 board-control@3,0 {
106                         #address-cells = <1>;
107                         #size-cells = <1>;
108                         compatible = "fsl,fpga-pixis";
109                         reg = <3 0 0x20>;
110                         ranges = <0 3 0 0x20>;
111                         interrupt-parent = <&mpic>;
112                         interrupts = <8 8>;
114                         sdcsr_pio: gpio-controller@a {
115                                 #gpio-cells = <2>;
116                                 compatible = "fsl,fpga-pixis-gpio-bank";
117                                 reg = <0xa 1>;
118                                 gpio-controller;
119                         };
120                 };
121         };
123         soc@e0000000 {
124                 #address-cells = <1>;
125                 #size-cells = <1>;
126                 #interrupt-cells = <2>;
127                 device_type = "soc";
128                 compatible = "fsl,mpc8610-immr", "simple-bus";
129                 ranges = <0x0 0xe0000000 0x00100000>;
130                 bus-frequency = <0>;
132                 mcm-law@0 {
133                         compatible = "fsl,mcm-law";
134                         reg = <0x0 0x1000>;
135                         fsl,num-laws = <10>;
136                 };
138                 mcm@1000 {
139                         compatible = "fsl,mpc8610-mcm", "fsl,mcm";
140                         reg = <0x1000 0x1000>;
141                         interrupts = <17 2>;
142                         interrupt-parent = <&mpic>;
143                 };
145                 i2c@3000 {
146                         #address-cells = <1>;
147                         #size-cells = <0>;
148                         cell-index = <0>;
149                         compatible = "fsl-i2c";
150                         reg = <0x3000 0x100>;
151                         interrupts = <43 2>;
152                         interrupt-parent = <&mpic>;
153                         dfsrr;
155                         cs4270:codec@4f {
156                                 compatible = "cirrus,cs4270";
157                                 reg = <0x4f>;
158                                 /* MCLK source is a stand-alone oscillator */
159                                 clock-frequency = <12288000>;
160                         };
161                 };
163                 i2c@3100 {
164                         #address-cells = <1>;
165                         #size-cells = <0>;
166                         cell-index = <1>;
167                         compatible = "fsl-i2c";
168                         reg = <0x3100 0x100>;
169                         interrupts = <43 2>;
170                         interrupt-parent = <&mpic>;
171                         sleep = <&pmc 0x00000004 0>;
172                         dfsrr;
173                 };
175                 serial0: serial@4500 {
176                         cell-index = <0>;
177                         device_type = "serial";
178                         compatible = "ns16550";
179                         reg = <0x4500 0x100>;
180                         clock-frequency = <0>;
181                         interrupts = <42 2>;
182                         interrupt-parent = <&mpic>;
183                         sleep = <&pmc 0x00000002 0>;
184                 };
186                 serial1: serial@4600 {
187                         cell-index = <1>;
188                         device_type = "serial";
189                         compatible = "ns16550";
190                         reg = <0x4600 0x100>;
191                         clock-frequency = <0>;
192                         interrupts = <42 2>;
193                         interrupt-parent = <&mpic>;
194                         sleep = <&pmc 0x00000008 0>;
195                 };
197                 spi@7000 {
198                         #address-cells = <1>;
199                         #size-cells = <0>;
200                         compatible = "fsl,mpc8610-spi", "fsl,spi";
201                         reg = <0x7000 0x40>;
202                         cell-index = <0>;
203                         interrupts = <59 2>;
204                         interrupt-parent = <&mpic>;
205                         mode = "cpu";
206                         gpios = <&sdcsr_pio 7 0>;
207                         sleep = <&pmc 0x00000800 0>;
209                         mmc-slot@0 {
210                                 compatible = "fsl,mpc8610hpcd-mmc-slot",
211                                              "mmc-spi-slot";
212                                 reg = <0>;
213                                 gpios = <&sdcsr_pio 0 1   /* nCD */
214                                          &sdcsr_pio 1 0>; /*  WP */
215                                 voltage-ranges = <3300 3300>;
216                                 spi-max-frequency = <50000000>;
217                         };
218                 };
220                 display@2c000 {
221                         compatible = "fsl,diu";
222                         reg = <0x2c000 100>;
223                         interrupts = <72 2>;
224                         interrupt-parent = <&mpic>;
225                         sleep = <&pmc 0x04000000 0>;
226                 };
228                 mpic: interrupt-controller@40000 {
229                         interrupt-controller;
230                         #address-cells = <0>;
231                         #interrupt-cells = <2>;
232                         reg = <0x40000 0x40000>;
233                         compatible = "chrp,open-pic";
234                         device_type = "open-pic";
235                 };
237                 msi@41600 {
238                         compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
239                         reg = <0x41600 0x80>;
240                         msi-available-ranges = <0 0x100>;
241                         interrupts = <
242                                 0xe0 0
243                                 0xe1 0
244                                 0xe2 0
245                                 0xe3 0
246                                 0xe4 0
247                                 0xe5 0
248                                 0xe6 0
249                                 0xe7 0>;
250                         interrupt-parent = <&mpic>;
251                 };
253                 global-utilities@e0000 {
254                         #address-cells = <1>;
255                         #size-cells = <1>;
256                         compatible = "fsl,mpc8610-guts";
257                         reg = <0xe0000 0x1000>;
258                         ranges = <0 0xe0000 0x1000>;
259                         fsl,has-rstcr;
261                         pmc: power@70 {
262                                 compatible = "fsl,mpc8610-pmc",
263                                              "fsl,mpc8641d-pmc";
264                                 reg = <0x70 0x20>;
265                         };
266                 };
268                 wdt@e4000 {
269                         compatible = "fsl,mpc8610-wdt";
270                         reg = <0xe4000 0x100>;
271                 };
273                 ssi@16000 {
274                         compatible = "fsl,mpc8610-ssi";
275                         cell-index = <0>;
276                         reg = <0x16000 0x100>;
277                         interrupt-parent = <&mpic>;
278                         interrupts = <62 2>;
279                         fsl,mode = "i2s-slave";
280                         codec-handle = <&cs4270>;
281                         fsl,playback-dma = <&dma00>;
282                         fsl,capture-dma = <&dma01>;
283                         fsl,fifo-depth = <8>;
284                         sleep = <&pmc 0 0x08000000>;
285                 };
287                 ssi@16100 {
288                         compatible = "fsl,mpc8610-ssi";
289                         status = "disabled";
290                         cell-index = <1>;
291                         reg = <0x16100 0x100>;
292                         interrupt-parent = <&mpic>;
293                         interrupts = <63 2>;
294                         fsl,fifo-depth = <8>;
295                         sleep = <&pmc 0 0x04000000>;
296                 };
298                 dma@21300 {
299                         #address-cells = <1>;
300                         #size-cells = <1>;
301                         compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
302                         cell-index = <0>;
303                         reg = <0x21300 0x4>; /* DMA general status register */
304                         ranges = <0x0 0x21100 0x200>;
305                         sleep = <&pmc 0x00000400 0>;
307                         dma00: dma-channel@0 {
308                                 compatible = "fsl,mpc8610-dma-channel",
309                                         "fsl,ssi-dma-channel";
310                                 cell-index = <0>;
311                                 reg = <0x0 0x80>;
312                                 interrupt-parent = <&mpic>;
313                                 interrupts = <20 2>;
314                         };
315                         dma01: dma-channel@1 {
316                                 compatible = "fsl,mpc8610-dma-channel",
317                                         "fsl,ssi-dma-channel";
318                                 cell-index = <1>;
319                                 reg = <0x80 0x80>;
320                                 interrupt-parent = <&mpic>;
321                                 interrupts = <21 2>;
322                         };
323                         dma-channel@2 {
324                                 compatible = "fsl,mpc8610-dma-channel",
325                                         "fsl,eloplus-dma-channel";
326                                 cell-index = <2>;
327                                 reg = <0x100 0x80>;
328                                 interrupt-parent = <&mpic>;
329                                 interrupts = <22 2>;
330                         };
331                         dma-channel@3 {
332                                 compatible = "fsl,mpc8610-dma-channel",
333                                         "fsl,eloplus-dma-channel";
334                                 cell-index = <3>;
335                                 reg = <0x180 0x80>;
336                                 interrupt-parent = <&mpic>;
337                                 interrupts = <23 2>;
338                         };
339                 };
341                 dma@c300 {
342                         #address-cells = <1>;
343                         #size-cells = <1>;
344                         compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
345                         cell-index = <1>;
346                         reg = <0xc300 0x4>; /* DMA general status register */
347                         ranges = <0x0 0xc100 0x200>;
348                         sleep = <&pmc 0x00000200 0>;
350                         dma-channel@0 {
351                                 compatible = "fsl,mpc8610-dma-channel",
352                                         "fsl,eloplus-dma-channel";
353                                 cell-index = <0>;
354                                 reg = <0x0 0x80>;
355                                 interrupt-parent = <&mpic>;
356                                 interrupts = <76 2>;
357                         };
358                         dma-channel@1 {
359                                 compatible = "fsl,mpc8610-dma-channel",
360                                         "fsl,eloplus-dma-channel";
361                                 cell-index = <1>;
362                                 reg = <0x80 0x80>;
363                                 interrupt-parent = <&mpic>;
364                                 interrupts = <77 2>;
365                         };
366                         dma-channel@2 {
367                                 compatible = "fsl,mpc8610-dma-channel",
368                                         "fsl,eloplus-dma-channel";
369                                 cell-index = <2>;
370                                 reg = <0x100 0x80>;
371                                 interrupt-parent = <&mpic>;
372                                 interrupts = <78 2>;
373                         };
374                         dma-channel@3 {
375                                 compatible = "fsl,mpc8610-dma-channel",
376                                         "fsl,eloplus-dma-channel";
377                                 cell-index = <3>;
378                                 reg = <0x180 0x80>;
379                                 interrupt-parent = <&mpic>;
380                                 interrupts = <79 2>;
381                         };
382                 };
384         };
386         pci0: pci@e0008000 {
387                 compatible = "fsl,mpc8610-pci";
388                 device_type = "pci";
389                 #interrupt-cells = <1>;
390                 #size-cells = <2>;
391                 #address-cells = <3>;
392                 reg = <0xe0008000 0x1000>;
393                 bus-range = <0 0>;
394                 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
395                           0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
396                 sleep = <&pmc 0x80000000 0>;
397                 clock-frequency = <33333333>;
398                 interrupt-parent = <&mpic>;
399                 interrupts = <24 2>;
400                 interrupt-map-mask = <0xf800 0 0 7>;
401                 interrupt-map = <
402                         /* IDSEL 0x11 */
403                         0x8800 0 0 1 &mpic 4 1
404                         0x8800 0 0 2 &mpic 5 1
405                         0x8800 0 0 3 &mpic 6 1
406                         0x8800 0 0 4 &mpic 7 1
408                         /* IDSEL 0x12 */
409                         0x9000 0 0 1 &mpic 5 1
410                         0x9000 0 0 2 &mpic 6 1
411                         0x9000 0 0 3 &mpic 7 1
412                         0x9000 0 0 4 &mpic 4 1
413                         >;
414         };
416         pci1: pcie@e000a000 {
417                 compatible = "fsl,mpc8641-pcie";
418                 device_type = "pci";
419                 #interrupt-cells = <1>;
420                 #size-cells = <2>;
421                 #address-cells = <3>;
422                 reg = <0xe000a000 0x1000>;
423                 bus-range = <1 3>;
424                 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
425                           0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
426                 sleep = <&pmc 0x40000000 0>;
427                 clock-frequency = <33333333>;
428                 interrupt-parent = <&mpic>;
429                 interrupts = <26 2>;
430                 interrupt-map-mask = <0xf800 0 0 7>;
432                 interrupt-map = <
433                         /* IDSEL 0x1b */
434                         0xd800 0 0 1 &mpic 2 1
436                         /* IDSEL 0x1c*/
437                         0xe000 0 0 1 &mpic 1 1
438                         0xe000 0 0 2 &mpic 1 1
439                         0xe000 0 0 3 &mpic 1 1
440                         0xe000 0 0 4 &mpic 1 1
442                         /* IDSEL 0x1f */
443                         0xf800 0 0 1 &mpic 3 2
444                         0xf800 0 0 2 &mpic 0 1
445                 >;
447                 pcie@0 {
448                         reg = <0 0 0 0 0>;
449                         #size-cells = <2>;
450                         #address-cells = <3>;
451                         device_type = "pci";
452                         ranges = <0x02000000 0x0 0xa0000000
453                                   0x02000000 0x0 0xa0000000
454                                   0x0 0x10000000
455                                   0x01000000 0x0 0x00000000
456                                   0x01000000 0x0 0x00000000
457                                   0x0 0x00100000>;
458                         uli1575@0 {
459                                 reg = <0 0 0 0 0>;
460                                 #size-cells = <2>;
461                                 #address-cells = <3>;
462                                 ranges = <0x02000000 0x0 0xa0000000
463                                           0x02000000 0x0 0xa0000000
464                                           0x0 0x10000000
465                                           0x01000000 0x0 0x00000000
466                                           0x01000000 0x0 0x00000000
467                                           0x0 0x00100000>;
469                                 isa@1e {
470                                         device_type = "isa";
471                                         #size-cells = <1>;
472                                         #address-cells = <2>;
473                                         reg = <0xf000 0 0 0 0>;
474                                         ranges = <1 0 0x01000000 0 0
475                                                   0x00001000>;
477                                         rtc@70 {
478                                                 compatible = "pnpPNP,b00";
479                                                 reg = <1 0x70 2>;
480                                         };
481                                 };
482                         };
483                 };
484         };
486         pci2: pcie@e0009000 {
487                 #address-cells = <3>;
488                 #size-cells = <2>;
489                 #interrupt-cells = <1>;
490                 device_type = "pci";
491                 compatible = "fsl,mpc8641-pcie";
492                 reg = <0xe0009000 0x00001000>;
493                 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
494                           0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
495                 bus-range = <0 255>;
496                 interrupt-map-mask = <0xf800 0 0 7>;
497                 interrupt-map = <0x0000 0 0 1 &mpic 4 1
498                                  0x0000 0 0 2 &mpic 5 1
499                                  0x0000 0 0 3 &mpic 6 1
500                                  0x0000 0 0 4 &mpic 7 1>;
501                 interrupt-parent = <&mpic>;
502                 interrupts = <25 2>;
503                 sleep = <&pmc 0x20000000 0>;
504                 clock-frequency = <33333333>;
505         };