| blob | cabe0a453ae65c08af5315aa2d7e9af47a6149a9 |
1 /*
2 * P1010si Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
12 /dts-v1/;
13 / {
14 compatible = "fsl,P1010";
15 #address-cells = <2>;
16 #size-cells = <2>;
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
22 PowerPC,P1010@0 {
23 device_type = "cpu";
24 reg = <0x0>;
25 next-level-cache = <&L2>;
26 };
27 };
29 ifc@ffe1e000 {
30 #address-cells = <2>;
31 #size-cells = <1>;
32 compatible = "fsl,ifc", "simple-bus";
33 reg = <0x0 0xffe1e000 0 0x2000>;
34 interrupts = <16 2 19 2>;
35 interrupt-parent = <&mpic>;
36 };
38 soc@ffe00000 {
39 #address-cells = <1>;
40 #size-cells = <1>;
41 device_type = "soc";
42 compatible = "fsl,p1010-immr", "simple-bus";
43 ranges = <0x0 0x0 0xffe00000 0x100000>;
44 bus-frequency = <0>; // Filled out by uboot.
46 ecm-law@0 {
47 compatible = "fsl,ecm-law";
48 reg = <0x0 0x1000>;
49 fsl,num-laws = <12>;
50 };
52 ecm@1000 {
53 compatible = "fsl,p1010-ecm", "fsl,ecm";
54 reg = <0x1000 0x1000>;
55 interrupts = <16 2>;
56 interrupt-parent = <&mpic>;
57 };
59 memory-controller@2000 {
60 compatible = "fsl,p1010-memory-controller";
61 reg = <0x2000 0x1000>;
62 interrupt-parent = <&mpic>;
63 interrupts = <16 2>;
64 };
66 i2c@3000 {
67 #address-cells = <1>;
68 #size-cells = <0>;
69 cell-index = <0>;
70 compatible = "fsl-i2c";
71 reg = <0x3000 0x100>;
72 interrupts = <43 2>;
73 interrupt-parent = <&mpic>;
74 dfsrr;
75 };
77 i2c@3100 {
78 #address-cells = <1>;
79 #size-cells = <0>;
80 cell-index = <1>;
81 compatible = "fsl-i2c";
82 reg = <0x3100 0x100>;
83 interrupts = <43 2>;
84 interrupt-parent = <&mpic>;
85 dfsrr;
86 };
88 serial0: serial@4500 {
89 cell-index = <0>;
90 device_type = "serial";
91 compatible = "ns16550";
92 reg = <0x4500 0x100>;
93 clock-frequency = <0>;
94 interrupts = <42 2>;
95 interrupt-parent = <&mpic>;
96 };
98 serial1: serial@4600 {
99 cell-index = <1>;
100 device_type = "serial";
101 compatible = "ns16550";
102 reg = <0x4600 0x100>;
103 clock-frequency = <0>;
104 interrupts = <42 2>;
105 interrupt-parent = <&mpic>;
106 };
108 spi@7000 {
109 #address-cells = <1>;
110 #size-cells = <0>;
111 compatible = "fsl,mpc8536-espi";
112 reg = <0x7000 0x1000>;
113 interrupts = <59 0x2>;
114 interrupt-parent = <&mpic>;
115 fsl,espi-num-chipselects = <1>;
116 };
118 gpio: gpio-controller@f000 {
119 #gpio-cells = <2>;
120 compatible = "fsl,mpc8572-gpio";
121 reg = <0xf000 0x100>;
122 interrupts = <47 0x2>;
123 interrupt-parent = <&mpic>;
124 gpio-controller;
125 };
127 sata@18000 {
128 compatible = "fsl,pq-sata-v2";
129 reg = <0x18000 0x1000>;
130 cell-index = <1>;
131 interrupts = <74 0x2>;
132 interrupt-parent = <&mpic>;
133 };
135 sata@19000 {
136 compatible = "fsl,pq-sata-v2";
137 reg = <0x19000 0x1000>;
138 cell-index = <2>;
139 interrupts = <41 0x2>;
140 interrupt-parent = <&mpic>;
141 };
143 can0: can@1c000 {
144 compatible = "fsl,p1010-flexcan";
145 reg = <0x1c000 0x1000>;
146 interrupts = <48 0x2>;
147 interrupt-parent = <&mpic>;
148 };
150 can1: can@1d000 {
151 compatible = "fsl,p1010-flexcan";
152 reg = <0x1d000 0x1000>;
153 interrupts = <61 0x2>;
154 interrupt-parent = <&mpic>;
155 };
157 L2: l2-cache-controller@20000 {
158 compatible = "fsl,p1010-l2-cache-controller",
159 "fsl,p1014-l2-cache-controller";
160 reg = <0x20000 0x1000>;
161 cache-line-size = <32>; // 32 bytes
162 cache-size = <0x40000>; // L2,256K
163 interrupt-parent = <&mpic>;
164 interrupts = <16 2>;
165 };
167 dma@21300 {
168 #address-cells = <1>;
169 #size-cells = <1>;
170 compatible = "fsl,p1010-dma", "fsl,eloplus-dma";
171 reg = <0x21300 0x4>;
172 ranges = <0x0 0x21100 0x200>;
173 cell-index = <0>;
174 dma-channel@0 {
175 compatible = "fsl,p1010-dma-channel", "fsl,eloplus-dma-channel";
176 reg = <0x0 0x80>;
177 cell-index = <0>;
178 interrupt-parent = <&mpic>;
179 interrupts = <20 2>;
180 };
181 dma-channel@80 {
182 compatible = "fsl,p1010-dma-channel", "fsl,eloplus-dma-channel";
183 reg = <0x80 0x80>;
184 cell-index = <1>;
185 interrupt-parent = <&mpic>;
186 interrupts = <21 2>;
187 };
188 dma-channel@100 {
189 compatible = "fsl,p1010-dma-channel", "fsl,eloplus-dma-channel";
190 reg = <0x100 0x80>;
191 cell-index = <2>;
192 interrupt-parent = <&mpic>;
193 interrupts = <22 2>;
194 };
195 dma-channel@180 {
196 compatible = "fsl,p1010-dma-channel", "fsl,eloplus-dma-channel";
197 reg = <0x180 0x80>;
198 cell-index = <3>;
199 interrupt-parent = <&mpic>;
200 interrupts = <23 2>;
201 };
202 };
204 usb@22000 {
205 compatible = "fsl-usb2-dr";
206 reg = <0x22000 0x1000>;
207 #address-cells = <1>;
208 #size-cells = <0>;
209 interrupt-parent = <&mpic>;
210 interrupts = <28 0x2>;
211 dr_mode = "host";
212 };
214 mdio@24000 {
215 #address-cells = <1>;
216 #size-cells = <0>;
217 compatible = "fsl,etsec2-mdio";
218 reg = <0x24000 0x1000 0xb0030 0x4>;
219 };
221 mdio@25000 {
222 #address-cells = <1>;
223 #size-cells = <0>;
224 compatible = "fsl,etsec2-tbi";
225 reg = <0x25000 0x1000 0xb1030 0x4>;
226 tbi0: tbi-phy@11 {
227 reg = <0x11>;
228 device_type = "tbi-phy";
229 };
230 };
232 mdio@26000 {
233 #address-cells = <1>;
234 #size-cells = <0>;
235 compatible = "fsl,etsec2-tbi";
236 reg = <0x26000 0x1000 0xb1030 0x4>;
237 tbi1: tbi-phy@11 {
238 reg = <0x11>;
239 device_type = "tbi-phy";
240 };
241 };
243 sdhci@2e000 {
244 compatible = "fsl,esdhc";
245 reg = <0x2e000 0x1000>;
246 interrupts = <72 0x8>;
247 interrupt-parent = <&mpic>;
248 /* Filled in by U-Boot */
249 clock-frequency = <0>;
250 fsl,sdhci-auto-cmd12;
251 };
253 enet0: ethernet@b0000 {
254 #address-cells = <1>;
255 #size-cells = <1>;
256 device_type = "network";
257 model = "eTSEC";
258 compatible = "fsl,etsec2";
259 fsl,num_rx_queues = <0x8>;
260 fsl,num_tx_queues = <0x8>;
261 local-mac-address = [ 00 00 00 00 00 00 ];
262 interrupt-parent = <&mpic>;
264 queue-group@0 {
265 #address-cells = <1>;
266 #size-cells = <1>;
267 reg = <0xb0000 0x1000>;
268 fsl,rx-bit-map = <0xff>;
269 fsl,tx-bit-map = <0xff>;
270 interrupts = <29 2 30 2 34 2>;
271 };
273 };
275 enet1: ethernet@b1000 {
276 #address-cells = <1>;
277 #size-cells = <1>;
278 device_type = "network";
279 model = "eTSEC";
280 compatible = "fsl,etsec2";
281 fsl,num_rx_queues = <0x8>;
282 fsl,num_tx_queues = <0x8>;
283 local-mac-address = [ 00 00 00 00 00 00 ];
284 interrupt-parent = <&mpic>;
286 queue-group@0 {
287 #address-cells = <1>;
288 #size-cells = <1>;
289 reg = <0xb1000 0x1000>;
290 fsl,rx-bit-map = <0xff>;
291 fsl,tx-bit-map = <0xff>;
292 interrupts = <35 2 36 2 40 2>;
293 };
295 };
297 enet2: ethernet@b2000 {
298 #address-cells = <1>;
299 #size-cells = <1>;
300 device_type = "network";
301 model = "eTSEC";
302 compatible = "fsl,etsec2";
303 fsl,num_rx_queues = <0x8>;
304 fsl,num_tx_queues = <0x8>;
305 local-mac-address = [ 00 00 00 00 00 00 ];
306 interrupt-parent = <&mpic>;
308 queue-group@0 {
309 #address-cells = <1>;
310 #size-cells = <1>;
311 reg = <0xb2000 0x1000>;
312 fsl,rx-bit-map = <0xff>;
313 fsl,tx-bit-map = <0xff>;
314 interrupts = <31 2 32 2 33 2>;
315 };
317 };
319 mpic: pic@40000 {
320 interrupt-controller;
321 #address-cells = <0>;
322 #interrupt-cells = <2>;
323 reg = <0x40000 0x40000>;
324 compatible = "chrp,open-pic";
325 device_type = "open-pic";
326 };
328 msi@41600 {
329 compatible = "fsl,p1010-msi", "fsl,mpic-msi";
330 reg = <0x41600 0x80>;
331 msi-available-ranges = <0 0x100>;
332 interrupts = <
333 0xe0 0
334 0xe1 0
335 0xe2 0
336 0xe3 0
337 0xe4 0
338 0xe5 0
339 0xe6 0
340 0xe7 0>;
341 interrupt-parent = <&mpic>;
342 };
344 global-utilities@e0000 { //global utilities block
345 compatible = "fsl,p1010-guts";
346 reg = <0xe0000 0x1000>;
347 fsl,has-rstcr;
348 };
349 };
351 pci0: pcie@ffe09000 {
352 compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3", "fsl,qoriq-pcie-v2.2";
353 device_type = "pci";
354 #size-cells = <2>;
355 #address-cells = <3>;
356 reg = <0 0xffe09000 0 0x1000>;
357 bus-range = <0 255>;
358 clock-frequency = <33333333>;
359 interrupt-parent = <&mpic>;
360 interrupts = <16 2>;
361 };
363 pci1: pcie@ffe0a000 {
364 compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3", "fsl,qoriq-pcie-v2.2";
365 device_type = "pci";
366 #size-cells = <2>;
367 #address-cells = <3>;
368 reg = <0 0xffe0a000 0 0x1000>;
369 bus-range = <0 255>;
370 clock-frequency = <33333333>;
371 interrupt-parent = <&mpic>;
372 interrupts = <16 2>;
373 };
374 };