arch/powerpc/include/asm/fsl_guts.h

   1 /**
   2  * Freecale 85xx and 86xx Global Utilties register set
   3  *
   4  * Authors: Jeff Brown
   5  *          Timur Tabi <timur@freescale.com>
   6  *
   7  * Copyright 2004,2007 Freescale Semiconductor, Inc
   8  *
   9  * This program is free software; you can redistribute  it and/or modify it
  10  * under  the terms of  the GNU General  Public License as published by the
  11  * Free Software Foundation;  either version 2 of the  License, or (at your
  12  * option) any later version.
  13  */
  14
  15 #ifndef __ASM_POWERPC_FSL_GUTS_H__
  16 #define __ASM_POWERPC_FSL_GUTS_H__
  17 #ifdef __KERNEL__
  18
  19 /*
  20  * These #ifdefs are safe because it's not possible to build a kernel that
  21  * runs on e500 and e600 cores.
  22  */
  23
  24 #if !defined(CONFIG_PPC_85xx) && !defined(CONFIG_PPC_86xx)
  25 #error Only 85xx and 86xx SOCs are supported
  26 #endif
  27
  28 /**
  29  * Global Utility Registers.
  30  *
  31  * Not all registers defined in this structure are available on all chips, so
  32  * you are expected to know whether a given register actually exists on your
  33  * chip before you access it.
  34  *
  35  * Also, some registers are similar on different chips but have slightly
  36  * different names.  In these cases, one name is chosen to avoid extraneous
  37  * #ifdefs.
  38  */
  39 #ifdef CONFIG_PPC_85xx
  40 struct ccsr_guts_85xx {
  41 #else
  42 struct ccsr_guts_86xx {
  43 #endif
  44         __be32  porpllsr;       /* 0x.0000 - POR PLL Ratio Status Register */
  45         __be32  porbmsr;        /* 0x.0004 - POR Boot Mode Status Register */
  46         __be32  porimpscr;      /* 0x.0008 - POR I/O Impedance Status and Control Register */
  47         __be32  pordevsr;       /* 0x.000c - POR I/O Device Status Register */
  48         __be32  pordbgmsr;      /* 0x.0010 - POR Debug Mode Status Register */
  49         __be32  pordevsr2;      /* 0x.0014 - POR device status register 2 */
  50         u8      res018[0x20 - 0x18];
  51         __be32  porcir;         /* 0x.0020 - POR Configuration Information Register */
  52         u8      res024[0x30 - 0x24];
  53         __be32  gpiocr;         /* 0x.0030 - GPIO Control Register */
  54         u8      res034[0x40 - 0x34];
  55         __be32  gpoutdr;        /* 0x.0040 - General-Purpose Output Data Register */
  56         u8      res044[0x50 - 0x44];
  57         __be32  gpindr;         /* 0x.0050 - General-Purpose Input Data Register */
  58         u8      res054[0x60 - 0x54];
  59         __be32  pmuxcr;         /* 0x.0060 - Alternate Function Signal Multiplex Control */
  60         __be32  pmuxcr2;        /* 0x.0064 - Alternate function signal multiplex control 2 */
  61         __be32  dmuxcr;         /* 0x.0068 - DMA Mux Control Register */
  62         u8      res06c[0x70 - 0x6c];
  63         __be32  devdisr;        /* 0x.0070 - Device Disable Control */
  64         __be32  devdisr2;       /* 0x.0074 - Device Disable Control 2 */
  65         u8      res078[0x7c - 0x78];
  66         __be32  pmjcr;          /* 0x.007c - 4 Power Management Jog Control Register */
  67         __be32  powmgtcsr;      /* 0x.0080 - Power Management Status and Control Register */
  68         __be32  pmrccr;         /* 0x.0084 - Power Management Reset Counter Configuration Register */
  69         __be32  pmpdccr;        /* 0x.0088 - Power Management Power Down Counter Configuration Register */
  70         __be32  pmcdr;          /* 0x.008c - 4Power management clock disable register */
  71         __be32  mcpsumr;        /* 0x.0090 - Machine Check Summary Register */
  72         __be32  rstrscr;        /* 0x.0094 - Reset Request Status and Control Register */
  73         __be32  ectrstcr;       /* 0x.0098 - Exception reset control register */
  74         __be32  autorstsr;      /* 0x.009c - Automatic reset status register */
  75         __be32  pvr;            /* 0x.00a0 - Processor Version Register */
  76         __be32  svr;            /* 0x.00a4 - System Version Register */
  77         u8      res0a8[0xb0 - 0xa8];
  78         __be32  rstcr;          /* 0x.00b0 - Reset Control Register */
  79         u8      res0b4[0xc0 - 0xb4];
  80 #ifdef CONFIG_PPC_85xx
  81         __be32  iovselsr;       /* 0x.00c0 - I/O voltage select status register */
  82 #else
  83         __be32  elbcvselcr;     /* 0x.00c0 - eLBC Voltage Select Ctrl Reg */
  84 #endif
  85         u8      res0c4[0x224 - 0xc4];
  86         __be32  iodelay1;       /* 0x.0224 - IO delay control register 1 */
  87         __be32  iodelay2;       /* 0x.0228 - IO delay control register 2 */
  88         u8      res22c[0x800 - 0x22c];
  89         __be32  clkdvdr;        /* 0x.0800 - Clock Divide Register */
  90         u8      res804[0x900 - 0x804];
  91         __be32  ircr;           /* 0x.0900 - Infrared Control Register */
  92         u8      res904[0x908 - 0x904];
  93         __be32  dmacr;          /* 0x.0908 - DMA Control Register */
  94         u8      res90c[0x914 - 0x90c];
  95         __be32  elbccr;         /* 0x.0914 - eLBC Control Register */
  96         u8      res918[0xb20 - 0x918];
  97         __be32  ddr1clkdr;      /* 0x.0b20 - DDR1 Clock Disable Register */
  98         __be32  ddr2clkdr;      /* 0x.0b24 - DDR2 Clock Disable Register */
  99         __be32  ddrclkdr;       /* 0x.0b28 - DDR Clock Disable Register */
 100         u8      resb2c[0xe00 - 0xb2c];
 101         __be32  clkocr;         /* 0x.0e00 - Clock Out Select Register */
 102         u8      rese04[0xe10 - 0xe04];
 103         __be32  ddrdllcr;       /* 0x.0e10 - DDR DLL Control Register */
 104         u8      rese14[0xe20 - 0xe14];
 105         __be32  lbcdllcr;       /* 0x.0e20 - LBC DLL Control Register */
 106         __be32  cpfor;          /* 0x.0e24 - L2 charge pump fuse override register */
 107         u8      rese28[0xf04 - 0xe28];
 108         __be32  srds1cr0;       /* 0x.0f04 - SerDes1 Control Register 0 */
 109         __be32  srds1cr1;       /* 0x.0f08 - SerDes1 Control Register 0 */
 110         u8      resf0c[0xf2c - 0xf0c];
 111         __be32  itcr;           /* 0x.0f2c - Internal transaction control register */
 112         u8      resf30[0xf40 - 0xf30];
 113         __be32  srds2cr0;       /* 0x.0f40 - SerDes2 Control Register 0 */
 114         __be32  srds2cr1;       /* 0x.0f44 - SerDes2 Control Register 0 */
 115 } __attribute__ ((packed));
 116
 117 #ifdef CONFIG_PPC_86xx
 118
 119 #define CCSR_GUTS_DMACR_DEV_SSI 0       /* DMA controller/channel set to SSI */
 120 #define CCSR_GUTS_DMACR_DEV_IR  1       /* DMA controller/channel set to IR */
 121
 122 /*
 123  * Set the DMACR register in the GUTS
 124  *
 125  * The DMACR register determines the source of initiated transfers for each
 126  * channel on each DMA controller.  Rather than have a bunch of repetitive
 127  * macros for the bit patterns, we just have a function that calculates
 128  * them.
 129  *
 130  * guts: Pointer to GUTS structure
 131  * co: The DMA controller (0 or 1)
 132  * ch: The channel on the DMA controller (0, 1, 2, or 3)
 133  * device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx)
 134  */
 135 static inline void guts_set_dmacr(struct ccsr_guts_86xx __iomem *guts,
 136         unsigned int co, unsigned int ch, unsigned int device)
 137 {
 138         unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch));
 139
 140         clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift);
 141 }
 142
 143 #define CCSR_GUTS_PMUXCR_LDPSEL         0x00010000
 144 #define CCSR_GUTS_PMUXCR_SSI1_MASK      0x0000C000      /* Bitmask for SSI1 */
 145 #define CCSR_GUTS_PMUXCR_SSI1_LA        0x00000000      /* Latched address */
 146 #define CCSR_GUTS_PMUXCR_SSI1_HI        0x00004000      /* High impedance */
 147 #define CCSR_GUTS_PMUXCR_SSI1_SSI       0x00008000      /* Used for SSI1 */
 148 #define CCSR_GUTS_PMUXCR_SSI2_MASK      0x00003000      /* Bitmask for SSI2 */
 149 #define CCSR_GUTS_PMUXCR_SSI2_LA        0x00000000      /* Latched address */
 150 #define CCSR_GUTS_PMUXCR_SSI2_HI        0x00001000      /* High impedance */
 151 #define CCSR_GUTS_PMUXCR_SSI2_SSI       0x00002000      /* Used for SSI2 */
 152 #define CCSR_GUTS_PMUXCR_LA_22_25_LA    0x00000000      /* Latched Address */
 153 #define CCSR_GUTS_PMUXCR_LA_22_25_HI    0x00000400      /* High impedance */
 154 #define CCSR_GUTS_PMUXCR_DBGDRV         0x00000200      /* Signals not driven */
 155 #define CCSR_GUTS_PMUXCR_DMA2_0         0x00000008
 156 #define CCSR_GUTS_PMUXCR_DMA2_3         0x00000004
 157 #define CCSR_GUTS_PMUXCR_DMA1_0         0x00000002
 158 #define CCSR_GUTS_PMUXCR_DMA1_3         0x00000001
 159
 160 /*
 161  * Set the DMA external control bits in the GUTS
 162  *
 163  * The DMA external control bits in the PMUXCR are only meaningful for
 164  * channels 0 and 3.  Any other channels are ignored.
 165  *
 166  * guts: Pointer to GUTS structure
 167  * co: The DMA controller (0 or 1)
 168  * ch: The channel on the DMA controller (0, 1, 2, or 3)
 169  * value: the new value for the bit (0 or 1)
 170  */
 171 static inline void guts_set_pmuxcr_dma(struct ccsr_guts_86xx __iomem *guts,
 172         unsigned int co, unsigned int ch, unsigned int value)
 173 {
 174         if ((ch == 0) || (ch == 3)) {
 175                 unsigned int shift = 2 * (co + 1) - (ch & 1) - 1;
 176
 177                 clrsetbits_be32(&guts->pmuxcr, 1 << shift, value << shift);
 178         }
 179 }
 180
 181 #define CCSR_GUTS_CLKDVDR_PXCKEN        0x80000000
 182 #define CCSR_GUTS_CLKDVDR_SSICKEN       0x20000000
 183 #define CCSR_GUTS_CLKDVDR_PXCKINV       0x10000000
 184 #define CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT 25
 185 #define CCSR_GUTS_CLKDVDR_PXCKDLY_MASK  0x06000000
 186 #define CCSR_GUTS_CLKDVDR_PXCKDLY(x) \
 187         (((x) & 3) << CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT)
 188 #define CCSR_GUTS_CLKDVDR_PXCLK_SHIFT   16
 189 #define CCSR_GUTS_CLKDVDR_PXCLK_MASK    0x001F0000
 190 #define CCSR_GUTS_CLKDVDR_PXCLK(x) (((x) & 31) << CCSR_GUTS_CLKDVDR_PXCLK_SHIFT)
 191 #define CCSR_GUTS_CLKDVDR_SSICLK_MASK   0x000000FF
 192 #define CCSR_GUTS_CLKDVDR_SSICLK(x) ((x) & CCSR_GUTS_CLKDVDR_SSICLK_MASK)
 193
 194 #endif
 195
 196 #endif
 197 #endif