Add linux-next specific files for 20110831
[linux-2.6/next.git] / arch / powerpc / mm / hash_utils_64.c
blob8352db0501921cd813fdcdb6e70e507844bbb064
1 /*
2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
9 *
10 * Module name: htab.c
12 * Description:
13 * PowerPC Hashed Page Table functions
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
21 #undef DEBUG
22 #undef DEBUG_LOW
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/sched.h>
27 #include <linux/proc_fs.h>
28 #include <linux/stat.h>
29 #include <linux/sysctl.h>
30 #include <linux/export.h>
31 #include <linux/ctype.h>
32 #include <linux/cache.h>
33 #include <linux/init.h>
34 #include <linux/signal.h>
35 #include <linux/memblock.h>
37 #include <asm/processor.h>
38 #include <asm/pgtable.h>
39 #include <asm/mmu.h>
40 #include <asm/mmu_context.h>
41 #include <asm/page.h>
42 #include <asm/types.h>
43 #include <asm/system.h>
44 #include <asm/uaccess.h>
45 #include <asm/machdep.h>
46 #include <asm/prom.h>
47 #include <asm/abs_addr.h>
48 #include <asm/tlbflush.h>
49 #include <asm/io.h>
50 #include <asm/eeh.h>
51 #include <asm/tlb.h>
52 #include <asm/cacheflush.h>
53 #include <asm/cputable.h>
54 #include <asm/sections.h>
55 #include <asm/spu.h>
56 #include <asm/udbg.h>
57 #include <asm/code-patching.h>
59 #ifdef DEBUG
60 #define DBG(fmt...) udbg_printf(fmt)
61 #else
62 #define DBG(fmt...)
63 #endif
65 #ifdef DEBUG_LOW
66 #define DBG_LOW(fmt...) udbg_printf(fmt)
67 #else
68 #define DBG_LOW(fmt...)
69 #endif
71 #define KB (1024)
72 #define MB (1024*KB)
73 #define GB (1024L*MB)
76 * Note: pte --> Linux PTE
77 * HPTE --> PowerPC Hashed Page Table Entry
79 * Execution context:
80 * htab_initialize is called with the MMU off (of course), but
81 * the kernel has been copied down to zero so it can directly
82 * reference global data. At this point it is very difficult
83 * to print debug info.
87 #ifdef CONFIG_U3_DART
88 extern unsigned long dart_tablebase;
89 #endif /* CONFIG_U3_DART */
91 static unsigned long _SDR1;
92 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
94 struct hash_pte *htab_address;
95 unsigned long htab_size_bytes;
96 unsigned long htab_hash_mask;
97 EXPORT_SYMBOL_GPL(htab_hash_mask);
98 int mmu_linear_psize = MMU_PAGE_4K;
99 int mmu_virtual_psize = MMU_PAGE_4K;
100 int mmu_vmalloc_psize = MMU_PAGE_4K;
101 #ifdef CONFIG_SPARSEMEM_VMEMMAP
102 int mmu_vmemmap_psize = MMU_PAGE_4K;
103 #endif
104 int mmu_io_psize = MMU_PAGE_4K;
105 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
106 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
107 u16 mmu_slb_size = 64;
108 EXPORT_SYMBOL_GPL(mmu_slb_size);
109 #ifdef CONFIG_HUGETLB_PAGE
110 unsigned int HPAGE_SHIFT;
111 #endif
112 #ifdef CONFIG_PPC_64K_PAGES
113 int mmu_ci_restrictions;
114 #endif
115 #ifdef CONFIG_DEBUG_PAGEALLOC
116 static u8 *linear_map_hash_slots;
117 static unsigned long linear_map_hash_count;
118 static DEFINE_SPINLOCK(linear_map_hash_lock);
119 #endif /* CONFIG_DEBUG_PAGEALLOC */
121 /* There are definitions of page sizes arrays to be used when none
122 * is provided by the firmware.
125 /* Pre-POWER4 CPUs (4k pages only)
127 static struct mmu_psize_def mmu_psize_defaults_old[] = {
128 [MMU_PAGE_4K] = {
129 .shift = 12,
130 .sllp = 0,
131 .penc = 0,
132 .avpnm = 0,
133 .tlbiel = 0,
137 /* POWER4, GPUL, POWER5
139 * Support for 16Mb large pages
141 static struct mmu_psize_def mmu_psize_defaults_gp[] = {
142 [MMU_PAGE_4K] = {
143 .shift = 12,
144 .sllp = 0,
145 .penc = 0,
146 .avpnm = 0,
147 .tlbiel = 1,
149 [MMU_PAGE_16M] = {
150 .shift = 24,
151 .sllp = SLB_VSID_L,
152 .penc = 0,
153 .avpnm = 0x1UL,
154 .tlbiel = 0,
158 static unsigned long htab_convert_pte_flags(unsigned long pteflags)
160 unsigned long rflags = pteflags & 0x1fa;
162 /* _PAGE_EXEC -> NOEXEC */
163 if ((pteflags & _PAGE_EXEC) == 0)
164 rflags |= HPTE_R_N;
166 /* PP bits. PAGE_USER is already PP bit 0x2, so we only
167 * need to add in 0x1 if it's a read-only user page
169 if ((pteflags & _PAGE_USER) && !((pteflags & _PAGE_RW) &&
170 (pteflags & _PAGE_DIRTY)))
171 rflags |= 1;
173 /* Always add C */
174 return rflags | HPTE_R_C;
177 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
178 unsigned long pstart, unsigned long prot,
179 int psize, int ssize)
181 unsigned long vaddr, paddr;
182 unsigned int step, shift;
183 int ret = 0;
185 shift = mmu_psize_defs[psize].shift;
186 step = 1 << shift;
188 prot = htab_convert_pte_flags(prot);
190 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
191 vstart, vend, pstart, prot, psize, ssize);
193 for (vaddr = vstart, paddr = pstart; vaddr < vend;
194 vaddr += step, paddr += step) {
195 unsigned long hash, hpteg;
196 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
197 unsigned long va = hpt_va(vaddr, vsid, ssize);
198 unsigned long tprot = prot;
200 /* Make kernel text executable */
201 if (overlaps_kernel_text(vaddr, vaddr + step))
202 tprot &= ~HPTE_R_N;
204 hash = hpt_hash(va, shift, ssize);
205 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
207 BUG_ON(!ppc_md.hpte_insert);
208 ret = ppc_md.hpte_insert(hpteg, va, paddr, tprot,
209 HPTE_V_BOLTED, psize, ssize);
211 if (ret < 0)
212 break;
213 #ifdef CONFIG_DEBUG_PAGEALLOC
214 if ((paddr >> PAGE_SHIFT) < linear_map_hash_count)
215 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
216 #endif /* CONFIG_DEBUG_PAGEALLOC */
218 return ret < 0 ? ret : 0;
221 #ifdef CONFIG_MEMORY_HOTPLUG
222 static int htab_remove_mapping(unsigned long vstart, unsigned long vend,
223 int psize, int ssize)
225 unsigned long vaddr;
226 unsigned int step, shift;
228 shift = mmu_psize_defs[psize].shift;
229 step = 1 << shift;
231 if (!ppc_md.hpte_removebolted) {
232 printk(KERN_WARNING "Platform doesn't implement "
233 "hpte_removebolted\n");
234 return -EINVAL;
237 for (vaddr = vstart; vaddr < vend; vaddr += step)
238 ppc_md.hpte_removebolted(vaddr, psize, ssize);
240 return 0;
242 #endif /* CONFIG_MEMORY_HOTPLUG */
244 static int __init htab_dt_scan_seg_sizes(unsigned long node,
245 const char *uname, int depth,
246 void *data)
248 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
249 u32 *prop;
250 unsigned long size = 0;
252 /* We are scanning "cpu" nodes only */
253 if (type == NULL || strcmp(type, "cpu") != 0)
254 return 0;
256 prop = (u32 *)of_get_flat_dt_prop(node, "ibm,processor-segment-sizes",
257 &size);
258 if (prop == NULL)
259 return 0;
260 for (; size >= 4; size -= 4, ++prop) {
261 if (prop[0] == 40) {
262 DBG("1T segment support detected\n");
263 cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
264 return 1;
267 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
268 return 0;
271 static void __init htab_init_seg_sizes(void)
273 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
276 static int __init htab_dt_scan_page_sizes(unsigned long node,
277 const char *uname, int depth,
278 void *data)
280 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
281 u32 *prop;
282 unsigned long size = 0;
284 /* We are scanning "cpu" nodes only */
285 if (type == NULL || strcmp(type, "cpu") != 0)
286 return 0;
288 prop = (u32 *)of_get_flat_dt_prop(node,
289 "ibm,segment-page-sizes", &size);
290 if (prop != NULL) {
291 DBG("Page sizes from device-tree:\n");
292 size /= 4;
293 cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
294 while(size > 0) {
295 unsigned int shift = prop[0];
296 unsigned int slbenc = prop[1];
297 unsigned int lpnum = prop[2];
298 unsigned int lpenc = 0;
299 struct mmu_psize_def *def;
300 int idx = -1;
302 size -= 3; prop += 3;
303 while(size > 0 && lpnum) {
304 if (prop[0] == shift)
305 lpenc = prop[1];
306 prop += 2; size -= 2;
307 lpnum--;
309 switch(shift) {
310 case 0xc:
311 idx = MMU_PAGE_4K;
312 break;
313 case 0x10:
314 idx = MMU_PAGE_64K;
315 break;
316 case 0x14:
317 idx = MMU_PAGE_1M;
318 break;
319 case 0x18:
320 idx = MMU_PAGE_16M;
321 cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
322 break;
323 case 0x22:
324 idx = MMU_PAGE_16G;
325 break;
327 if (idx < 0)
328 continue;
329 def = &mmu_psize_defs[idx];
330 def->shift = shift;
331 if (shift <= 23)
332 def->avpnm = 0;
333 else
334 def->avpnm = (1 << (shift - 23)) - 1;
335 def->sllp = slbenc;
336 def->penc = lpenc;
337 /* We don't know for sure what's up with tlbiel, so
338 * for now we only set it for 4K and 64K pages
340 if (idx == MMU_PAGE_4K || idx == MMU_PAGE_64K)
341 def->tlbiel = 1;
342 else
343 def->tlbiel = 0;
345 DBG(" %d: shift=%02x, sllp=%04lx, avpnm=%08lx, "
346 "tlbiel=%d, penc=%d\n",
347 idx, shift, def->sllp, def->avpnm, def->tlbiel,
348 def->penc);
350 return 1;
352 return 0;
355 #ifdef CONFIG_HUGETLB_PAGE
356 /* Scan for 16G memory blocks that have been set aside for huge pages
357 * and reserve those blocks for 16G huge pages.
359 static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
360 const char *uname, int depth,
361 void *data) {
362 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
363 unsigned long *addr_prop;
364 u32 *page_count_prop;
365 unsigned int expected_pages;
366 long unsigned int phys_addr;
367 long unsigned int block_size;
369 /* We are scanning "memory" nodes only */
370 if (type == NULL || strcmp(type, "memory") != 0)
371 return 0;
373 /* This property is the log base 2 of the number of virtual pages that
374 * will represent this memory block. */
375 page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
376 if (page_count_prop == NULL)
377 return 0;
378 expected_pages = (1 << page_count_prop[0]);
379 addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
380 if (addr_prop == NULL)
381 return 0;
382 phys_addr = addr_prop[0];
383 block_size = addr_prop[1];
384 if (block_size != (16 * GB))
385 return 0;
386 printk(KERN_INFO "Huge page(16GB) memory: "
387 "addr = 0x%lX size = 0x%lX pages = %d\n",
388 phys_addr, block_size, expected_pages);
389 if (phys_addr + (16 * GB) <= memblock_end_of_DRAM()) {
390 memblock_reserve(phys_addr, block_size * expected_pages);
391 add_gpage(phys_addr, block_size, expected_pages);
393 return 0;
395 #endif /* CONFIG_HUGETLB_PAGE */
397 static void __init htab_init_page_sizes(void)
399 int rc;
401 /* Default to 4K pages only */
402 memcpy(mmu_psize_defs, mmu_psize_defaults_old,
403 sizeof(mmu_psize_defaults_old));
406 * Try to find the available page sizes in the device-tree
408 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
409 if (rc != 0) /* Found */
410 goto found;
413 * Not in the device-tree, let's fallback on known size
414 * list for 16M capable GP & GR
416 if (mmu_has_feature(MMU_FTR_16M_PAGE))
417 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
418 sizeof(mmu_psize_defaults_gp));
419 found:
420 #ifndef CONFIG_DEBUG_PAGEALLOC
422 * Pick a size for the linear mapping. Currently, we only support
423 * 16M, 1M and 4K which is the default
425 if (mmu_psize_defs[MMU_PAGE_16M].shift)
426 mmu_linear_psize = MMU_PAGE_16M;
427 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
428 mmu_linear_psize = MMU_PAGE_1M;
429 #endif /* CONFIG_DEBUG_PAGEALLOC */
431 #ifdef CONFIG_PPC_64K_PAGES
433 * Pick a size for the ordinary pages. Default is 4K, we support
434 * 64K for user mappings and vmalloc if supported by the processor.
435 * We only use 64k for ioremap if the processor
436 * (and firmware) support cache-inhibited large pages.
437 * If not, we use 4k and set mmu_ci_restrictions so that
438 * hash_page knows to switch processes that use cache-inhibited
439 * mappings to 4k pages.
441 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
442 mmu_virtual_psize = MMU_PAGE_64K;
443 mmu_vmalloc_psize = MMU_PAGE_64K;
444 if (mmu_linear_psize == MMU_PAGE_4K)
445 mmu_linear_psize = MMU_PAGE_64K;
446 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
448 * Don't use 64k pages for ioremap on pSeries, since
449 * that would stop us accessing the HEA ethernet.
451 if (!machine_is(pseries))
452 mmu_io_psize = MMU_PAGE_64K;
453 } else
454 mmu_ci_restrictions = 1;
456 #endif /* CONFIG_PPC_64K_PAGES */
458 #ifdef CONFIG_SPARSEMEM_VMEMMAP
459 /* We try to use 16M pages for vmemmap if that is supported
460 * and we have at least 1G of RAM at boot
462 if (mmu_psize_defs[MMU_PAGE_16M].shift &&
463 memblock_phys_mem_size() >= 0x40000000)
464 mmu_vmemmap_psize = MMU_PAGE_16M;
465 else if (mmu_psize_defs[MMU_PAGE_64K].shift)
466 mmu_vmemmap_psize = MMU_PAGE_64K;
467 else
468 mmu_vmemmap_psize = MMU_PAGE_4K;
469 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
471 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
472 "virtual = %d, io = %d"
473 #ifdef CONFIG_SPARSEMEM_VMEMMAP
474 ", vmemmap = %d"
475 #endif
476 "\n",
477 mmu_psize_defs[mmu_linear_psize].shift,
478 mmu_psize_defs[mmu_virtual_psize].shift,
479 mmu_psize_defs[mmu_io_psize].shift
480 #ifdef CONFIG_SPARSEMEM_VMEMMAP
481 ,mmu_psize_defs[mmu_vmemmap_psize].shift
482 #endif
485 #ifdef CONFIG_HUGETLB_PAGE
486 /* Reserve 16G huge page memory sections for huge pages */
487 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
488 #endif /* CONFIG_HUGETLB_PAGE */
491 static int __init htab_dt_scan_pftsize(unsigned long node,
492 const char *uname, int depth,
493 void *data)
495 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
496 u32 *prop;
498 /* We are scanning "cpu" nodes only */
499 if (type == NULL || strcmp(type, "cpu") != 0)
500 return 0;
502 prop = (u32 *)of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
503 if (prop != NULL) {
504 /* pft_size[0] is the NUMA CEC cookie */
505 ppc64_pft_size = prop[1];
506 return 1;
508 return 0;
511 static unsigned long __init htab_get_table_size(void)
513 unsigned long mem_size, rnd_mem_size, pteg_count, psize;
515 /* If hash size isn't already provided by the platform, we try to
516 * retrieve it from the device-tree. If it's not there neither, we
517 * calculate it now based on the total RAM size
519 if (ppc64_pft_size == 0)
520 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
521 if (ppc64_pft_size)
522 return 1UL << ppc64_pft_size;
524 /* round mem_size up to next power of 2 */
525 mem_size = memblock_phys_mem_size();
526 rnd_mem_size = 1UL << __ilog2(mem_size);
527 if (rnd_mem_size < mem_size)
528 rnd_mem_size <<= 1;
530 /* # pages / 2 */
531 psize = mmu_psize_defs[mmu_virtual_psize].shift;
532 pteg_count = max(rnd_mem_size >> (psize + 1), 1UL << 11);
534 return pteg_count << 7;
537 #ifdef CONFIG_MEMORY_HOTPLUG
538 void create_section_mapping(unsigned long start, unsigned long end)
540 BUG_ON(htab_bolt_mapping(start, end, __pa(start),
541 pgprot_val(PAGE_KERNEL), mmu_linear_psize,
542 mmu_kernel_ssize));
545 int remove_section_mapping(unsigned long start, unsigned long end)
547 return htab_remove_mapping(start, end, mmu_linear_psize,
548 mmu_kernel_ssize);
550 #endif /* CONFIG_MEMORY_HOTPLUG */
552 #define FUNCTION_TEXT(A) ((*(unsigned long *)(A)))
554 static void __init htab_finish_init(void)
556 extern unsigned int *htab_call_hpte_insert1;
557 extern unsigned int *htab_call_hpte_insert2;
558 extern unsigned int *htab_call_hpte_remove;
559 extern unsigned int *htab_call_hpte_updatepp;
561 #ifdef CONFIG_PPC_HAS_HASH_64K
562 extern unsigned int *ht64_call_hpte_insert1;
563 extern unsigned int *ht64_call_hpte_insert2;
564 extern unsigned int *ht64_call_hpte_remove;
565 extern unsigned int *ht64_call_hpte_updatepp;
567 patch_branch(ht64_call_hpte_insert1,
568 FUNCTION_TEXT(ppc_md.hpte_insert),
569 BRANCH_SET_LINK);
570 patch_branch(ht64_call_hpte_insert2,
571 FUNCTION_TEXT(ppc_md.hpte_insert),
572 BRANCH_SET_LINK);
573 patch_branch(ht64_call_hpte_remove,
574 FUNCTION_TEXT(ppc_md.hpte_remove),
575 BRANCH_SET_LINK);
576 patch_branch(ht64_call_hpte_updatepp,
577 FUNCTION_TEXT(ppc_md.hpte_updatepp),
578 BRANCH_SET_LINK);
580 #endif /* CONFIG_PPC_HAS_HASH_64K */
582 patch_branch(htab_call_hpte_insert1,
583 FUNCTION_TEXT(ppc_md.hpte_insert),
584 BRANCH_SET_LINK);
585 patch_branch(htab_call_hpte_insert2,
586 FUNCTION_TEXT(ppc_md.hpte_insert),
587 BRANCH_SET_LINK);
588 patch_branch(htab_call_hpte_remove,
589 FUNCTION_TEXT(ppc_md.hpte_remove),
590 BRANCH_SET_LINK);
591 patch_branch(htab_call_hpte_updatepp,
592 FUNCTION_TEXT(ppc_md.hpte_updatepp),
593 BRANCH_SET_LINK);
596 static void __init htab_initialize(void)
598 unsigned long table;
599 unsigned long pteg_count;
600 unsigned long prot;
601 unsigned long base = 0, size = 0, limit;
602 struct memblock_region *reg;
604 DBG(" -> htab_initialize()\n");
606 /* Initialize segment sizes */
607 htab_init_seg_sizes();
609 /* Initialize page sizes */
610 htab_init_page_sizes();
612 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
613 mmu_kernel_ssize = MMU_SEGSIZE_1T;
614 mmu_highuser_ssize = MMU_SEGSIZE_1T;
615 printk(KERN_INFO "Using 1TB segments\n");
619 * Calculate the required size of the htab. We want the number of
620 * PTEGs to equal one half the number of real pages.
622 htab_size_bytes = htab_get_table_size();
623 pteg_count = htab_size_bytes >> 7;
625 htab_hash_mask = pteg_count - 1;
627 if (firmware_has_feature(FW_FEATURE_LPAR)) {
628 /* Using a hypervisor which owns the htab */
629 htab_address = NULL;
630 _SDR1 = 0;
631 } else {
632 /* Find storage for the HPT. Must be contiguous in
633 * the absolute address space. On cell we want it to be
634 * in the first 2 Gig so we can use it for IOMMU hacks.
636 if (machine_is(cell))
637 limit = 0x80000000;
638 else
639 limit = MEMBLOCK_ALLOC_ANYWHERE;
641 table = memblock_alloc_base(htab_size_bytes, htab_size_bytes, limit);
643 DBG("Hash table allocated at %lx, size: %lx\n", table,
644 htab_size_bytes);
646 htab_address = abs_to_virt(table);
648 /* htab absolute addr + encoded htabsize */
649 _SDR1 = table + __ilog2(pteg_count) - 11;
651 /* Initialize the HPT with no entries */
652 memset((void *)table, 0, htab_size_bytes);
654 /* Set SDR1 */
655 mtspr(SPRN_SDR1, _SDR1);
658 prot = pgprot_val(PAGE_KERNEL);
660 #ifdef CONFIG_DEBUG_PAGEALLOC
661 linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
662 linear_map_hash_slots = __va(memblock_alloc_base(linear_map_hash_count,
663 1, ppc64_rma_size));
664 memset(linear_map_hash_slots, 0, linear_map_hash_count);
665 #endif /* CONFIG_DEBUG_PAGEALLOC */
667 /* On U3 based machines, we need to reserve the DART area and
668 * _NOT_ map it to avoid cache paradoxes as it's remapped non
669 * cacheable later on
672 /* create bolted the linear mapping in the hash table */
673 for_each_memblock(memory, reg) {
674 base = (unsigned long)__va(reg->base);
675 size = reg->size;
677 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
678 base, size, prot);
680 #ifdef CONFIG_U3_DART
681 /* Do not map the DART space. Fortunately, it will be aligned
682 * in such a way that it will not cross two memblock regions and
683 * will fit within a single 16Mb page.
684 * The DART space is assumed to be a full 16Mb region even if
685 * we only use 2Mb of that space. We will use more of it later
686 * for AGP GART. We have to use a full 16Mb large page.
688 DBG("DART base: %lx\n", dart_tablebase);
690 if (dart_tablebase != 0 && dart_tablebase >= base
691 && dart_tablebase < (base + size)) {
692 unsigned long dart_table_end = dart_tablebase + 16 * MB;
693 if (base != dart_tablebase)
694 BUG_ON(htab_bolt_mapping(base, dart_tablebase,
695 __pa(base), prot,
696 mmu_linear_psize,
697 mmu_kernel_ssize));
698 if ((base + size) > dart_table_end)
699 BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB,
700 base + size,
701 __pa(dart_table_end),
702 prot,
703 mmu_linear_psize,
704 mmu_kernel_ssize));
705 continue;
707 #endif /* CONFIG_U3_DART */
708 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
709 prot, mmu_linear_psize, mmu_kernel_ssize));
711 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
714 * If we have a memory_limit and we've allocated TCEs then we need to
715 * explicitly map the TCE area at the top of RAM. We also cope with the
716 * case that the TCEs start below memory_limit.
717 * tce_alloc_start/end are 16MB aligned so the mapping should work
718 * for either 4K or 16MB pages.
720 if (tce_alloc_start) {
721 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
722 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
724 if (base + size >= tce_alloc_start)
725 tce_alloc_start = base + size + 1;
727 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
728 __pa(tce_alloc_start), prot,
729 mmu_linear_psize, mmu_kernel_ssize));
732 htab_finish_init();
734 DBG(" <- htab_initialize()\n");
736 #undef KB
737 #undef MB
739 void __init early_init_mmu(void)
741 /* Setup initial STAB address in the PACA */
742 get_paca()->stab_real = __pa((u64)&initial_stab);
743 get_paca()->stab_addr = (u64)&initial_stab;
745 /* Initialize the MMU Hash table and create the linear mapping
746 * of memory. Has to be done before stab/slb initialization as
747 * this is currently where the page size encoding is obtained
749 htab_initialize();
751 /* Initialize stab / SLB management except on iSeries
753 if (mmu_has_feature(MMU_FTR_SLB))
754 slb_initialize();
755 else if (!firmware_has_feature(FW_FEATURE_ISERIES))
756 stab_initialize(get_paca()->stab_real);
759 #ifdef CONFIG_SMP
760 void __cpuinit early_init_mmu_secondary(void)
762 /* Initialize hash table for that CPU */
763 if (!firmware_has_feature(FW_FEATURE_LPAR))
764 mtspr(SPRN_SDR1, _SDR1);
766 /* Initialize STAB/SLB. We use a virtual address as it works
767 * in real mode on pSeries and we want a virtual address on
768 * iSeries anyway
770 if (mmu_has_feature(MMU_FTR_SLB))
771 slb_initialize();
772 else
773 stab_initialize(get_paca()->stab_addr);
775 #endif /* CONFIG_SMP */
778 * Called by asm hashtable.S for doing lazy icache flush
780 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
782 struct page *page;
784 if (!pfn_valid(pte_pfn(pte)))
785 return pp;
787 page = pte_page(pte);
789 /* page is dirty */
790 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
791 if (trap == 0x400) {
792 flush_dcache_icache_page(page);
793 set_bit(PG_arch_1, &page->flags);
794 } else
795 pp |= HPTE_R_N;
797 return pp;
800 #ifdef CONFIG_PPC_MM_SLICES
801 unsigned int get_paca_psize(unsigned long addr)
803 unsigned long index, slices;
805 if (addr < SLICE_LOW_TOP) {
806 slices = get_paca()->context.low_slices_psize;
807 index = GET_LOW_SLICE_INDEX(addr);
808 } else {
809 slices = get_paca()->context.high_slices_psize;
810 index = GET_HIGH_SLICE_INDEX(addr);
812 return (slices >> (index * 4)) & 0xF;
815 #else
816 unsigned int get_paca_psize(unsigned long addr)
818 return get_paca()->context.user_psize;
820 #endif
823 * Demote a segment to using 4k pages.
824 * For now this makes the whole process use 4k pages.
826 #ifdef CONFIG_PPC_64K_PAGES
827 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
829 if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
830 return;
831 slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
832 #ifdef CONFIG_SPU_BASE
833 spu_flush_all_slbs(mm);
834 #endif
835 if (get_paca_psize(addr) != MMU_PAGE_4K) {
836 get_paca()->context = mm->context;
837 slb_flush_and_rebolt();
840 #endif /* CONFIG_PPC_64K_PAGES */
842 #ifdef CONFIG_PPC_SUBPAGE_PROT
844 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
845 * Userspace sets the subpage permissions using the subpage_prot system call.
847 * Result is 0: full permissions, _PAGE_RW: read-only,
848 * _PAGE_USER or _PAGE_USER|_PAGE_RW: no access.
850 static int subpage_protection(struct mm_struct *mm, unsigned long ea)
852 struct subpage_prot_table *spt = &mm->context.spt;
853 u32 spp = 0;
854 u32 **sbpm, *sbpp;
856 if (ea >= spt->maxaddr)
857 return 0;
858 if (ea < 0x100000000) {
859 /* addresses below 4GB use spt->low_prot */
860 sbpm = spt->low_prot;
861 } else {
862 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
863 if (!sbpm)
864 return 0;
866 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
867 if (!sbpp)
868 return 0;
869 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
871 /* extract 2-bit bitfield for this 4k subpage */
872 spp >>= 30 - 2 * ((ea >> 12) & 0xf);
874 /* turn 0,1,2,3 into combination of _PAGE_USER and _PAGE_RW */
875 spp = ((spp & 2) ? _PAGE_USER : 0) | ((spp & 1) ? _PAGE_RW : 0);
876 return spp;
879 #else /* CONFIG_PPC_SUBPAGE_PROT */
880 static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
882 return 0;
884 #endif
886 void hash_failure_debug(unsigned long ea, unsigned long access,
887 unsigned long vsid, unsigned long trap,
888 int ssize, int psize, unsigned long pte)
890 if (!printk_ratelimit())
891 return;
892 pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
893 ea, access, current->comm);
894 pr_info(" trap=0x%lx vsid=0x%lx ssize=%d psize=%d pte=0x%lx\n",
895 trap, vsid, ssize, psize, pte);
898 /* Result code is:
899 * 0 - handled
900 * 1 - normal page fault
901 * -1 - critical hash insertion error
902 * -2 - access not permitted by subpage protection mechanism
904 int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
906 pgd_t *pgdir;
907 unsigned long vsid;
908 struct mm_struct *mm;
909 pte_t *ptep;
910 unsigned hugeshift;
911 const struct cpumask *tmp;
912 int rc, user_region = 0, local = 0;
913 int psize, ssize;
915 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
916 ea, access, trap);
918 if ((ea & ~REGION_MASK) >= PGTABLE_RANGE) {
919 DBG_LOW(" out of pgtable range !\n");
920 return 1;
923 /* Get region & vsid */
924 switch (REGION_ID(ea)) {
925 case USER_REGION_ID:
926 user_region = 1;
927 mm = current->mm;
928 if (! mm) {
929 DBG_LOW(" user region with no mm !\n");
930 return 1;
932 psize = get_slice_psize(mm, ea);
933 ssize = user_segment_size(ea);
934 vsid = get_vsid(mm->context.id, ea, ssize);
935 break;
936 case VMALLOC_REGION_ID:
937 mm = &init_mm;
938 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
939 if (ea < VMALLOC_END)
940 psize = mmu_vmalloc_psize;
941 else
942 psize = mmu_io_psize;
943 ssize = mmu_kernel_ssize;
944 break;
945 default:
946 /* Not a valid range
947 * Send the problem up to do_page_fault
949 return 1;
951 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
953 /* Get pgdir */
954 pgdir = mm->pgd;
955 if (pgdir == NULL)
956 return 1;
958 /* Check CPU locality */
959 tmp = cpumask_of(smp_processor_id());
960 if (user_region && cpumask_equal(mm_cpumask(mm), tmp))
961 local = 1;
963 #ifndef CONFIG_PPC_64K_PAGES
964 /* If we use 4K pages and our psize is not 4K, then we might
965 * be hitting a special driver mapping, and need to align the
966 * address before we fetch the PTE.
968 * It could also be a hugepage mapping, in which case this is
969 * not necessary, but it's not harmful, either.
971 if (psize != MMU_PAGE_4K)
972 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
973 #endif /* CONFIG_PPC_64K_PAGES */
975 /* Get PTE and page size from page tables */
976 ptep = find_linux_pte_or_hugepte(pgdir, ea, &hugeshift);
977 if (ptep == NULL || !pte_present(*ptep)) {
978 DBG_LOW(" no PTE !\n");
979 return 1;
982 /* Add _PAGE_PRESENT to the required access perm */
983 access |= _PAGE_PRESENT;
985 /* Pre-check access permissions (will be re-checked atomically
986 * in __hash_page_XX but this pre-check is a fast path
988 if (access & ~pte_val(*ptep)) {
989 DBG_LOW(" no access !\n");
990 return 1;
993 #ifdef CONFIG_HUGETLB_PAGE
994 if (hugeshift)
995 return __hash_page_huge(ea, access, vsid, ptep, trap, local,
996 ssize, hugeshift, psize);
997 #endif /* CONFIG_HUGETLB_PAGE */
999 #ifndef CONFIG_PPC_64K_PAGES
1000 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
1001 #else
1002 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
1003 pte_val(*(ptep + PTRS_PER_PTE)));
1004 #endif
1005 /* Do actual hashing */
1006 #ifdef CONFIG_PPC_64K_PAGES
1007 /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */
1008 if ((pte_val(*ptep) & _PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
1009 demote_segment_4k(mm, ea);
1010 psize = MMU_PAGE_4K;
1013 /* If this PTE is non-cacheable and we have restrictions on
1014 * using non cacheable large pages, then we switch to 4k
1016 if (mmu_ci_restrictions && psize == MMU_PAGE_64K &&
1017 (pte_val(*ptep) & _PAGE_NO_CACHE)) {
1018 if (user_region) {
1019 demote_segment_4k(mm, ea);
1020 psize = MMU_PAGE_4K;
1021 } else if (ea < VMALLOC_END) {
1023 * some driver did a non-cacheable mapping
1024 * in vmalloc space, so switch vmalloc
1025 * to 4k pages
1027 printk(KERN_ALERT "Reducing vmalloc segment "
1028 "to 4kB pages because of "
1029 "non-cacheable mapping\n");
1030 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
1031 #ifdef CONFIG_SPU_BASE
1032 spu_flush_all_slbs(mm);
1033 #endif
1036 if (user_region) {
1037 if (psize != get_paca_psize(ea)) {
1038 get_paca()->context = mm->context;
1039 slb_flush_and_rebolt();
1041 } else if (get_paca()->vmalloc_sllp !=
1042 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
1043 get_paca()->vmalloc_sllp =
1044 mmu_psize_defs[mmu_vmalloc_psize].sllp;
1045 slb_vmalloc_update();
1047 #endif /* CONFIG_PPC_64K_PAGES */
1049 #ifdef CONFIG_PPC_HAS_HASH_64K
1050 if (psize == MMU_PAGE_64K)
1051 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
1052 else
1053 #endif /* CONFIG_PPC_HAS_HASH_64K */
1055 int spp = subpage_protection(mm, ea);
1056 if (access & spp)
1057 rc = -2;
1058 else
1059 rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1060 local, ssize, spp);
1063 /* Dump some info in case of hash insertion failure, they should
1064 * never happen so it is really useful to know if/when they do
1066 if (rc == -1)
1067 hash_failure_debug(ea, access, vsid, trap, ssize, psize,
1068 pte_val(*ptep));
1069 #ifndef CONFIG_PPC_64K_PAGES
1070 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1071 #else
1072 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1073 pte_val(*(ptep + PTRS_PER_PTE)));
1074 #endif
1075 DBG_LOW(" -> rc=%d\n", rc);
1076 return rc;
1078 EXPORT_SYMBOL_GPL(hash_page);
1080 void hash_preload(struct mm_struct *mm, unsigned long ea,
1081 unsigned long access, unsigned long trap)
1083 unsigned long vsid;
1084 pgd_t *pgdir;
1085 pte_t *ptep;
1086 unsigned long flags;
1087 int rc, ssize, local = 0;
1089 BUG_ON(REGION_ID(ea) != USER_REGION_ID);
1091 #ifdef CONFIG_PPC_MM_SLICES
1092 /* We only prefault standard pages for now */
1093 if (unlikely(get_slice_psize(mm, ea) != mm->context.user_psize))
1094 return;
1095 #endif
1097 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1098 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1100 /* Get Linux PTE if available */
1101 pgdir = mm->pgd;
1102 if (pgdir == NULL)
1103 return;
1104 ptep = find_linux_pte(pgdir, ea);
1105 if (!ptep)
1106 return;
1108 #ifdef CONFIG_PPC_64K_PAGES
1109 /* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on
1110 * a 64K kernel), then we don't preload, hash_page() will take
1111 * care of it once we actually try to access the page.
1112 * That way we don't have to duplicate all of the logic for segment
1113 * page size demotion here
1115 if (pte_val(*ptep) & (_PAGE_4K_PFN | _PAGE_NO_CACHE))
1116 return;
1117 #endif /* CONFIG_PPC_64K_PAGES */
1119 /* Get VSID */
1120 ssize = user_segment_size(ea);
1121 vsid = get_vsid(mm->context.id, ea, ssize);
1123 /* Hash doesn't like irqs */
1124 local_irq_save(flags);
1126 /* Is that local to this CPU ? */
1127 if (cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id())))
1128 local = 1;
1130 /* Hash it in */
1131 #ifdef CONFIG_PPC_HAS_HASH_64K
1132 if (mm->context.user_psize == MMU_PAGE_64K)
1133 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
1134 else
1135 #endif /* CONFIG_PPC_HAS_HASH_64K */
1136 rc = __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize,
1137 subpage_protection(mm, ea));
1139 /* Dump some info in case of hash insertion failure, they should
1140 * never happen so it is really useful to know if/when they do
1142 if (rc == -1)
1143 hash_failure_debug(ea, access, vsid, trap, ssize,
1144 mm->context.user_psize, pte_val(*ptep));
1146 local_irq_restore(flags);
1149 /* WARNING: This is called from hash_low_64.S, if you change this prototype,
1150 * do not forget to update the assembly call site !
1152 void flush_hash_page(unsigned long va, real_pte_t pte, int psize, int ssize,
1153 int local)
1155 unsigned long hash, index, shift, hidx, slot;
1157 DBG_LOW("flush_hash_page(va=%016lx)\n", va);
1158 pte_iterate_hashed_subpages(pte, psize, va, index, shift) {
1159 hash = hpt_hash(va, shift, ssize);
1160 hidx = __rpte_to_hidx(pte, index);
1161 if (hidx & _PTEIDX_SECONDARY)
1162 hash = ~hash;
1163 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1164 slot += hidx & _PTEIDX_GROUP_IX;
1165 DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index, slot, hidx);
1166 ppc_md.hpte_invalidate(slot, va, psize, ssize, local);
1167 } pte_iterate_hashed_end();
1170 void flush_hash_range(unsigned long number, int local)
1172 if (ppc_md.flush_hash_range)
1173 ppc_md.flush_hash_range(number, local);
1174 else {
1175 int i;
1176 struct ppc64_tlb_batch *batch =
1177 &__get_cpu_var(ppc64_tlb_batch);
1179 for (i = 0; i < number; i++)
1180 flush_hash_page(batch->vaddr[i], batch->pte[i],
1181 batch->psize, batch->ssize, local);
1186 * low_hash_fault is called when we the low level hash code failed
1187 * to instert a PTE due to an hypervisor error
1189 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1191 if (user_mode(regs)) {
1192 #ifdef CONFIG_PPC_SUBPAGE_PROT
1193 if (rc == -2)
1194 _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1195 else
1196 #endif
1197 _exception(SIGBUS, regs, BUS_ADRERR, address);
1198 } else
1199 bad_page_fault(regs, address, SIGBUS);
1202 #ifdef CONFIG_DEBUG_PAGEALLOC
1203 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1205 unsigned long hash, hpteg;
1206 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1207 unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
1208 unsigned long mode = htab_convert_pte_flags(PAGE_KERNEL);
1209 int ret;
1211 hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
1212 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
1214 ret = ppc_md.hpte_insert(hpteg, va, __pa(vaddr),
1215 mode, HPTE_V_BOLTED,
1216 mmu_linear_psize, mmu_kernel_ssize);
1217 BUG_ON (ret < 0);
1218 spin_lock(&linear_map_hash_lock);
1219 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1220 linear_map_hash_slots[lmi] = ret | 0x80;
1221 spin_unlock(&linear_map_hash_lock);
1224 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1226 unsigned long hash, hidx, slot;
1227 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1228 unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
1230 hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
1231 spin_lock(&linear_map_hash_lock);
1232 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1233 hidx = linear_map_hash_slots[lmi] & 0x7f;
1234 linear_map_hash_slots[lmi] = 0;
1235 spin_unlock(&linear_map_hash_lock);
1236 if (hidx & _PTEIDX_SECONDARY)
1237 hash = ~hash;
1238 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1239 slot += hidx & _PTEIDX_GROUP_IX;
1240 ppc_md.hpte_invalidate(slot, va, mmu_linear_psize, mmu_kernel_ssize, 0);
1243 void kernel_map_pages(struct page *page, int numpages, int enable)
1245 unsigned long flags, vaddr, lmi;
1246 int i;
1248 local_irq_save(flags);
1249 for (i = 0; i < numpages; i++, page++) {
1250 vaddr = (unsigned long)page_address(page);
1251 lmi = __pa(vaddr) >> PAGE_SHIFT;
1252 if (lmi >= linear_map_hash_count)
1253 continue;
1254 if (enable)
1255 kernel_map_linear_page(vaddr, lmi);
1256 else
1257 kernel_unmap_linear_page(vaddr, lmi);
1259 local_irq_restore(flags);
1261 #endif /* CONFIG_DEBUG_PAGEALLOC */
1263 void setup_initial_memory_limit(phys_addr_t first_memblock_base,
1264 phys_addr_t first_memblock_size)
1266 /* We don't currently support the first MEMBLOCK not mapping 0
1267 * physical on those processors
1269 BUG_ON(first_memblock_base != 0);
1271 /* On LPAR systems, the first entry is our RMA region,
1272 * non-LPAR 64-bit hash MMU systems don't have a limitation
1273 * on real mode access, but using the first entry works well
1274 * enough. We also clamp it to 1G to avoid some funky things
1275 * such as RTAS bugs etc...
1277 ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
1279 /* Finally limit subsequent allocations */
1280 memblock_set_current_limit(ppc64_rma_size);