arch/powerpc/platforms/85xx/mpc85xx_cds.c

   1 /*
   2  * MPC85xx setup and early boot code plus other random bits.
   3  *
   4  * Maintained by Kumar Gala (see MAINTAINERS for contact information)
   5  *
   6  * Copyright 2005 Freescale Semiconductor Inc.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13
  14 #include <linux/stddef.h>
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/errno.h>
  18 #include <linux/reboot.h>
  19 #include <linux/pci.h>
  20 #include <linux/kdev_t.h>
  21 #include <linux/major.h>
  22 #include <linux/console.h>
  23 #include <linux/delay.h>
  24 #include <linux/seq_file.h>
  25 #include <linux/initrd.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/fsl_devices.h>
  28 #include <linux/of_platform.h>
  29
  30 #include <asm/system.h>
  31 #include <asm/pgtable.h>
  32 #include <asm/page.h>
  33 #include <linux/atomic.h>
  34 #include <asm/time.h>
  35 #include <asm/io.h>
  36 #include <asm/machdep.h>
  37 #include <asm/ipic.h>
  38 #include <asm/pci-bridge.h>
  39 #include <asm/irq.h>
  40 #include <mm/mmu_decl.h>
  41 #include <asm/prom.h>
  42 #include <asm/udbg.h>
  43 #include <asm/mpic.h>
  44 #include <asm/i8259.h>
  45
  46 #include <sysdev/fsl_soc.h>
  47 #include <sysdev/fsl_pci.h>
  48
  49 /* CADMUS info */
  50 /* xxx - galak, move into device tree */
  51 #define CADMUS_BASE (0xf8004000)
  52 #define CADMUS_SIZE (256)
  53 #define CM_VER  (0)
  54 #define CM_CSR  (1)
  55 #define CM_RST  (2)
  56
  57
  58 static int cds_pci_slot = 2;
  59 static volatile u8 *cadmus;
  60
  61 #ifdef CONFIG_PCI
  62
  63 #define ARCADIA_HOST_BRIDGE_IDSEL       17
  64 #define ARCADIA_2ND_BRIDGE_IDSEL        3
  65
  66 static int mpc85xx_exclude_device(struct pci_controller *hose,
  67                                   u_char bus, u_char devfn)
  68 {
  69         /* We explicitly do not go past the Tundra 320 Bridge */
  70         if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
  71                 return PCIBIOS_DEVICE_NOT_FOUND;
  72         if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
  73                 return PCIBIOS_DEVICE_NOT_FOUND;
  74         else
  75                 return PCIBIOS_SUCCESSFUL;
  76 }
  77
  78 static void mpc85xx_cds_restart(char *cmd)
  79 {
  80         struct pci_dev *dev;
  81         u_char tmp;
  82
  83         if ((dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686,
  84                                         NULL))) {
  85
  86                 /* Use the VIA Super Southbridge to force a PCI reset */
  87                 pci_read_config_byte(dev, 0x47, &tmp);
  88                 pci_write_config_byte(dev, 0x47, tmp | 1);
  89
  90                 /* Flush the outbound PCI write queues */
  91                 pci_read_config_byte(dev, 0x47, &tmp);
  92
  93                 /*
  94                  *  At this point, the harware reset should have triggered.
  95                  *  However, if it doesn't work for some mysterious reason,
  96                  *  just fall through to the default reset below.
  97                  */
  98
  99                 pci_dev_put(dev);
 100         }
 101
 102         /*
 103          *  If we can't find the VIA chip (maybe the P2P bridge is disabled)
 104          *  or the VIA chip reset didn't work, just use the default reset.
 105          */
 106         fsl_rstcr_restart(NULL);
 107 }
 108
 109 static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev)
 110 {
 111         u_char c;
 112         if (dev->vendor == PCI_VENDOR_ID_VIA) {
 113                 switch (dev->device) {
 114                 case PCI_DEVICE_ID_VIA_82C586_1:
 115                         /*
 116                          * U-Boot does not set the enable bits
 117                          * for the IDE device. Force them on here.
 118                          */
 119                         pci_read_config_byte(dev, 0x40, &c);
 120                         c |= 0x03; /* IDE: Chip Enable Bits */
 121                         pci_write_config_byte(dev, 0x40, c);
 122
 123                         /*
 124                          * Since only primary interface works, force the
 125                          * IDE function to standard primary IDE interrupt
 126                          * w/ 8259 offset
 127                          */
 128                         dev->irq = 14;
 129                         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
 130                         break;
 131                 /*
 132                  * Force legacy USB interrupt routing
 133                  */
 134                 case PCI_DEVICE_ID_VIA_82C586_2:
 135                 /* There are two USB controllers.
 136                  * Identify them by functon number
 137                  */
 138                         if (PCI_FUNC(dev->devfn) == 3)
 139                                 dev->irq = 11;
 140                         else
 141                                 dev->irq = 10;
 142                         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
 143                 default:
 144                         break;
 145                 }
 146         }
 147 }
 148
 149 static void __devinit skip_fake_bridge(struct pci_dev *dev)
 150 {
 151         /* Make it an error to skip the fake bridge
 152          * in pci_setup_device() in probe.c */
 153         dev->hdr_type = 0x7f;
 154 }
 155 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x3fff, skip_fake_bridge);
 156 DECLARE_PCI_FIXUP_EARLY(0x3fff, 0x1957, skip_fake_bridge);
 157 DECLARE_PCI_FIXUP_EARLY(0xff3f, 0x5719, skip_fake_bridge);
 158
 159 #ifdef CONFIG_PPC_I8259
 160 static void mpc85xx_8259_cascade_handler(unsigned int irq,
 161                                          struct irq_desc *desc)
 162 {
 163         unsigned int cascade_irq = i8259_irq();
 164
 165         if (cascade_irq != NO_IRQ)
 166                 /* handle an interrupt from the 8259 */
 167                 generic_handle_irq(cascade_irq);
 168
 169         /* check for any interrupts from the shared IRQ line */
 170         handle_fasteoi_irq(irq, desc);
 171 }
 172
 173 static irqreturn_t mpc85xx_8259_cascade_action(int irq, void *dev_id)
 174 {
 175         return IRQ_HANDLED;
 176 }
 177
 178 static struct irqaction mpc85xxcds_8259_irqaction = {
 179         .handler = mpc85xx_8259_cascade_action,
 180         .flags = IRQF_SHARED,
 181         .name = "8259 cascade",
 182 };
 183 #endif /* PPC_I8259 */
 184 #endif /* CONFIG_PCI */
 185
 186 static void __init mpc85xx_cds_pic_init(void)
 187 {
 188         struct mpic *mpic;
 189         struct resource r;
 190         struct device_node *np = NULL;
 191
 192         np = of_find_node_by_type(np, "open-pic");
 193
 194         if (np == NULL) {
 195                 printk(KERN_ERR "Could not find open-pic node\n");
 196                 return;
 197         }
 198
 199         if (of_address_to_resource(np, 0, &r)) {
 200                 printk(KERN_ERR "Failed to map mpic register space\n");
 201                 of_node_put(np);
 202                 return;
 203         }
 204
 205         mpic = mpic_alloc(np, r.start,
 206                         MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
 207                         0, 256, " OpenPIC  ");
 208         BUG_ON(mpic == NULL);
 209
 210         /* Return the mpic node */
 211         of_node_put(np);
 212
 213         mpic_init(mpic);
 214 }
 215
 216 #if defined(CONFIG_PPC_I8259) && defined(CONFIG_PCI)
 217 static int mpc85xx_cds_8259_attach(void)
 218 {
 219         int ret;
 220         struct device_node *np = NULL;
 221         struct device_node *cascade_node = NULL;
 222         int cascade_irq;
 223
 224         /* Initialize the i8259 controller */
 225         for_each_node_by_type(np, "interrupt-controller")
 226                 if (of_device_is_compatible(np, "chrp,iic")) {
 227                         cascade_node = np;
 228                         break;
 229                 }
 230
 231         if (cascade_node == NULL) {
 232                 printk(KERN_DEBUG "Could not find i8259 PIC\n");
 233                 return -ENODEV;
 234         }
 235
 236         cascade_irq = irq_of_parse_and_map(cascade_node, 0);
 237         if (cascade_irq == NO_IRQ) {
 238                 printk(KERN_ERR "Failed to map cascade interrupt\n");
 239                 return -ENXIO;
 240         }
 241
 242         i8259_init(cascade_node, 0);
 243         of_node_put(cascade_node);
 244
 245         /*
 246          *  Hook the interrupt to make sure desc->action is never NULL.
 247          *  This is required to ensure that the interrupt does not get
 248          *  disabled when the last user of the shared IRQ line frees their
 249          *  interrupt.
 250          */
 251         if ((ret = setup_irq(cascade_irq, &mpc85xxcds_8259_irqaction))) {
 252                 printk(KERN_ERR "Failed to setup cascade interrupt\n");
 253                 return ret;
 254         }
 255
 256         /* Success. Connect our low-level cascade handler. */
 257         irq_set_handler(cascade_irq, mpc85xx_8259_cascade_handler);
 258
 259         return 0;
 260 }
 261 machine_device_initcall(mpc85xx_cds, mpc85xx_cds_8259_attach);
 262
 263 #endif /* CONFIG_PPC_I8259 */
 264
 265 /*
 266  * Setup the architecture
 267  */
 268 static void __init mpc85xx_cds_setup_arch(void)
 269 {
 270 #ifdef CONFIG_PCI
 271         struct device_node *np;
 272 #endif
 273
 274         if (ppc_md.progress)
 275                 ppc_md.progress("mpc85xx_cds_setup_arch()", 0);
 276
 277         cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE);
 278         cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
 279
 280         if (ppc_md.progress) {
 281                 char buf[40];
 282                 snprintf(buf, 40, "CDS Version = 0x%x in slot %d\n",
 283                                 cadmus[CM_VER], cds_pci_slot);
 284                 ppc_md.progress(buf, 0);
 285         }
 286
 287 #ifdef CONFIG_PCI
 288         for_each_node_by_type(np, "pci") {
 289                 if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
 290                     of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
 291                         struct resource rsrc;
 292                         of_address_to_resource(np, 0, &rsrc);
 293                         if ((rsrc.start & 0xfffff) == 0x8000)
 294                                 fsl_add_bridge(np, 1);
 295                         else
 296                                 fsl_add_bridge(np, 0);
 297                 }
 298         }
 299
 300         ppc_md.pci_irq_fixup = mpc85xx_cds_pci_irq_fixup;
 301         ppc_md.pci_exclude_device = mpc85xx_exclude_device;
 302 #endif
 303 }
 304
 305 static void mpc85xx_cds_show_cpuinfo(struct seq_file *m)
 306 {
 307         uint pvid, svid, phid1;
 308
 309         pvid = mfspr(SPRN_PVR);
 310         svid = mfspr(SPRN_SVR);
 311
 312         seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
 313         seq_printf(m, "Machine\t\t: MPC85xx CDS (0x%x)\n", cadmus[CM_VER]);
 314         seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
 315         seq_printf(m, "SVR\t\t: 0x%x\n", svid);
 316
 317         /* Display cpu Pll setting */
 318         phid1 = mfspr(SPRN_HID1);
 319         seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
 320 }
 321
 322
 323 /*
 324  * Called very early, device-tree isn't unflattened
 325  */
 326 static int __init mpc85xx_cds_probe(void)
 327 {
 328         unsigned long root = of_get_flat_dt_root();
 329
 330         return of_flat_dt_is_compatible(root, "MPC85xxCDS");
 331 }
 332
 333 static struct of_device_id __initdata of_bus_ids[] = {
 334         { .type = "soc", },
 335         { .compatible = "soc", },
 336         { .compatible = "simple-bus", },
 337         { .compatible = "gianfar", },
 338         {},
 339 };
 340
 341 static int __init declare_of_platform_devices(void)
 342 {
 343         return of_platform_bus_probe(NULL, of_bus_ids, NULL);
 344 }
 345 machine_device_initcall(mpc85xx_cds, declare_of_platform_devices);
 346
 347 define_machine(mpc85xx_cds) {
 348         .name           = "MPC85xx CDS",
 349         .probe          = mpc85xx_cds_probe,
 350         .setup_arch     = mpc85xx_cds_setup_arch,
 351         .init_IRQ       = mpc85xx_cds_pic_init,
 352         .show_cpuinfo   = mpc85xx_cds_show_cpuinfo,
 353         .get_irq        = mpic_get_irq,
 354 #ifdef CONFIG_PCI
 355         .restart        = mpc85xx_cds_restart,
 356         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 357 #else
 358         .restart        = fsl_rstcr_restart,
 359 #endif
 360         .calibrate_decr = generic_calibrate_decr,
 361         .progress       = udbg_progress,
 362 };