arch/powerpc/platforms/86xx/mpc8610_hpcd.c

   1 /*
   2  * MPC8610 HPCD board specific routines
   3  *
   4  * Initial author: Xianghua Xiao <x.xiao@freescale.com>
   5  * Recode: Jason Jin <jason.jin@freescale.com>
   6  *         York Sun <yorksun@freescale.com>
   7  *
   8  * Rewrite the interrupt routing. remove the 8259PIC support,
   9  * All the integrated device in ULI use sideband interrupt.
  10  *
  11  * Copyright 2008 Freescale Semiconductor Inc.
  12  *
  13  * This program is free software; you can redistribute  it and/or modify it
  14  * under  the terms of  the GNU General  Public License as published by the
  15  * Free Software Foundation;  either version 2 of the  License, or (at your
  16  * option) any later version.
  17  */
  18
  19 #include <linux/stddef.h>
  20 #include <linux/kernel.h>
  21 #include <linux/pci.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/kdev_t.h>
  24 #include <linux/delay.h>
  25 #include <linux/seq_file.h>
  26 #include <linux/of.h>
  27
  28 #include <asm/system.h>
  29 #include <asm/time.h>
  30 #include <asm/machdep.h>
  31 #include <asm/pci-bridge.h>
  32 #include <asm/prom.h>
  33 #include <mm/mmu_decl.h>
  34 #include <asm/udbg.h>
  35
  36 #include <asm/mpic.h>
  37
  38 #include <linux/of_platform.h>
  39 #include <sysdev/fsl_pci.h>
  40 #include <sysdev/fsl_soc.h>
  41 #include <sysdev/simple_gpio.h>
  42 #include <asm/fsl_guts.h>
  43
  44 #include "mpc86xx.h"
  45
  46 static struct device_node *pixis_node;
  47 static unsigned char *pixis_bdcfg0, *pixis_arch;
  48
  49 /* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */
  50 #define CLKDVDR_PXCKEN          0x80000000
  51 #define CLKDVDR_PXCKINV         0x10000000
  52 #define CLKDVDR_PXCKDLY         0x06000000
  53 #define CLKDVDR_PXCLK_MASK      0x001F0000
  54
  55 #ifdef CONFIG_SUSPEND
  56 static irqreturn_t mpc8610_sw9_irq(int irq, void *data)
  57 {
  58         pr_debug("%s: PIXIS' event (sw9/wakeup) IRQ handled\n", __func__);
  59         return IRQ_HANDLED;
  60 }
  61
  62 static void __init mpc8610_suspend_init(void)
  63 {
  64         int irq;
  65         int ret;
  66
  67         if (!pixis_node)
  68                 return;
  69
  70         irq = irq_of_parse_and_map(pixis_node, 0);
  71         if (!irq) {
  72                 pr_err("%s: can't map pixis event IRQ.\n", __func__);
  73                 return;
  74         }
  75
  76         ret = request_irq(irq, mpc8610_sw9_irq, 0, "sw9:wakeup", NULL);
  77         if (ret) {
  78                 pr_err("%s: can't request pixis event IRQ: %d\n",
  79                        __func__, ret);
  80                 irq_dispose_mapping(irq);
  81         }
  82
  83         enable_irq_wake(irq);
  84 }
  85 #else
  86 static inline void mpc8610_suspend_init(void) { }
  87 #endif /* CONFIG_SUSPEND */
  88
  89 static struct of_device_id __initdata mpc8610_ids[] = {
  90         { .compatible = "fsl,mpc8610-immr", },
  91         { .compatible = "fsl,mpc8610-guts", },
  92         { .compatible = "simple-bus", },
  93         /* So that the DMA channel nodes can be probed individually: */
  94         { .compatible = "fsl,eloplus-dma", },
  95         {}
  96 };
  97
  98 static int __init mpc8610_declare_of_platform_devices(void)
  99 {
 100         /* Firstly, register PIXIS GPIOs. */
 101         simple_gpiochip_init("fsl,fpga-pixis-gpio-bank");
 102
 103         /* Enable wakeup on PIXIS' event IRQ. */
 104         mpc8610_suspend_init();
 105
 106         /* Without this call, the SSI device driver won't get probed. */
 107         of_platform_bus_probe(NULL, mpc8610_ids, NULL);
 108
 109         return 0;
 110 }
 111 machine_device_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices);
 112
 113 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
 114
 115 /*
 116  * DIU Area Descriptor
 117  *
 118  * The MPC8610 reference manual shows the bits of the AD register in
 119  * little-endian order, which causes the BLUE_C field to be split into two
 120  * parts. To simplify the definition of the MAKE_AD() macro, we define the
 121  * fields in big-endian order and byte-swap the result.
 122  *
 123  * So even though the registers don't look like they're in the
 124  * same bit positions as they are on the P1022, the same value is written to
 125  * the AD register on the MPC8610 and on the P1022.
 126  */
 127 #define AD_BYTE_F               0x10000000
 128 #define AD_ALPHA_C_MASK         0x0E000000
 129 #define AD_ALPHA_C_SHIFT        25
 130 #define AD_BLUE_C_MASK          0x01800000
 131 #define AD_BLUE_C_SHIFT         23
 132 #define AD_GREEN_C_MASK         0x00600000
 133 #define AD_GREEN_C_SHIFT        21
 134 #define AD_RED_C_MASK           0x00180000
 135 #define AD_RED_C_SHIFT          19
 136 #define AD_PALETTE              0x00040000
 137 #define AD_PIXEL_S_MASK         0x00030000
 138 #define AD_PIXEL_S_SHIFT        16
 139 #define AD_COMP_3_MASK          0x0000F000
 140 #define AD_COMP_3_SHIFT         12
 141 #define AD_COMP_2_MASK          0x00000F00
 142 #define AD_COMP_2_SHIFT         8
 143 #define AD_COMP_1_MASK          0x000000F0
 144 #define AD_COMP_1_SHIFT         4
 145 #define AD_COMP_0_MASK          0x0000000F
 146 #define AD_COMP_0_SHIFT         0
 147
 148 #define MAKE_AD(alpha, red, blue, green, size, c0, c1, c2, c3) \
 149         cpu_to_le32(AD_BYTE_F | (alpha << AD_ALPHA_C_SHIFT) | \
 150         (blue << AD_BLUE_C_SHIFT) | (green << AD_GREEN_C_SHIFT) | \
 151         (red << AD_RED_C_SHIFT) | (c3 << AD_COMP_3_SHIFT) | \
 152         (c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \
 153         (c0 << AD_COMP_0_SHIFT) | (size << AD_PIXEL_S_SHIFT))
 154
 155 u32 mpc8610hpcd_get_pixel_format(enum fsl_diu_monitor_port port,
 156                                  unsigned int bits_per_pixel)
 157 {
 158         static const u32 pixelformat[][3] = {
 159                 {
 160                         MAKE_AD(3, 0, 2, 1, 3, 8, 8, 8, 8),
 161                         MAKE_AD(4, 2, 0, 1, 2, 8, 8, 8, 0),
 162                         MAKE_AD(4, 0, 2, 1, 1, 5, 6, 5, 0)
 163                 },
 164                 {
 165                         MAKE_AD(3, 2, 0, 1, 3, 8, 8, 8, 8),
 166                         MAKE_AD(4, 0, 2, 1, 2, 8, 8, 8, 0),
 167                         MAKE_AD(4, 2, 0, 1, 1, 5, 6, 5, 0)
 168                 },
 169         };
 170         unsigned int arch_monitor;
 171
 172         /* The DVI port is mis-wired on revision 1 of this board. */
 173         arch_monitor =
 174                 ((*pixis_arch == 0x01) && (port == FSL_DIU_PORT_DVI)) ? 0 : 1;
 175
 176         switch (bits_per_pixel) {
 177         case 32:
 178                 return pixelformat[arch_monitor][0];
 179         case 24:
 180                 return pixelformat[arch_monitor][1];
 181         case 16:
 182                 return pixelformat[arch_monitor][2];
 183         default:
 184                 pr_err("fsl-diu: unsupported pixel depth %u\n", bits_per_pixel);
 185                 return 0;
 186         }
 187 }
 188
 189 void mpc8610hpcd_set_gamma_table(enum fsl_diu_monitor_port port,
 190                                  char *gamma_table_base)
 191 {
 192         int i;
 193         if (port == FSL_DIU_PORT_DLVDS) {
 194                 for (i = 0; i < 256*3; i++)
 195                         gamma_table_base[i] = (gamma_table_base[i] << 2) |
 196                                          ((gamma_table_base[i] >> 6) & 0x03);
 197         }
 198 }
 199
 200 #define PX_BRDCFG0_DVISEL       (1 << 3)
 201 #define PX_BRDCFG0_DLINK        (1 << 4)
 202 #define PX_BRDCFG0_DIU_MASK     (PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK)
 203
 204 void mpc8610hpcd_set_monitor_port(enum fsl_diu_monitor_port port)
 205 {
 206         switch (port) {
 207         case FSL_DIU_PORT_DVI:
 208                 clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK,
 209                              PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK);
 210                 break;
 211         case FSL_DIU_PORT_LVDS:
 212                 clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK,
 213                              PX_BRDCFG0_DLINK);
 214                 break;
 215         case FSL_DIU_PORT_DLVDS:
 216                 clrbits8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK);
 217                 break;
 218         }
 219 }
 220
 221 /**
 222  * mpc8610hpcd_set_pixel_clock: program the DIU's clock
 223  *
 224  * @pixclock: the wavelength, in picoseconds, of the clock
 225  */
 226 void mpc8610hpcd_set_pixel_clock(unsigned int pixclock)
 227 {
 228         struct device_node *guts_np = NULL;
 229         struct ccsr_guts_86xx __iomem *guts;
 230         unsigned long freq;
 231         u64 temp;
 232         u32 pxclk;
 233
 234         /* Map the global utilities registers. */
 235         guts_np = of_find_compatible_node(NULL, NULL, "fsl,mpc8610-guts");
 236         if (!guts_np) {
 237                 pr_err("mpc8610hpcd: missing global utilties device node\n");
 238                 return;
 239         }
 240
 241         guts = of_iomap(guts_np, 0);
 242         of_node_put(guts_np);
 243         if (!guts) {
 244                 pr_err("mpc8610hpcd: could not map global utilties device\n");
 245                 return;
 246         }
 247
 248         /* Convert pixclock from a wavelength to a frequency */
 249         temp = 1000000000000ULL;
 250         do_div(temp, pixclock);
 251         freq = temp;
 252
 253         /*
 254          * 'pxclk' is the ratio of the platform clock to the pixel clock.
 255          * On the MPC8610, the value programmed into CLKDVDR is the ratio
 256          * minus one.  The valid range of values is 2-31.
 257          */
 258         pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq) - 1;
 259         pxclk = clamp_t(u32, pxclk, 2, 31);
 260
 261         /* Disable the pixel clock, and set it to non-inverted and no delay */
 262         clrbits32(&guts->clkdvdr,
 263                   CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
 264
 265         /* Enable the clock and set the pxclk */
 266         setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
 267
 268         iounmap(guts);
 269 }
 270
 271 enum fsl_diu_monitor_port
 272 mpc8610hpcd_valid_monitor_port(enum fsl_diu_monitor_port port)
 273 {
 274         return port;
 275 }
 276
 277 #endif
 278
 279 static void __init mpc86xx_hpcd_setup_arch(void)
 280 {
 281         struct resource r;
 282         struct device_node *np;
 283         unsigned char *pixis;
 284
 285         if (ppc_md.progress)
 286                 ppc_md.progress("mpc86xx_hpcd_setup_arch()", 0);
 287
 288 #ifdef CONFIG_PCI
 289         for_each_node_by_type(np, "pci") {
 290                 if (of_device_is_compatible(np, "fsl,mpc8610-pci")
 291                     || of_device_is_compatible(np, "fsl,mpc8641-pcie")) {
 292                         struct resource rsrc;
 293                         of_address_to_resource(np, 0, &rsrc);
 294                         if ((rsrc.start & 0xfffff) == 0xa000)
 295                                 fsl_add_bridge(np, 1);
 296                         else
 297                                 fsl_add_bridge(np, 0);
 298                 }
 299         }
 300 #endif
 301 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
 302         diu_ops.get_pixel_format        = mpc8610hpcd_get_pixel_format;
 303         diu_ops.set_gamma_table         = mpc8610hpcd_set_gamma_table;
 304         diu_ops.set_monitor_port        = mpc8610hpcd_set_monitor_port;
 305         diu_ops.set_pixel_clock         = mpc8610hpcd_set_pixel_clock;
 306         diu_ops.valid_monitor_port      = mpc8610hpcd_valid_monitor_port;
 307 #endif
 308
 309         pixis_node = of_find_compatible_node(NULL, NULL, "fsl,fpga-pixis");
 310         if (pixis_node) {
 311                 of_address_to_resource(pixis_node, 0, &r);
 312                 of_node_put(pixis_node);
 313                 pixis = ioremap(r.start, 32);
 314                 if (!pixis) {
 315                         printk(KERN_ERR "Err: can't map FPGA cfg register!\n");
 316                         return;
 317                 }
 318                 pixis_bdcfg0 = pixis + 8;
 319                 pixis_arch = pixis + 1;
 320         } else
 321                 printk(KERN_ERR "Err: "
 322                                 "can't find device node 'fsl,fpga-pixis'\n");
 323
 324         printk("MPC86xx HPCD board from Freescale Semiconductor\n");
 325 }
 326
 327 /*
 328  * Called very early, device-tree isn't unflattened
 329  */
 330 static int __init mpc86xx_hpcd_probe(void)
 331 {
 332         unsigned long root = of_get_flat_dt_root();
 333
 334         if (of_flat_dt_is_compatible(root, "fsl,MPC8610HPCD"))
 335                 return 1;       /* Looks good */
 336
 337         return 0;
 338 }
 339
 340 static long __init mpc86xx_time_init(void)
 341 {
 342         unsigned int temp;
 343
 344         /* Set the time base to zero */
 345         mtspr(SPRN_TBWL, 0);
 346         mtspr(SPRN_TBWU, 0);
 347
 348         temp = mfspr(SPRN_HID0);
 349         temp |= HID0_TBEN;
 350         mtspr(SPRN_HID0, temp);
 351         asm volatile("isync");
 352
 353         return 0;
 354 }
 355
 356 define_machine(mpc86xx_hpcd) {
 357         .name                   = "MPC86xx HPCD",
 358         .probe                  = mpc86xx_hpcd_probe,
 359         .setup_arch             = mpc86xx_hpcd_setup_arch,
 360         .init_IRQ               = mpc86xx_init_irq,
 361         .get_irq                = mpic_get_irq,
 362         .restart                = fsl_rstcr_restart,
 363         .time_init              = mpc86xx_time_init,
 364         .calibrate_decr         = generic_calibrate_decr,
 365         .progress               = udbg_progress,
 366         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 367 };