2 * SH7760 DMABRG IRQ handling
4 * (c) 2007 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
5 * licensed under the GPLv2.
9 #include <linux/interrupt.h>
10 #include <linux/kernel.h>
11 #include <linux/slab.h>
13 #include <asm/dmabrg.h>
17 * The DMABRG is a special DMA unit within the SH7760. It does transfers
18 * from USB-SRAM/Audio units to main memory (and also the LCDC; but that
19 * part is sensibly placed in the LCDC registers and requires no irqs)
20 * It has 3 IRQ lines which trigger 10 events, and works independently
21 * from the traditional SH DMAC (although it blocks usage of DMAC 0)
23 * BRGIRQID | component | dir | meaning | source
24 * -----------------------------------------------------
25 * 0 | USB-DMA | ... | xfer done | DMABRGI1
26 * 1 | USB-UAE | ... | USB addr err.| DMABRGI0
27 * 2 | HAC0/SSI0 | play| all done | DMABRGI1
28 * 3 | HAC0/SSI0 | play| half done | DMABRGI2
29 * 4 | HAC0/SSI0 | rec | all done | DMABRGI1
30 * 5 | HAC0/SSI0 | rec | half done | DMABRGI2
31 * 6 | HAC1/SSI1 | play| all done | DMABRGI1
32 * 7 | HAC1/SSI1 | play| half done | DMABRGI2
33 * 8 | HAC1/SSI1 | rec | all done | DMABRGI1
34 * 9 | HAC1/SSI1 | rec | half done | DMABRGI2
36 * all can be enabled/disabled in the DMABRGCR register,
37 * as well as checked if they occurred.
39 * DMABRGI0 services USB DMA Address errors, but it still must be
40 * enabled/acked in the DMABRGCR register. USB-DMA complete indicator
41 * is grouped together with the audio buffer end indicators, too bad...
43 * DMABRGCR: Bits 31-24: audio-dma ENABLE flags,
44 * Bits 23-16: audio-dma STATUS flags,
45 * Bits 9-8: USB error/xfer ENABLE,
46 * Bits 1-0: USB error/xfer STATUS.
47 * Ack an IRQ by writing 0 to the STATUS flag.
48 * Mask IRQ by writing 0 to ENABLE flag.
50 * Usage is almost like with any other IRQ:
51 * dmabrg_request_irq(BRGIRQID, handler, data)
52 * dmabrg_free_irq(BRGIRQID)
54 * handler prototype: void brgirqhandler(void *data)
57 #define DMARSRA 0xfe090000
58 #define DMAOR 0xffa00040
59 #define DMACHCR0 0xffa0000c
60 #define DMABRGCR 0xfe3c0000
62 #define DMAOR_BRG 0x0000c000
63 #define DMAOR_DMEN 0x00000001
69 struct dmabrg_handler
{
70 void (*handler
)(void *);
74 static inline void dmabrg_call_handler(int i
)
76 dmabrg_handlers
[i
].handler(dmabrg_handlers
[i
].data
);
80 * main DMABRG irq handler. It acks irqs and then
81 * handles every set and unmasked bit sequentially.
82 * No locking and no validity checks; it should be
83 * as fast as possible (audio!)
85 static irqreturn_t
dmabrg_irq(int irq
, void *data
)
90 dcr
= __raw_readl(DMABRGCR
);
91 __raw_writel(dcr
& ~0x00ff0003, DMABRGCR
); /* ack all */
92 dcr
&= dcr
>> 8; /* ignore masked */
94 /* USB stuff, get it out of the way first */
96 dmabrg_call_handler(DMABRGIRQ_USBDMA
);
98 dmabrg_call_handler(DMABRGIRQ_USBDMAERR
);
105 dmabrg_call_handler(i
+ DMABRGIRQ_A0TXF
);
110 static void dmabrg_disable_irq(unsigned int dmairq
)
113 dcr
= __raw_readl(DMABRGCR
);
114 dcr
&= ~(1 << ((dmairq
> 1) ? dmairq
+ 22 : dmairq
+ 8));
115 __raw_writel(dcr
, DMABRGCR
);
118 static void dmabrg_enable_irq(unsigned int dmairq
)
121 dcr
= __raw_readl(DMABRGCR
);
122 dcr
|= (1 << ((dmairq
> 1) ? dmairq
+ 22 : dmairq
+ 8));
123 __raw_writel(dcr
, DMABRGCR
);
126 int dmabrg_request_irq(unsigned int dmairq
, void(*handler
)(void*),
129 if ((dmairq
> 9) || !handler
)
131 if (dmabrg_handlers
[dmairq
].handler
)
134 dmabrg_handlers
[dmairq
].handler
= handler
;
135 dmabrg_handlers
[dmairq
].data
= data
;
137 dmabrg_enable_irq(dmairq
);
140 EXPORT_SYMBOL_GPL(dmabrg_request_irq
);
142 void dmabrg_free_irq(unsigned int dmairq
)
144 if (likely(dmairq
< 10)) {
145 dmabrg_disable_irq(dmairq
);
146 dmabrg_handlers
[dmairq
].handler
= NULL
;
147 dmabrg_handlers
[dmairq
].data
= NULL
;
150 EXPORT_SYMBOL_GPL(dmabrg_free_irq
);
152 static int __init
dmabrg_init(void)
157 dmabrg_handlers
= kzalloc(10 * sizeof(struct dmabrg_handler
),
159 if (!dmabrg_handlers
)
163 /* request DMAC channel 0 before anyone else can get it */
164 ret
= request_dma(0, "DMAC 0 (DMABRG)");
166 printk(KERN_INFO
"DMABRG: DMAC ch0 not reserved!\n");
169 __raw_writel(0, DMABRGCR
);
170 __raw_writel(0, DMACHCR0
);
171 __raw_writel(0x94000000, DMARSRA
); /* enable DMABRG in DMAC 0 */
173 /* enable DMABRG mode, enable the DMAC */
174 or = __raw_readl(DMAOR
);
175 __raw_writel(or | DMAOR_BRG
| DMAOR_DMEN
, DMAOR
);
177 ret
= request_irq(DMABRGI0
, dmabrg_irq
, IRQF_DISABLED
,
178 "DMABRG USB address error", NULL
);
182 ret
= request_irq(DMABRGI1
, dmabrg_irq
, IRQF_DISABLED
,
183 "DMABRG Transfer End", NULL
);
187 ret
= request_irq(DMABRGI2
, dmabrg_irq
, IRQF_DISABLED
,
188 "DMABRG Transfer Half", NULL
);
192 free_irq(DMABRGI1
, 0);
193 out1
: free_irq(DMABRGI0
, 0);
194 out0
: kfree(dmabrg_handlers
);
197 subsys_initcall(dmabrg_init
);