arch/sh/drivers/pci/fixups-rts7751r2d.c

   1 /*
   2  * arch/sh/drivers/pci/fixups-rts7751r2d.c
   3  *
   4  * RTS7751R2D / LBOXRE2 PCI fixups
   5  *
   6  * Copyright (C) 2003  Lineo uSolutions, Inc.
   7  * Copyright (C) 2004  Paul Mundt
   8  * Copyright (C) 2007  Nobuhiro Iwamatsu
   9  *
  10  * This file is subject to the terms and conditions of the GNU General Public
  11  * License.  See the file "COPYING" in the main directory of this archive
  12  * for more details.
  13  */
  14 #include <linux/pci.h>
  15 #include <mach/lboxre2.h>
  16 #include <mach/r2d.h>
  17 #include "pci-sh4.h"
  18 #include <generated/machtypes.h>
  19
  20 #define PCIMCR_MRSET_OFF        0xBFFFFFFF
  21 #define PCIMCR_RFSH_OFF         0xFFFFFFFB
  22
  23 static u8 rts7751r2d_irq_tab[] __initdata = {
  24         IRQ_PCI_INTA,
  25         IRQ_PCI_INTB,
  26         IRQ_PCI_INTC,
  27         IRQ_PCI_INTD,
  28 };
  29
  30 static char lboxre2_irq_tab[] __initdata = {
  31         IRQ_ETH0, IRQ_ETH1, IRQ_INTA, IRQ_INTD,
  32 };
  33
  34 int __init pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
  35 {
  36         if (mach_is_lboxre2())
  37                 return lboxre2_irq_tab[slot];
  38         else
  39                 return rts7751r2d_irq_tab[slot];
  40 }
  41
  42 int pci_fixup_pcic(struct pci_channel *chan)
  43 {
  44         unsigned long bcr1, mcr;
  45
  46         bcr1 = __raw_readl(SH7751_BCR1);
  47         bcr1 |= 0x40080000;     /* Enable Bit 19 BREQEN, set PCIC to slave */
  48         pci_write_reg(chan, bcr1, SH4_PCIBCR1);
  49
  50         /* Enable all interrupts, so we known what to fix */
  51         pci_write_reg(chan, 0x0000c3ff, SH4_PCIINTM);
  52         pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM);
  53
  54         pci_write_reg(chan, 0xfb900047, SH7751_PCICONF1);
  55         pci_write_reg(chan, 0xab000001, SH7751_PCICONF4);
  56
  57         mcr = __raw_readl(SH7751_MCR);
  58         mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
  59         pci_write_reg(chan, mcr, SH4_PCIMCR);
  60
  61         pci_write_reg(chan, 0x0c000000, SH7751_PCICONF5);
  62         pci_write_reg(chan, 0xd0000000, SH7751_PCICONF6);
  63         pci_write_reg(chan, 0x0c000000, SH4_PCILAR0);
  64         pci_write_reg(chan, 0x00000000, SH4_PCILAR1);
  65
  66         return 0;
  67 }