arch/sh/drivers/pci/ops-sh4.c

   1 /*
   2  * Generic SH-4 / SH-4A PCIC operations (SH7751, SH7780).
   3  *
   4  * Copyright (C) 2002 - 2009  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License v2. See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/pci.h>
  11 #include <linux/io.h>
  12 #include <linux/spinlock.h>
  13 #include <asm/addrspace.h>
  14 #include "pci-sh4.h"
  15
  16 /*
  17  * Direct access to PCI hardware...
  18  */
  19 #define CONFIG_CMD(bus, devfn, where) \
  20         (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
  21
  22 /*
  23  * Functions for accessing PCI configuration space with type 1 accesses
  24  */
  25 static int sh4_pci_read(struct pci_bus *bus, unsigned int devfn,
  26                            int where, int size, u32 *val)
  27 {
  28         struct pci_channel *chan = bus->sysdata;
  29         unsigned long flags;
  30         u32 data;
  31
  32         /*
  33          * PCIPDR may only be accessed as 32 bit words,
  34          * so we must do byte alignment by hand
  35          */
  36         raw_spin_lock_irqsave(&pci_config_lock, flags);
  37         pci_write_reg(chan, CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
  38         data = pci_read_reg(chan, SH4_PCIPDR);
  39         raw_spin_unlock_irqrestore(&pci_config_lock, flags);
  40
  41         switch (size) {
  42         case 1:
  43                 *val = (data >> ((where & 3) << 3)) & 0xff;
  44                 break;
  45         case 2:
  46                 *val = (data >> ((where & 2) << 3)) & 0xffff;
  47                 break;
  48         case 4:
  49                 *val = data;
  50                 break;
  51         default:
  52                 return PCIBIOS_FUNC_NOT_SUPPORTED;
  53         }
  54
  55         return PCIBIOS_SUCCESSFUL;
  56 }
  57
  58 /*
  59  * Since SH4 only does 32bit access we'll have to do a read,
  60  * mask,write operation.
  61  * We'll allow an odd byte offset, though it should be illegal.
  62  */
  63 static int sh4_pci_write(struct pci_bus *bus, unsigned int devfn,
  64                          int where, int size, u32 val)
  65 {
  66         struct pci_channel *chan = bus->sysdata;
  67         unsigned long flags;
  68         int shift;
  69         u32 data;
  70
  71         raw_spin_lock_irqsave(&pci_config_lock, flags);
  72         pci_write_reg(chan, CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
  73         data = pci_read_reg(chan, SH4_PCIPDR);
  74         raw_spin_unlock_irqrestore(&pci_config_lock, flags);
  75
  76         switch (size) {
  77         case 1:
  78                 shift = (where & 3) << 3;
  79                 data &= ~(0xff << shift);
  80                 data |= ((val & 0xff) << shift);
  81                 break;
  82         case 2:
  83                 shift = (where & 2) << 3;
  84                 data &= ~(0xffff << shift);
  85                 data |= ((val & 0xffff) << shift);
  86                 break;
  87         case 4:
  88                 data = val;
  89                 break;
  90         default:
  91                 return PCIBIOS_FUNC_NOT_SUPPORTED;
  92         }
  93
  94         pci_write_reg(chan, data, SH4_PCIPDR);
  95
  96         return PCIBIOS_SUCCESSFUL;
  97 }
  98
  99 struct pci_ops sh4_pci_ops = {
 100         .read           = sh4_pci_read,
 101         .write          = sh4_pci_write,
 102 };
 103
 104 int __attribute__((weak)) pci_fixup_pcic(struct pci_channel *chan)
 105 {
 106         /* Nothing to do. */
 107         return 0;
 108 }