arch/sh/drivers/pci/pci.c

   1 /*
   2  * New-style PCI core.
   3  *
   4  * Copyright (c) 2004 - 2009  Paul Mundt
   5  * Copyright (c) 2002  M. R. Brown
   6  *
   7  * Modelled after arch/mips/pci/pci.c:
   8  *  Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org)
   9  *
  10  * This file is subject to the terms and conditions of the GNU General Public
  11  * License.  See the file "COPYING" in the main directory of this archive
  12  * for more details.
  13  */
  14 #include <linux/kernel.h>
  15 #include <linux/mm.h>
  16 #include <linux/pci.h>
  17 #include <linux/init.h>
  18 #include <linux/types.h>
  19 #include <linux/dma-debug.h>
  20 #include <linux/io.h>
  21 #include <linux/mutex.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/export.h>
  24
  25 unsigned long PCIBIOS_MIN_IO = 0x0000;
  26 unsigned long PCIBIOS_MIN_MEM = 0;
  27
  28 /*
  29  * The PCI controller list.
  30  */
  31 static struct pci_channel *hose_head, **hose_tail = &hose_head;
  32
  33 static int pci_initialized;
  34
  35 static void __devinit pcibios_scanbus(struct pci_channel *hose)
  36 {
  37         static int next_busno;
  38         static int need_domain_info;
  39         struct pci_bus *bus;
  40
  41         bus = pci_scan_bus(next_busno, hose->pci_ops, hose);
  42         hose->bus = bus;
  43
  44         need_domain_info = need_domain_info || hose->index;
  45         hose->need_domain_info = need_domain_info;
  46         if (bus) {
  47                 next_busno = bus->subordinate + 1;
  48                 /* Don't allow 8-bit bus number overflow inside the hose -
  49                    reserve some space for bridges. */
  50                 if (next_busno > 224) {
  51                         next_busno = 0;
  52                         need_domain_info = 1;
  53                 }
  54
  55                 pci_bus_size_bridges(bus);
  56                 pci_bus_assign_resources(bus);
  57                 pci_enable_bridges(bus);
  58         }
  59 }
  60
  61 /*
  62  * This interrupt-safe spinlock protects all accesses to PCI
  63  * configuration space.
  64  */
  65 DEFINE_RAW_SPINLOCK(pci_config_lock);
  66 static DEFINE_MUTEX(pci_scan_mutex);
  67
  68 int __devinit register_pci_controller(struct pci_channel *hose)
  69 {
  70         int i;
  71
  72         for (i = 0; i < hose->nr_resources; i++) {
  73                 struct resource *res = hose->resources + i;
  74
  75                 if (res->flags & IORESOURCE_IO) {
  76                         if (request_resource(&ioport_resource, res) < 0)
  77                                 goto out;
  78                 } else {
  79                         if (request_resource(&iomem_resource, res) < 0)
  80                                 goto out;
  81                 }
  82         }
  83
  84         *hose_tail = hose;
  85         hose_tail = &hose->next;
  86
  87         /*
  88          * Do not panic here but later - this might happen before console init.
  89          */
  90         if (!hose->io_map_base) {
  91                 printk(KERN_WARNING
  92                        "registering PCI controller with io_map_base unset\n");
  93         }
  94
  95         /*
  96          * Setup the ERR/PERR and SERR timers, if available.
  97          */
  98         pcibios_enable_timers(hose);
  99
 100         /*
 101          * Scan the bus if it is register after the PCI subsystem
 102          * initialization.
 103          */
 104         if (pci_initialized) {
 105                 mutex_lock(&pci_scan_mutex);
 106                 pcibios_scanbus(hose);
 107                 mutex_unlock(&pci_scan_mutex);
 108         }
 109
 110         return 0;
 111
 112 out:
 113         for (--i; i >= 0; i--)
 114                 release_resource(&hose->resources[i]);
 115
 116         printk(KERN_WARNING "Skipping PCI bus scan due to resource conflict\n");
 117         return -1;
 118 }
 119
 120 static int __init pcibios_init(void)
 121 {
 122         struct pci_channel *hose;
 123
 124         /* Scan all of the recorded PCI controllers.  */
 125         for (hose = hose_head; hose; hose = hose->next)
 126                 pcibios_scanbus(hose);
 127
 128         pci_fixup_irqs(pci_common_swizzle, pcibios_map_platform_irq);
 129
 130         dma_debug_add_bus(&pci_bus_type);
 131
 132         pci_initialized = 1;
 133
 134         return 0;
 135 }
 136 subsys_initcall(pcibios_init);
 137
 138 static void pcibios_fixup_device_resources(struct pci_dev *dev,
 139         struct pci_bus *bus)
 140 {
 141         /* Update device resources.  */
 142         struct pci_channel *hose = bus->sysdata;
 143         unsigned long offset = 0;
 144         int i;
 145
 146         for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 147                 if (!dev->resource[i].start)
 148                         continue;
 149                 if (dev->resource[i].flags & IORESOURCE_IO)
 150                         offset = hose->io_offset;
 151                 else if (dev->resource[i].flags & IORESOURCE_MEM)
 152                         offset = hose->mem_offset;
 153
 154                 dev->resource[i].start += offset;
 155                 dev->resource[i].end += offset;
 156         }
 157 }
 158
 159 /*
 160  *  Called after each bus is probed, but before its children
 161  *  are examined.
 162  */
 163 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
 164 {
 165         struct pci_dev *dev = bus->self;
 166         struct list_head *ln;
 167         struct pci_channel *hose = bus->sysdata;
 168
 169         if (!dev) {
 170                 int i;
 171
 172                 for (i = 0; i < hose->nr_resources; i++)
 173                         bus->resource[i] = hose->resources + i;
 174         }
 175
 176         for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
 177                 dev = pci_dev_b(ln);
 178
 179                 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
 180                         pcibios_fixup_device_resources(dev, bus);
 181         }
 182 }
 183
 184 /*
 185  * We need to avoid collisions with `mirrored' VGA ports
 186  * and other strange ISA hardware, so we always want the
 187  * addresses to be allocated in the 0x000-0x0ff region
 188  * modulo 0x400.
 189  */
 190 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
 191                                 resource_size_t size, resource_size_t align)
 192 {
 193         struct pci_dev *dev = data;
 194         struct pci_channel *hose = dev->sysdata;
 195         resource_size_t start = res->start;
 196
 197         if (res->flags & IORESOURCE_IO) {
 198                 if (start < PCIBIOS_MIN_IO + hose->resources[0].start)
 199                         start = PCIBIOS_MIN_IO + hose->resources[0].start;
 200
 201                 /*
 202                  * Put everything into 0x00-0xff region modulo 0x400.
 203                  */
 204                 if (start & 0x300)
 205                         start = (start + 0x3ff) & ~0x3ff;
 206         }
 207
 208         return start;
 209 }
 210
 211 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
 212                              struct resource *res)
 213 {
 214         struct pci_channel *hose = dev->sysdata;
 215         unsigned long offset = 0;
 216
 217         if (res->flags & IORESOURCE_IO)
 218                 offset = hose->io_offset;
 219         else if (res->flags & IORESOURCE_MEM)
 220                 offset = hose->mem_offset;
 221
 222         region->start = res->start - offset;
 223         region->end = res->end - offset;
 224 }
 225
 226 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
 227                              struct pci_bus_region *region)
 228 {
 229         struct pci_channel *hose = dev->sysdata;
 230         unsigned long offset = 0;
 231
 232         if (res->flags & IORESOURCE_IO)
 233                 offset = hose->io_offset;
 234         else if (res->flags & IORESOURCE_MEM)
 235                 offset = hose->mem_offset;
 236
 237         res->start = region->start + offset;
 238         res->end = region->end + offset;
 239 }
 240
 241 int pcibios_enable_device(struct pci_dev *dev, int mask)
 242 {
 243         return pci_enable_resources(dev, mask);
 244 }
 245
 246 /*
 247  *  If we set up a device for bus mastering, we need to check and set
 248  *  the latency timer as it may not be properly set.
 249  */
 250 static unsigned int pcibios_max_latency = 255;
 251
 252 void pcibios_set_master(struct pci_dev *dev)
 253 {
 254         u8 lat;
 255         pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
 256         if (lat < 16)
 257                 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
 258         else if (lat > pcibios_max_latency)
 259                 lat = pcibios_max_latency;
 260         else
 261                 return;
 262         printk(KERN_INFO "PCI: Setting latency timer of device %s to %d\n",
 263                pci_name(dev), lat);
 264         pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
 265 }
 266
 267 void __init pcibios_update_irq(struct pci_dev *dev, int irq)
 268 {
 269         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 270 }
 271
 272 char * __devinit __weak pcibios_setup(char *str)
 273 {
 274         return str;
 275 }
 276
 277 static void __init
 278 pcibios_bus_report_status_early(struct pci_channel *hose,
 279                                 int top_bus, int current_bus,
 280                                 unsigned int status_mask, int warn)
 281 {
 282         unsigned int pci_devfn;
 283         u16 status;
 284         int ret;
 285
 286         for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
 287                 if (PCI_FUNC(pci_devfn))
 288                         continue;
 289                 ret = early_read_config_word(hose, top_bus, current_bus,
 290                                              pci_devfn, PCI_STATUS, &status);
 291                 if (ret != PCIBIOS_SUCCESSFUL)
 292                         continue;
 293                 if (status == 0xffff)
 294                         continue;
 295
 296                 early_write_config_word(hose, top_bus, current_bus,
 297                                         pci_devfn, PCI_STATUS,
 298                                         status & status_mask);
 299                 if (warn)
 300                         printk("(%02x:%02x: %04X) ", current_bus,
 301                                pci_devfn, status);
 302         }
 303 }
 304
 305 /*
 306  * We can't use pci_find_device() here since we are
 307  * called from interrupt context.
 308  */
 309 static void __init_refok
 310 pcibios_bus_report_status(struct pci_bus *bus, unsigned int status_mask,
 311                           int warn)
 312 {
 313         struct pci_dev *dev;
 314
 315         list_for_each_entry(dev, &bus->devices, bus_list) {
 316                 u16 status;
 317
 318                 /*
 319                  * ignore host bridge - we handle
 320                  * that separately
 321                  */
 322                 if (dev->bus->number == 0 && dev->devfn == 0)
 323                         continue;
 324
 325                 pci_read_config_word(dev, PCI_STATUS, &status);
 326                 if (status == 0xffff)
 327                         continue;
 328
 329                 if ((status & status_mask) == 0)
 330                         continue;
 331
 332                 /* clear the status errors */
 333                 pci_write_config_word(dev, PCI_STATUS, status & status_mask);
 334
 335                 if (warn)
 336                         printk("(%s: %04X) ", pci_name(dev), status);
 337         }
 338
 339         list_for_each_entry(dev, &bus->devices, bus_list)
 340                 if (dev->subordinate)
 341                         pcibios_bus_report_status(dev->subordinate, status_mask, warn);
 342 }
 343
 344 void __init_refok pcibios_report_status(unsigned int status_mask, int warn)
 345 {
 346         struct pci_channel *hose;
 347
 348         for (hose = hose_head; hose; hose = hose->next) {
 349                 if (unlikely(!hose->bus))
 350                         pcibios_bus_report_status_early(hose, hose_head->index,
 351                                         hose->index, status_mask, warn);
 352                 else
 353                         pcibios_bus_report_status(hose->bus, status_mask, warn);
 354         }
 355 }
 356
 357 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
 358                         enum pci_mmap_state mmap_state, int write_combine)
 359 {
 360         /*
 361          * I/O space can be accessed via normal processor loads and stores on
 362          * this platform but for now we elect not to do this and portable
 363          * drivers should not do this anyway.
 364          */
 365         if (mmap_state == pci_mmap_io)
 366                 return -EINVAL;
 367
 368         /*
 369          * Ignore write-combine; for now only return uncached mappings.
 370          */
 371         vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
 372
 373         return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
 374                                vma->vm_end - vma->vm_start,
 375                                vma->vm_page_prot);
 376 }
 377
 378 #ifndef CONFIG_GENERIC_IOMAP
 379
 380 static void __iomem *ioport_map_pci(struct pci_dev *dev,
 381                                     unsigned long port, unsigned int nr)
 382 {
 383         struct pci_channel *chan = dev->sysdata;
 384
 385         if (unlikely(!chan->io_map_base)) {
 386                 chan->io_map_base = sh_io_port_base;
 387
 388                 if (pci_domains_supported)
 389                         panic("To avoid data corruption io_map_base MUST be "
 390                               "set with multiple PCI domains.");
 391         }
 392
 393         return (void __iomem *)(chan->io_map_base + port);
 394 }
 395
 396 void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
 397 {
 398         resource_size_t start = pci_resource_start(dev, bar);
 399         resource_size_t len = pci_resource_len(dev, bar);
 400         unsigned long flags = pci_resource_flags(dev, bar);
 401
 402         if (unlikely(!len || !start))
 403                 return NULL;
 404         if (maxlen && len > maxlen)
 405                 len = maxlen;
 406
 407         if (flags & IORESOURCE_IO)
 408                 return ioport_map_pci(dev, start, len);
 409         if (flags & IORESOURCE_MEM) {
 410                 if (flags & IORESOURCE_CACHEABLE)
 411                         return ioremap(start, len);
 412                 return ioremap_nocache(start, len);
 413         }
 414
 415         return NULL;
 416 }
 417 EXPORT_SYMBOL(pci_iomap);
 418
 419 void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
 420 {
 421         iounmap(addr);
 422 }
 423 EXPORT_SYMBOL(pci_iounmap);
 424
 425 #endif /* CONFIG_GENERIC_IOMAP */
 426
 427 #ifdef CONFIG_HOTPLUG
 428 EXPORT_SYMBOL(pcibios_resource_to_bus);
 429 EXPORT_SYMBOL(pcibios_bus_to_resource);
 430 EXPORT_SYMBOL(PCIBIOS_MIN_IO);
 431 EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
 432 #endif