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Add linux-next specific files for 20110831
[linux-2.6/next.git] / arch / x86 / kvm / paging_tmpl.h
blob92994100638b26749519bc69d9c59b5a4ba10cc7
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 *
12 * Authors:
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
21 /*
22 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
23 * so the code in this file is compiled twice, once per pte size.
24 */
25
26 #if PTTYPE == 64
27 #define pt_element_t u64
28 #define guest_walker guest_walker64
29 #define FNAME(name) paging##64_##name
30 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
31 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
32 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
33 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
34 #define PT_LEVEL_BITS PT64_LEVEL_BITS
35 #ifdef CONFIG_X86_64
36 #define PT_MAX_FULL_LEVELS 4
37 #define CMPXCHG cmpxchg
38 #else
39 #define CMPXCHG cmpxchg64
40 #define PT_MAX_FULL_LEVELS 2
41 #endif
42 #elif PTTYPE == 32
43 #define pt_element_t u32
44 #define guest_walker guest_walker32
45 #define FNAME(name) paging##32_##name
46 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
47 #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
48 #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
49 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
50 #define PT_LEVEL_BITS PT32_LEVEL_BITS
51 #define PT_MAX_FULL_LEVELS 2
52 #define CMPXCHG cmpxchg
53 #else
54 #error Invalid PTTYPE value
55 #endif
56
57 #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
58 #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
59
60 /*
61 * The guest_walker structure emulates the behavior of the hardware page
62 * table walker.
63 */
64 struct guest_walker {
65 int level;
66 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
67 pt_element_t ptes[PT_MAX_FULL_LEVELS];
68 pt_element_t prefetch_ptes[PTE_PREFETCH_NUM];
69 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
70 unsigned pt_access;
71 unsigned pte_access;
72 gfn_t gfn;
73 struct x86_exception fault;
74 };
75
76 static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
77 {
78 return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
79 }
80
81 static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
82 pt_element_t __user *ptep_user, unsigned index,
83 pt_element_t orig_pte, pt_element_t new_pte)
84 {
85 int npages;
86 pt_element_t ret;
87 pt_element_t *table;
88 struct page *page;
89
90 npages = get_user_pages_fast((unsigned long)ptep_user, 1, 1, &page);
91 /* Check if the user is doing something meaningless. */
92 if (unlikely(npages != 1))
93 return -EFAULT;
94
95 table = kmap_atomic(page, KM_USER0);
96 ret = CMPXCHG(&table[index], orig_pte, new_pte);
97 kunmap_atomic(table, KM_USER0);
98
99 kvm_release_page_dirty(page);
100
101 return (ret != orig_pte);
102 }
103
104 static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte,
105 bool last)
106 {
107 unsigned access;
108
109 access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
110 if (last && !is_dirty_gpte(gpte))
111 access &= ~ACC_WRITE_MASK;
112
113 #if PTTYPE == 64
114 if (vcpu->arch.mmu.nx)
115 access &= ~(gpte >> PT64_NX_SHIFT);
116 #endif
117 return access;
118 }
119
120 static bool FNAME(is_last_gpte)(struct guest_walker *walker,
121 struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
122 pt_element_t gpte)
123 {
124 if (walker->level == PT_PAGE_TABLE_LEVEL)
125 return true;
126
127 if ((walker->level == PT_DIRECTORY_LEVEL) && is_large_pte(gpte) &&
128 (PTTYPE == 64 || is_pse(vcpu)))
129 return true;
130
131 if ((walker->level == PT_PDPE_LEVEL) && is_large_pte(gpte) &&
132 (mmu->root_level == PT64_ROOT_LEVEL))
133 return true;
134
135 return false;
136 }
137
138 /*
139 * Fetch a guest pte for a guest virtual address
140 */
141 static int FNAME(walk_addr_generic)(struct guest_walker *walker,
142 struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
143 gva_t addr, u32 access)
144 {
145 pt_element_t pte;
146 pt_element_t __user *uninitialized_var(ptep_user);
147 gfn_t table_gfn;
148 unsigned index, pt_access, uninitialized_var(pte_access);
149 gpa_t pte_gpa;
150 bool eperm, last_gpte;
151 int offset;
152 const int write_fault = access & PFERR_WRITE_MASK;
153 const int user_fault = access & PFERR_USER_MASK;
154 const int fetch_fault = access & PFERR_FETCH_MASK;
155 u16 errcode = 0;
156
157 trace_kvm_mmu_pagetable_walk(addr, write_fault, user_fault,
158 fetch_fault);
159 retry_walk:
160 eperm = false;
161 walker->level = mmu->root_level;
162 pte = mmu->get_cr3(vcpu);
163
164 #if PTTYPE == 64
165 if (walker->level == PT32E_ROOT_LEVEL) {
166 pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3);
167 trace_kvm_mmu_paging_element(pte, walker->level);
168 if (!is_present_gpte(pte))
169 goto error;
170 --walker->level;
171 }
172 #endif
173 ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
174 (mmu->get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0);
175
176 pt_access = ACC_ALL;
177
178 for (;;) {
179 gfn_t real_gfn;
180 unsigned long host_addr;
181
182 index = PT_INDEX(addr, walker->level);
183
184 table_gfn = gpte_to_gfn(pte);
185 offset = index * sizeof(pt_element_t);
186 pte_gpa = gfn_to_gpa(table_gfn) + offset;
187 walker->table_gfn[walker->level - 1] = table_gfn;
188 walker->pte_gpa[walker->level - 1] = pte_gpa;
189
190 real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn),
191 PFERR_USER_MASK|PFERR_WRITE_MASK);
192 if (unlikely(real_gfn == UNMAPPED_GVA))
193 goto error;
194 real_gfn = gpa_to_gfn(real_gfn);
195
196 host_addr = gfn_to_hva(vcpu->kvm, real_gfn);
197 if (unlikely(kvm_is_error_hva(host_addr)))
198 goto error;
199
200 ptep_user = (pt_element_t __user *)((void *)host_addr + offset);
201 if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte))))
202 goto error;
203
204 trace_kvm_mmu_paging_element(pte, walker->level);
205
206 if (unlikely(!is_present_gpte(pte)))
207 goto error;
208
209 if (unlikely(is_rsvd_bits_set(&vcpu->arch.mmu, pte,
210 walker->level))) {
211 errcode |= PFERR_RSVD_MASK | PFERR_PRESENT_MASK;
212 goto error;
213 }
214
215 if (!check_write_user_access(vcpu, write_fault, user_fault,
216 pte))
217 eperm = true;
218
219 #if PTTYPE == 64
220 if (unlikely(fetch_fault && (pte & PT64_NX_MASK)))
221 eperm = true;
222 #endif
223
224 last_gpte = FNAME(is_last_gpte)(walker, vcpu, mmu, pte);
225 if (last_gpte) {
226 pte_access = pt_access &
227 FNAME(gpte_access)(vcpu, pte, true);
228 /* check if the kernel is fetching from user page */
229 if (unlikely(pte_access & PT_USER_MASK) &&
230 kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
231 if (fetch_fault && !user_fault)
232 eperm = true;
233 }
234
235 if (!eperm && unlikely(!(pte & PT_ACCESSED_MASK))) {
236 int ret;
237 trace_kvm_mmu_set_accessed_bit(table_gfn, index,
238 sizeof(pte));
239 ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index,
240 pte, pte|PT_ACCESSED_MASK);
241 if (unlikely(ret < 0))
242 goto error;
243 else if (ret)
244 goto retry_walk;
245
246 mark_page_dirty(vcpu->kvm, table_gfn);
247 pte |= PT_ACCESSED_MASK;
248 }
249
250 walker->ptes[walker->level - 1] = pte;
251
252 if (last_gpte) {
253 int lvl = walker->level;
254 gpa_t real_gpa;
255 gfn_t gfn;
256 u32 ac;
257
258 gfn = gpte_to_gfn_lvl(pte, lvl);
259 gfn += (addr & PT_LVL_OFFSET_MASK(lvl)) >> PAGE_SHIFT;
260
261 if (PTTYPE == 32 &&
262 walker->level == PT_DIRECTORY_LEVEL &&
263 is_cpuid_PSE36())
264 gfn += pse36_gfn_delta(pte);
265
266 ac = write_fault | fetch_fault | user_fault;
267
268 real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn),
269 ac);
270 if (real_gpa == UNMAPPED_GVA)
271 return 0;
272
273 walker->gfn = real_gpa >> PAGE_SHIFT;
274
275 break;
276 }
277
278 pt_access &= FNAME(gpte_access)(vcpu, pte, false);
279 --walker->level;
280 }
281
282 if (unlikely(eperm)) {
283 errcode |= PFERR_PRESENT_MASK;
284 goto error;
285 }
286
287 if (write_fault && unlikely(!is_dirty_gpte(pte))) {
288 int ret;
289
290 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
291 ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index,
292 pte, pte|PT_DIRTY_MASK);
293 if (unlikely(ret < 0))
294 goto error;
295 else if (ret)
296 goto retry_walk;
297
298 mark_page_dirty(vcpu->kvm, table_gfn);
299 pte |= PT_DIRTY_MASK;
300 walker->ptes[walker->level - 1] = pte;
301 }
302
303 walker->pt_access = pt_access;
304 walker->pte_access = pte_access;
305 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
306 __func__, (u64)pte, pte_access, pt_access);
307 return 1;
308
309 error:
310 errcode |= write_fault | user_fault;
311 if (fetch_fault && (mmu->nx ||
312 kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)))
313 errcode |= PFERR_FETCH_MASK;
314
315 walker->fault.vector = PF_VECTOR;
316 walker->fault.error_code_valid = true;
317 walker->fault.error_code = errcode;
318 walker->fault.address = addr;
319 walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu;
320
321 trace_kvm_mmu_walker_error(walker->fault.error_code);
322 return 0;
323 }
324
325 static int FNAME(walk_addr)(struct guest_walker *walker,
326 struct kvm_vcpu *vcpu, gva_t addr, u32 access)
327 {
328 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr,
329 access);
330 }
331
332 static int FNAME(walk_addr_nested)(struct guest_walker *walker,
333 struct kvm_vcpu *vcpu, gva_t addr,
334 u32 access)
335 {
336 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu,
337 addr, access);
338 }
339
340 static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu,
341 struct kvm_mmu_page *sp, u64 *spte,
342 pt_element_t gpte)
343 {
344 if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL))
345 goto no_present;
346
347 if (!is_present_gpte(gpte))
348 goto no_present;
349
350 if (!(gpte & PT_ACCESSED_MASK))
351 goto no_present;
352
353 return false;
354
355 no_present:
356 drop_spte(vcpu->kvm, spte);
357 return true;
358 }
359
360 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
361 u64 *spte, const void *pte)
362 {
363 pt_element_t gpte;
364 unsigned pte_access;
365 pfn_t pfn;
366
367 gpte = *(const pt_element_t *)pte;
368 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
369 return;
370
371 pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
372 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte, true);
373 pfn = gfn_to_pfn_atomic(vcpu->kvm, gpte_to_gfn(gpte));
374 if (mmu_invalid_pfn(pfn)) {
375 kvm_release_pfn_clean(pfn);
376 return;
377 }
378
379 /*
380 * we call mmu_set_spte() with host_writable = true because that
381 * vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1).
382 */
383 mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0,
384 NULL, PT_PAGE_TABLE_LEVEL,
385 gpte_to_gfn(gpte), pfn, true, true);
386 }
387
388 static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu,
389 struct guest_walker *gw, int level)
390 {
391 pt_element_t curr_pte;
392 gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1];
393 u64 mask;
394 int r, index;
395
396 if (level == PT_PAGE_TABLE_LEVEL) {
397 mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1;
398 base_gpa = pte_gpa & ~mask;
399 index = (pte_gpa - base_gpa) / sizeof(pt_element_t);
400
401 r = kvm_read_guest_atomic(vcpu->kvm, base_gpa,
402 gw->prefetch_ptes, sizeof(gw->prefetch_ptes));
403 curr_pte = gw->prefetch_ptes[index];
404 } else
405 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa,
406 &curr_pte, sizeof(curr_pte));
407
408 return r || curr_pte != gw->ptes[level - 1];
409 }
410
411 static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
412 u64 *sptep)
413 {
414 struct kvm_mmu_page *sp;
415 pt_element_t *gptep = gw->prefetch_ptes;
416 u64 *spte;
417 int i;
418
419 sp = page_header(__pa(sptep));
420
421 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
422 return;
423
424 if (sp->role.direct)
425 return __direct_pte_prefetch(vcpu, sp, sptep);
426
427 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
428 spte = sp->spt + i;
429
430 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
431 pt_element_t gpte;
432 unsigned pte_access;
433 gfn_t gfn;
434 pfn_t pfn;
435
436 if (spte == sptep)
437 continue;
438
439 if (is_shadow_present_pte(*spte))
440 continue;
441
442 gpte = gptep[i];
443
444 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
445 continue;
446
447 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte,
448 true);
449 gfn = gpte_to_gfn(gpte);
450 pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn,
451 pte_access & ACC_WRITE_MASK);
452 if (mmu_invalid_pfn(pfn)) {
453 kvm_release_pfn_clean(pfn);
454 break;
455 }
456
457 mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0,
458 NULL, PT_PAGE_TABLE_LEVEL, gfn,
459 pfn, true, true);
460 }
461 }
462
463 /*
464 * Fetch a shadow pte for a specific level in the paging hierarchy.
465 */
466 static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
467 struct guest_walker *gw,
468 int user_fault, int write_fault, int hlevel,
469 int *emulate, pfn_t pfn, bool map_writable,
470 bool prefault)
471 {
472 unsigned access = gw->pt_access;
473 struct kvm_mmu_page *sp = NULL;
474 int top_level;
475 unsigned direct_access;
476 struct kvm_shadow_walk_iterator it;
477
478 if (!is_present_gpte(gw->ptes[gw->level - 1]))
479 return NULL;
480
481 direct_access = gw->pte_access;
482
483 top_level = vcpu->arch.mmu.root_level;
484 if (top_level == PT32E_ROOT_LEVEL)
485 top_level = PT32_ROOT_LEVEL;
486 /*
487 * Verify that the top-level gpte is still there. Since the page
488 * is a root page, it is either write protected (and cannot be
489 * changed from now on) or it is invalid (in which case, we don't
490 * really care if it changes underneath us after this point).
491 */
492 if (FNAME(gpte_changed)(vcpu, gw, top_level))
493 goto out_gpte_changed;
494
495 for (shadow_walk_init(&it, vcpu, addr);
496 shadow_walk_okay(&it) && it.level > gw->level;
497 shadow_walk_next(&it)) {
498 gfn_t table_gfn;
499
500 drop_large_spte(vcpu, it.sptep);
501
502 sp = NULL;
503 if (!is_shadow_present_pte(*it.sptep)) {
504 table_gfn = gw->table_gfn[it.level - 2];
505 sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1,
506 false, access, it.sptep);
507 }
508
509 /*
510 * Verify that the gpte in the page we've just write
511 * protected is still there.
512 */
513 if (FNAME(gpte_changed)(vcpu, gw, it.level - 1))
514 goto out_gpte_changed;
515
516 if (sp)
517 link_shadow_page(it.sptep, sp);
518 }
519
520 for (;
521 shadow_walk_okay(&it) && it.level > hlevel;
522 shadow_walk_next(&it)) {
523 gfn_t direct_gfn;
524
525 validate_direct_spte(vcpu, it.sptep, direct_access);
526
527 drop_large_spte(vcpu, it.sptep);
528
529 if (is_shadow_present_pte(*it.sptep))
530 continue;
531
532 direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
533
534 sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1,
535 true, direct_access, it.sptep);
536 link_shadow_page(it.sptep, sp);
537 }
538
539 mmu_set_spte(vcpu, it.sptep, access, gw->pte_access,
540 user_fault, write_fault, emulate, it.level,
541 gw->gfn, pfn, prefault, map_writable);
542 FNAME(pte_prefetch)(vcpu, gw, it.sptep);
543
544 return it.sptep;
545
546 out_gpte_changed:
547 if (sp)
548 kvm_mmu_put_page(sp, it.sptep);
549 kvm_release_pfn_clean(pfn);
550 return NULL;
551 }
552
553 /*
554 * Page fault handler. There are several causes for a page fault:
555 * - there is no shadow pte for the guest pte
556 * - write access through a shadow pte marked read only so that we can set
557 * the dirty bit
558 * - write access to a shadow pte marked read only so we can update the page
559 * dirty bitmap, when userspace requests it
560 * - mmio access; in this case we will never install a present shadow pte
561 * - normal guest page fault due to the guest pte marked not present, not
562 * writable, or not executable
563 *
564 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
565 * a negative value on error.
566 */
567 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code,
568 bool prefault)
569 {
570 int write_fault = error_code & PFERR_WRITE_MASK;
571 int user_fault = error_code & PFERR_USER_MASK;
572 struct guest_walker walker;
573 u64 *sptep;
574 int emulate = 0;
575 int r;
576 pfn_t pfn;
577 int level = PT_PAGE_TABLE_LEVEL;
578 int force_pt_level;
579 unsigned long mmu_seq;
580 bool map_writable;
581
582 pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
583
584 if (unlikely(error_code & PFERR_RSVD_MASK))
585 return handle_mmio_page_fault(vcpu, addr, error_code,
586 mmu_is_nested(vcpu));
587
588 r = mmu_topup_memory_caches(vcpu);
589 if (r)
590 return r;
591
592 /*
593 * Look up the guest pte for the faulting address.
594 */
595 r = FNAME(walk_addr)(&walker, vcpu, addr, error_code);
596
597 /*
598 * The page is not mapped by the guest. Let the guest handle it.
599 */
600 if (!r) {
601 pgprintk("%s: guest page fault\n", __func__);
602 if (!prefault) {
603 inject_page_fault(vcpu, &walker.fault);
604 /* reset fork detector */
605 vcpu->arch.last_pt_write_count = 0;
606 }
607 return 0;
608 }
609
610 if (walker.level >= PT_DIRECTORY_LEVEL)
611 force_pt_level = mapping_level_dirty_bitmap(vcpu, walker.gfn);
612 else
613 force_pt_level = 1;
614 if (!force_pt_level) {
615 level = min(walker.level, mapping_level(vcpu, walker.gfn));
616 walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
617 }
618
619 mmu_seq = vcpu->kvm->mmu_notifier_seq;
620 smp_rmb();
621
622 if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault,
623 &map_writable))
624 return 0;
625
626 if (handle_abnormal_pfn(vcpu, mmu_is_nested(vcpu) ? 0 : addr,
627 walker.gfn, pfn, walker.pte_access, &r))
628 return r;
629
630 spin_lock(&vcpu->kvm->mmu_lock);
631 if (mmu_notifier_retry(vcpu, mmu_seq))
632 goto out_unlock;
633
634 trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT);
635 kvm_mmu_free_some_pages(vcpu);
636 if (!force_pt_level)
637 transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level);
638 sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
639 level, &emulate, pfn, map_writable, prefault);
640 (void)sptep;
641 pgprintk("%s: shadow pte %p %llx emulate %d\n", __func__,
642 sptep, *sptep, emulate);
643
644 if (!emulate)
645 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
646
647 ++vcpu->stat.pf_fixed;
648 trace_kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT);
649 spin_unlock(&vcpu->kvm->mmu_lock);
650
651 return emulate;
652
653 out_unlock:
654 spin_unlock(&vcpu->kvm->mmu_lock);
655 kvm_release_pfn_clean(pfn);
656 return 0;
657 }
658
659 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
660 {
661 struct kvm_shadow_walk_iterator iterator;
662 struct kvm_mmu_page *sp;
663 gpa_t pte_gpa = -1;
664 int level;
665 u64 *sptep;
666 int need_flush = 0;
667
668 vcpu_clear_mmio_info(vcpu, gva);
669
670 spin_lock(&vcpu->kvm->mmu_lock);
671
672 for_each_shadow_entry(vcpu, gva, iterator) {
673 level = iterator.level;
674 sptep = iterator.sptep;
675
676 sp = page_header(__pa(sptep));
677 if (is_last_spte(*sptep, level)) {
678 int offset, shift;
679
680 if (!sp->unsync)
681 break;
682
683 shift = PAGE_SHIFT -
684 (PT_LEVEL_BITS - PT64_LEVEL_BITS) * level;
685 offset = sp->role.quadrant << shift;
686
687 pte_gpa = (sp->gfn << PAGE_SHIFT) + offset;
688 pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
689
690 if (is_shadow_present_pte(*sptep)) {
691 if (is_large_pte(*sptep))
692 --vcpu->kvm->stat.lpages;
693 drop_spte(vcpu->kvm, sptep);
694 need_flush = 1;
695 } else if (is_mmio_spte(*sptep))
696 mmu_spte_clear_no_track(sptep);
697
698 break;
699 }
700
701 if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
702 break;
703 }
704
705 if (need_flush)
706 kvm_flush_remote_tlbs(vcpu->kvm);
707
708 atomic_inc(&vcpu->kvm->arch.invlpg_counter);
709
710 spin_unlock(&vcpu->kvm->mmu_lock);
711
712 if (pte_gpa == -1)
713 return;
714
715 if (mmu_topup_memory_caches(vcpu))
716 return;
717 kvm_mmu_pte_write(vcpu, pte_gpa, NULL, sizeof(pt_element_t), 0);
718 }
719
720 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
721 struct x86_exception *exception)
722 {
723 struct guest_walker walker;
724 gpa_t gpa = UNMAPPED_GVA;
725 int r;
726
727 r = FNAME(walk_addr)(&walker, vcpu, vaddr, access);
728
729 if (r) {
730 gpa = gfn_to_gpa(walker.gfn);
731 gpa |= vaddr & ~PAGE_MASK;
732 } else if (exception)
733 *exception = walker.fault;
734
735 return gpa;
736 }
737
738 static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr,
739 u32 access,
740 struct x86_exception *exception)
741 {
742 struct guest_walker walker;
743 gpa_t gpa = UNMAPPED_GVA;
744 int r;
745
746 r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access);
747
748 if (r) {
749 gpa = gfn_to_gpa(walker.gfn);
750 gpa |= vaddr & ~PAGE_MASK;
751 } else if (exception)
752 *exception = walker.fault;
753
754 return gpa;
755 }
756
757 /*
758 * Using the cached information from sp->gfns is safe because:
759 * - The spte has a reference to the struct page, so the pfn for a given gfn
760 * can't change unless all sptes pointing to it are nuked first.
761 *
762 * Note:
763 * We should flush all tlbs if spte is dropped even though guest is
764 * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page
765 * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't
766 * used by guest then tlbs are not flushed, so guest is allowed to access the
767 * freed pages.
768 * And we increase kvm->tlbs_dirty to delay tlbs flush in this case.
769 */
770 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
771 {
772 int i, offset, nr_present;
773 bool host_writable;
774 gpa_t first_pte_gpa;
775
776 offset = nr_present = 0;
777
778 /* direct kvm_mmu_page can not be unsync. */
779 BUG_ON(sp->role.direct);
780
781 if (PTTYPE == 32)
782 offset = sp->role.quadrant << PT64_LEVEL_BITS;
783
784 first_pte_gpa = gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
785
786 for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
787 unsigned pte_access;
788 pt_element_t gpte;
789 gpa_t pte_gpa;
790 gfn_t gfn;
791
792 if (!sp->spt[i])
793 continue;
794
795 pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
796
797 if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
798 sizeof(pt_element_t)))
799 return -EINVAL;
800
801 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) {
802 vcpu->kvm->tlbs_dirty++;
803 continue;
804 }
805
806 gfn = gpte_to_gfn(gpte);
807 pte_access = sp->role.access;
808 pte_access &= FNAME(gpte_access)(vcpu, gpte, true);
809
810 if (sync_mmio_spte(&sp->spt[i], gfn, pte_access, &nr_present))
811 continue;
812
813 if (gfn != sp->gfns[i]) {
814 drop_spte(vcpu->kvm, &sp->spt[i]);
815 vcpu->kvm->tlbs_dirty++;
816 continue;
817 }
818
819 nr_present++;
820
821 host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE;
822
823 set_spte(vcpu, &sp->spt[i], pte_access, 0, 0,
824 PT_PAGE_TABLE_LEVEL, gfn,
825 spte_to_pfn(sp->spt[i]), true, false,
826 host_writable);
827 }
828
829 return !nr_present;
830 }
831
832 #undef pt_element_t
833 #undef guest_walker
834 #undef FNAME
835 #undef PT_BASE_ADDR_MASK
836 #undef PT_INDEX
837 #undef PT_LVL_ADDR_MASK
838 #undef PT_LVL_OFFSET_MASK
839 #undef PT_LEVEL_BITS
840 #undef PT_MAX_FULL_LEVELS
841 #undef gpte_to_gfn
842 #undef gpte_to_gfn_lvl
843 #undef CMPXCHG
linux-next