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Add linux-next specific files for 20110831
[linux-2.6/next.git] / arch / x86 / kvm / vmx.c
blob5e8d411b0a815133768acf80c1c842294ee765ae
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
19 #include "irq.h"
20 #include "mmu.h"
21
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/mm.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31 #include <linux/tboot.h>
32 #include "kvm_cache_regs.h"
33 #include "x86.h"
34
35 #include <asm/io.h>
36 #include <asm/desc.h>
37 #include <asm/vmx.h>
38 #include <asm/virtext.h>
39 #include <asm/mce.h>
40 #include <asm/i387.h>
41 #include <asm/xcr.h>
42
43 #include "trace.h"
44
45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
46 #define __ex_clear(x, reg) \
47 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
48
49 MODULE_AUTHOR("Qumranet");
50 MODULE_LICENSE("GPL");
51
52 static int __read_mostly enable_vpid = 1;
53 module_param_named(vpid, enable_vpid, bool, 0444);
54
55 static int __read_mostly flexpriority_enabled = 1;
56 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
57
58 static int __read_mostly enable_ept = 1;
59 module_param_named(ept, enable_ept, bool, S_IRUGO);
60
61 static int __read_mostly enable_unrestricted_guest = 1;
62 module_param_named(unrestricted_guest,
63 enable_unrestricted_guest, bool, S_IRUGO);
64
65 static int __read_mostly emulate_invalid_guest_state = 0;
66 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
67
68 static int __read_mostly vmm_exclusive = 1;
69 module_param(vmm_exclusive, bool, S_IRUGO);
70
71 static int __read_mostly yield_on_hlt = 1;
72 module_param(yield_on_hlt, bool, S_IRUGO);
73
74 /*
75 * If nested=1, nested virtualization is supported, i.e., guests may use
76 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
77 * use VMX instructions.
78 */
79 static int __read_mostly nested = 0;
80 module_param(nested, bool, S_IRUGO);
81
82 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
83 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
84 #define KVM_GUEST_CR0_MASK \
85 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
86 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
87 (X86_CR0_WP | X86_CR0_NE)
88 #define KVM_VM_CR0_ALWAYS_ON \
89 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
90 #define KVM_CR4_GUEST_OWNED_BITS \
91 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
92 | X86_CR4_OSXMMEXCPT)
93
94 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
95 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
96
97 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
98
99 /*
100 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
101 * ple_gap: upper bound on the amount of time between two successive
102 * executions of PAUSE in a loop. Also indicate if ple enabled.
103 * According to test, this time is usually smaller than 128 cycles.
104 * ple_window: upper bound on the amount of time a guest is allowed to execute
105 * in a PAUSE loop. Tests indicate that most spinlocks are held for
106 * less than 2^12 cycles
107 * Time is measured based on a counter that runs at the same rate as the TSC,
108 * refer SDM volume 3b section 21.6.13 & 22.1.3.
109 */
110 #define KVM_VMX_DEFAULT_PLE_GAP 128
111 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
112 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
113 module_param(ple_gap, int, S_IRUGO);
114
115 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
116 module_param(ple_window, int, S_IRUGO);
117
118 #define NR_AUTOLOAD_MSRS 1
119 #define VMCS02_POOL_SIZE 1
120
121 struct vmcs {
122 u32 revision_id;
123 u32 abort;
124 char data[0];
125 };
126
127 /*
128 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
129 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
130 * loaded on this CPU (so we can clear them if the CPU goes down).
131 */
132 struct loaded_vmcs {
133 struct vmcs *vmcs;
134 int cpu;
135 int launched;
136 struct list_head loaded_vmcss_on_cpu_link;
137 };
138
139 struct shared_msr_entry {
140 unsigned index;
141 u64 data;
142 u64 mask;
143 };
144
145 /*
146 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
147 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
148 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
149 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
150 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
151 * More than one of these structures may exist, if L1 runs multiple L2 guests.
152 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
153 * underlying hardware which will be used to run L2.
154 * This structure is packed to ensure that its layout is identical across
155 * machines (necessary for live migration).
156 * If there are changes in this struct, VMCS12_REVISION must be changed.
157 */
158 typedef u64 natural_width;
159 struct __packed vmcs12 {
160 /* According to the Intel spec, a VMCS region must start with the
161 * following two fields. Then follow implementation-specific data.
162 */
163 u32 revision_id;
164 u32 abort;
165
166 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
167 u32 padding[7]; /* room for future expansion */
168
169 u64 io_bitmap_a;
170 u64 io_bitmap_b;
171 u64 msr_bitmap;
172 u64 vm_exit_msr_store_addr;
173 u64 vm_exit_msr_load_addr;
174 u64 vm_entry_msr_load_addr;
175 u64 tsc_offset;
176 u64 virtual_apic_page_addr;
177 u64 apic_access_addr;
178 u64 ept_pointer;
179 u64 guest_physical_address;
180 u64 vmcs_link_pointer;
181 u64 guest_ia32_debugctl;
182 u64 guest_ia32_pat;
183 u64 guest_ia32_efer;
184 u64 guest_ia32_perf_global_ctrl;
185 u64 guest_pdptr0;
186 u64 guest_pdptr1;
187 u64 guest_pdptr2;
188 u64 guest_pdptr3;
189 u64 host_ia32_pat;
190 u64 host_ia32_efer;
191 u64 host_ia32_perf_global_ctrl;
192 u64 padding64[8]; /* room for future expansion */
193 /*
194 * To allow migration of L1 (complete with its L2 guests) between
195 * machines of different natural widths (32 or 64 bit), we cannot have
196 * unsigned long fields with no explict size. We use u64 (aliased
197 * natural_width) instead. Luckily, x86 is little-endian.
198 */
199 natural_width cr0_guest_host_mask;
200 natural_width cr4_guest_host_mask;
201 natural_width cr0_read_shadow;
202 natural_width cr4_read_shadow;
203 natural_width cr3_target_value0;
204 natural_width cr3_target_value1;
205 natural_width cr3_target_value2;
206 natural_width cr3_target_value3;
207 natural_width exit_qualification;
208 natural_width guest_linear_address;
209 natural_width guest_cr0;
210 natural_width guest_cr3;
211 natural_width guest_cr4;
212 natural_width guest_es_base;
213 natural_width guest_cs_base;
214 natural_width guest_ss_base;
215 natural_width guest_ds_base;
216 natural_width guest_fs_base;
217 natural_width guest_gs_base;
218 natural_width guest_ldtr_base;
219 natural_width guest_tr_base;
220 natural_width guest_gdtr_base;
221 natural_width guest_idtr_base;
222 natural_width guest_dr7;
223 natural_width guest_rsp;
224 natural_width guest_rip;
225 natural_width guest_rflags;
226 natural_width guest_pending_dbg_exceptions;
227 natural_width guest_sysenter_esp;
228 natural_width guest_sysenter_eip;
229 natural_width host_cr0;
230 natural_width host_cr3;
231 natural_width host_cr4;
232 natural_width host_fs_base;
233 natural_width host_gs_base;
234 natural_width host_tr_base;
235 natural_width host_gdtr_base;
236 natural_width host_idtr_base;
237 natural_width host_ia32_sysenter_esp;
238 natural_width host_ia32_sysenter_eip;
239 natural_width host_rsp;
240 natural_width host_rip;
241 natural_width paddingl[8]; /* room for future expansion */
242 u32 pin_based_vm_exec_control;
243 u32 cpu_based_vm_exec_control;
244 u32 exception_bitmap;
245 u32 page_fault_error_code_mask;
246 u32 page_fault_error_code_match;
247 u32 cr3_target_count;
248 u32 vm_exit_controls;
249 u32 vm_exit_msr_store_count;
250 u32 vm_exit_msr_load_count;
251 u32 vm_entry_controls;
252 u32 vm_entry_msr_load_count;
253 u32 vm_entry_intr_info_field;
254 u32 vm_entry_exception_error_code;
255 u32 vm_entry_instruction_len;
256 u32 tpr_threshold;
257 u32 secondary_vm_exec_control;
258 u32 vm_instruction_error;
259 u32 vm_exit_reason;
260 u32 vm_exit_intr_info;
261 u32 vm_exit_intr_error_code;
262 u32 idt_vectoring_info_field;
263 u32 idt_vectoring_error_code;
264 u32 vm_exit_instruction_len;
265 u32 vmx_instruction_info;
266 u32 guest_es_limit;
267 u32 guest_cs_limit;
268 u32 guest_ss_limit;
269 u32 guest_ds_limit;
270 u32 guest_fs_limit;
271 u32 guest_gs_limit;
272 u32 guest_ldtr_limit;
273 u32 guest_tr_limit;
274 u32 guest_gdtr_limit;
275 u32 guest_idtr_limit;
276 u32 guest_es_ar_bytes;
277 u32 guest_cs_ar_bytes;
278 u32 guest_ss_ar_bytes;
279 u32 guest_ds_ar_bytes;
280 u32 guest_fs_ar_bytes;
281 u32 guest_gs_ar_bytes;
282 u32 guest_ldtr_ar_bytes;
283 u32 guest_tr_ar_bytes;
284 u32 guest_interruptibility_info;
285 u32 guest_activity_state;
286 u32 guest_sysenter_cs;
287 u32 host_ia32_sysenter_cs;
288 u32 padding32[8]; /* room for future expansion */
289 u16 virtual_processor_id;
290 u16 guest_es_selector;
291 u16 guest_cs_selector;
292 u16 guest_ss_selector;
293 u16 guest_ds_selector;
294 u16 guest_fs_selector;
295 u16 guest_gs_selector;
296 u16 guest_ldtr_selector;
297 u16 guest_tr_selector;
298 u16 host_es_selector;
299 u16 host_cs_selector;
300 u16 host_ss_selector;
301 u16 host_ds_selector;
302 u16 host_fs_selector;
303 u16 host_gs_selector;
304 u16 host_tr_selector;
305 };
306
307 /*
308 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
309 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
310 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
311 */
312 #define VMCS12_REVISION 0x11e57ed0
313
314 /*
315 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
316 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
317 * current implementation, 4K are reserved to avoid future complications.
318 */
319 #define VMCS12_SIZE 0x1000
320
321 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
322 struct vmcs02_list {
323 struct list_head list;
324 gpa_t vmptr;
325 struct loaded_vmcs vmcs02;
326 };
327
328 /*
329 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
330 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
331 */
332 struct nested_vmx {
333 /* Has the level1 guest done vmxon? */
334 bool vmxon;
335
336 /* The guest-physical address of the current VMCS L1 keeps for L2 */
337 gpa_t current_vmptr;
338 /* The host-usable pointer to the above */
339 struct page *current_vmcs12_page;
340 struct vmcs12 *current_vmcs12;
341
342 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
343 struct list_head vmcs02_pool;
344 int vmcs02_num;
345 u64 vmcs01_tsc_offset;
346 /* L2 must run next, and mustn't decide to exit to L1. */
347 bool nested_run_pending;
348 /*
349 * Guest pages referred to in vmcs02 with host-physical pointers, so
350 * we must keep them pinned while L2 runs.
351 */
352 struct page *apic_access_page;
353 };
354
355 struct vcpu_vmx {
356 struct kvm_vcpu vcpu;
357 unsigned long host_rsp;
358 u8 fail;
359 u8 cpl;
360 bool nmi_known_unmasked;
361 u32 exit_intr_info;
362 u32 idt_vectoring_info;
363 ulong rflags;
364 struct shared_msr_entry *guest_msrs;
365 int nmsrs;
366 int save_nmsrs;
367 #ifdef CONFIG_X86_64
368 u64 msr_host_kernel_gs_base;
369 u64 msr_guest_kernel_gs_base;
370 #endif
371 /*
372 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
373 * non-nested (L1) guest, it always points to vmcs01. For a nested
374 * guest (L2), it points to a different VMCS.
375 */
376 struct loaded_vmcs vmcs01;
377 struct loaded_vmcs *loaded_vmcs;
378 bool __launched; /* temporary, used in vmx_vcpu_run */
379 struct msr_autoload {
380 unsigned nr;
381 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
382 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
383 } msr_autoload;
384 struct {
385 int loaded;
386 u16 fs_sel, gs_sel, ldt_sel;
387 int gs_ldt_reload_needed;
388 int fs_reload_needed;
389 } host_state;
390 struct {
391 int vm86_active;
392 ulong save_rflags;
393 struct kvm_save_segment {
394 u16 selector;
395 unsigned long base;
396 u32 limit;
397 u32 ar;
398 } tr, es, ds, fs, gs;
399 } rmode;
400 struct {
401 u32 bitmask; /* 4 bits per segment (1 bit per field) */
402 struct kvm_save_segment seg[8];
403 } segment_cache;
404 int vpid;
405 bool emulation_required;
406
407 /* Support for vnmi-less CPUs */
408 int soft_vnmi_blocked;
409 ktime_t entry_time;
410 s64 vnmi_blocked_time;
411 u32 exit_reason;
412
413 bool rdtscp_enabled;
414
415 /* Support for a guest hypervisor (nested VMX) */
416 struct nested_vmx nested;
417 };
418
419 enum segment_cache_field {
420 SEG_FIELD_SEL = 0,
421 SEG_FIELD_BASE = 1,
422 SEG_FIELD_LIMIT = 2,
423 SEG_FIELD_AR = 3,
424
425 SEG_FIELD_NR = 4
426 };
427
428 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
429 {
430 return container_of(vcpu, struct vcpu_vmx, vcpu);
431 }
432
433 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
434 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
435 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
436 [number##_HIGH] = VMCS12_OFFSET(name)+4
437
438 static unsigned short vmcs_field_to_offset_table[] = {
439 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
440 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
441 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
442 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
443 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
444 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
445 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
446 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
447 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
448 FIELD(HOST_ES_SELECTOR, host_es_selector),
449 FIELD(HOST_CS_SELECTOR, host_cs_selector),
450 FIELD(HOST_SS_SELECTOR, host_ss_selector),
451 FIELD(HOST_DS_SELECTOR, host_ds_selector),
452 FIELD(HOST_FS_SELECTOR, host_fs_selector),
453 FIELD(HOST_GS_SELECTOR, host_gs_selector),
454 FIELD(HOST_TR_SELECTOR, host_tr_selector),
455 FIELD64(IO_BITMAP_A, io_bitmap_a),
456 FIELD64(IO_BITMAP_B, io_bitmap_b),
457 FIELD64(MSR_BITMAP, msr_bitmap),
458 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
459 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
460 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
461 FIELD64(TSC_OFFSET, tsc_offset),
462 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
463 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
464 FIELD64(EPT_POINTER, ept_pointer),
465 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
466 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
467 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
468 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
469 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
470 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
471 FIELD64(GUEST_PDPTR0, guest_pdptr0),
472 FIELD64(GUEST_PDPTR1, guest_pdptr1),
473 FIELD64(GUEST_PDPTR2, guest_pdptr2),
474 FIELD64(GUEST_PDPTR3, guest_pdptr3),
475 FIELD64(HOST_IA32_PAT, host_ia32_pat),
476 FIELD64(HOST_IA32_EFER, host_ia32_efer),
477 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
478 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
479 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
480 FIELD(EXCEPTION_BITMAP, exception_bitmap),
481 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
482 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
483 FIELD(CR3_TARGET_COUNT, cr3_target_count),
484 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
485 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
486 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
487 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
488 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
489 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
490 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
491 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
492 FIELD(TPR_THRESHOLD, tpr_threshold),
493 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
494 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
495 FIELD(VM_EXIT_REASON, vm_exit_reason),
496 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
497 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
498 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
499 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
500 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
501 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
502 FIELD(GUEST_ES_LIMIT, guest_es_limit),
503 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
504 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
505 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
506 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
507 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
508 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
509 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
510 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
511 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
512 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
513 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
514 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
515 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
516 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
517 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
518 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
519 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
520 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
521 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
522 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
523 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
524 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
525 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
526 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
527 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
528 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
529 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
530 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
531 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
532 FIELD(EXIT_QUALIFICATION, exit_qualification),
533 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
534 FIELD(GUEST_CR0, guest_cr0),
535 FIELD(GUEST_CR3, guest_cr3),
536 FIELD(GUEST_CR4, guest_cr4),
537 FIELD(GUEST_ES_BASE, guest_es_base),
538 FIELD(GUEST_CS_BASE, guest_cs_base),
539 FIELD(GUEST_SS_BASE, guest_ss_base),
540 FIELD(GUEST_DS_BASE, guest_ds_base),
541 FIELD(GUEST_FS_BASE, guest_fs_base),
542 FIELD(GUEST_GS_BASE, guest_gs_base),
543 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
544 FIELD(GUEST_TR_BASE, guest_tr_base),
545 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
546 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
547 FIELD(GUEST_DR7, guest_dr7),
548 FIELD(GUEST_RSP, guest_rsp),
549 FIELD(GUEST_RIP, guest_rip),
550 FIELD(GUEST_RFLAGS, guest_rflags),
551 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
552 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
553 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
554 FIELD(HOST_CR0, host_cr0),
555 FIELD(HOST_CR3, host_cr3),
556 FIELD(HOST_CR4, host_cr4),
557 FIELD(HOST_FS_BASE, host_fs_base),
558 FIELD(HOST_GS_BASE, host_gs_base),
559 FIELD(HOST_TR_BASE, host_tr_base),
560 FIELD(HOST_GDTR_BASE, host_gdtr_base),
561 FIELD(HOST_IDTR_BASE, host_idtr_base),
562 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
563 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
564 FIELD(HOST_RSP, host_rsp),
565 FIELD(HOST_RIP, host_rip),
566 };
567 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
568
569 static inline short vmcs_field_to_offset(unsigned long field)
570 {
571 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
572 return -1;
573 return vmcs_field_to_offset_table[field];
574 }
575
576 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
577 {
578 return to_vmx(vcpu)->nested.current_vmcs12;
579 }
580
581 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
582 {
583 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
584 if (is_error_page(page)) {
585 kvm_release_page_clean(page);
586 return NULL;
587 }
588 return page;
589 }
590
591 static void nested_release_page(struct page *page)
592 {
593 kvm_release_page_dirty(page);
594 }
595
596 static void nested_release_page_clean(struct page *page)
597 {
598 kvm_release_page_clean(page);
599 }
600
601 static u64 construct_eptp(unsigned long root_hpa);
602 static void kvm_cpu_vmxon(u64 addr);
603 static void kvm_cpu_vmxoff(void);
604 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
605 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
606
607 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
608 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
609 /*
610 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
611 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
612 */
613 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
614 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
615
616 static unsigned long *vmx_io_bitmap_a;
617 static unsigned long *vmx_io_bitmap_b;
618 static unsigned long *vmx_msr_bitmap_legacy;
619 static unsigned long *vmx_msr_bitmap_longmode;
620
621 static bool cpu_has_load_ia32_efer;
622
623 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
624 static DEFINE_SPINLOCK(vmx_vpid_lock);
625
626 static struct vmcs_config {
627 int size;
628 int order;
629 u32 revision_id;
630 u32 pin_based_exec_ctrl;
631 u32 cpu_based_exec_ctrl;
632 u32 cpu_based_2nd_exec_ctrl;
633 u32 vmexit_ctrl;
634 u32 vmentry_ctrl;
635 } vmcs_config;
636
637 static struct vmx_capability {
638 u32 ept;
639 u32 vpid;
640 } vmx_capability;
641
642 #define VMX_SEGMENT_FIELD(seg) \
643 [VCPU_SREG_##seg] = { \
644 .selector = GUEST_##seg##_SELECTOR, \
645 .base = GUEST_##seg##_BASE, \
646 .limit = GUEST_##seg##_LIMIT, \
647 .ar_bytes = GUEST_##seg##_AR_BYTES, \
648 }
649
650 static struct kvm_vmx_segment_field {
651 unsigned selector;
652 unsigned base;
653 unsigned limit;
654 unsigned ar_bytes;
655 } kvm_vmx_segment_fields[] = {
656 VMX_SEGMENT_FIELD(CS),
657 VMX_SEGMENT_FIELD(DS),
658 VMX_SEGMENT_FIELD(ES),
659 VMX_SEGMENT_FIELD(FS),
660 VMX_SEGMENT_FIELD(GS),
661 VMX_SEGMENT_FIELD(SS),
662 VMX_SEGMENT_FIELD(TR),
663 VMX_SEGMENT_FIELD(LDTR),
664 };
665
666 static u64 host_efer;
667
668 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
669
670 /*
671 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
672 * away by decrementing the array size.
673 */
674 static const u32 vmx_msr_index[] = {
675 #ifdef CONFIG_X86_64
676 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
677 #endif
678 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
679 };
680 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
681
682 static inline bool is_page_fault(u32 intr_info)
683 {
684 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
685 INTR_INFO_VALID_MASK)) ==
686 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
687 }
688
689 static inline bool is_no_device(u32 intr_info)
690 {
691 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
692 INTR_INFO_VALID_MASK)) ==
693 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
694 }
695
696 static inline bool is_invalid_opcode(u32 intr_info)
697 {
698 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
699 INTR_INFO_VALID_MASK)) ==
700 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
701 }
702
703 static inline bool is_external_interrupt(u32 intr_info)
704 {
705 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
706 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
707 }
708
709 static inline bool is_machine_check(u32 intr_info)
710 {
711 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
712 INTR_INFO_VALID_MASK)) ==
713 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
714 }
715
716 static inline bool cpu_has_vmx_msr_bitmap(void)
717 {
718 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
719 }
720
721 static inline bool cpu_has_vmx_tpr_shadow(void)
722 {
723 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
724 }
725
726 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
727 {
728 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
729 }
730
731 static inline bool cpu_has_secondary_exec_ctrls(void)
732 {
733 return vmcs_config.cpu_based_exec_ctrl &
734 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
735 }
736
737 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
738 {
739 return vmcs_config.cpu_based_2nd_exec_ctrl &
740 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
741 }
742
743 static inline bool cpu_has_vmx_flexpriority(void)
744 {
745 return cpu_has_vmx_tpr_shadow() &&
746 cpu_has_vmx_virtualize_apic_accesses();
747 }
748
749 static inline bool cpu_has_vmx_ept_execute_only(void)
750 {
751 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
752 }
753
754 static inline bool cpu_has_vmx_eptp_uncacheable(void)
755 {
756 return vmx_capability.ept & VMX_EPTP_UC_BIT;
757 }
758
759 static inline bool cpu_has_vmx_eptp_writeback(void)
760 {
761 return vmx_capability.ept & VMX_EPTP_WB_BIT;
762 }
763
764 static inline bool cpu_has_vmx_ept_2m_page(void)
765 {
766 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
767 }
768
769 static inline bool cpu_has_vmx_ept_1g_page(void)
770 {
771 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
772 }
773
774 static inline bool cpu_has_vmx_ept_4levels(void)
775 {
776 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
777 }
778
779 static inline bool cpu_has_vmx_invept_individual_addr(void)
780 {
781 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
782 }
783
784 static inline bool cpu_has_vmx_invept_context(void)
785 {
786 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
787 }
788
789 static inline bool cpu_has_vmx_invept_global(void)
790 {
791 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
792 }
793
794 static inline bool cpu_has_vmx_invvpid_single(void)
795 {
796 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
797 }
798
799 static inline bool cpu_has_vmx_invvpid_global(void)
800 {
801 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
802 }
803
804 static inline bool cpu_has_vmx_ept(void)
805 {
806 return vmcs_config.cpu_based_2nd_exec_ctrl &
807 SECONDARY_EXEC_ENABLE_EPT;
808 }
809
810 static inline bool cpu_has_vmx_unrestricted_guest(void)
811 {
812 return vmcs_config.cpu_based_2nd_exec_ctrl &
813 SECONDARY_EXEC_UNRESTRICTED_GUEST;
814 }
815
816 static inline bool cpu_has_vmx_ple(void)
817 {
818 return vmcs_config.cpu_based_2nd_exec_ctrl &
819 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
820 }
821
822 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
823 {
824 return flexpriority_enabled && irqchip_in_kernel(kvm);
825 }
826
827 static inline bool cpu_has_vmx_vpid(void)
828 {
829 return vmcs_config.cpu_based_2nd_exec_ctrl &
830 SECONDARY_EXEC_ENABLE_VPID;
831 }
832
833 static inline bool cpu_has_vmx_rdtscp(void)
834 {
835 return vmcs_config.cpu_based_2nd_exec_ctrl &
836 SECONDARY_EXEC_RDTSCP;
837 }
838
839 static inline bool cpu_has_virtual_nmis(void)
840 {
841 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
842 }
843
844 static inline bool cpu_has_vmx_wbinvd_exit(void)
845 {
846 return vmcs_config.cpu_based_2nd_exec_ctrl &
847 SECONDARY_EXEC_WBINVD_EXITING;
848 }
849
850 static inline bool report_flexpriority(void)
851 {
852 return flexpriority_enabled;
853 }
854
855 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
856 {
857 return vmcs12->cpu_based_vm_exec_control & bit;
858 }
859
860 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
861 {
862 return (vmcs12->cpu_based_vm_exec_control &
863 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
864 (vmcs12->secondary_vm_exec_control & bit);
865 }
866
867 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
868 struct kvm_vcpu *vcpu)
869 {
870 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
871 }
872
873 static inline bool is_exception(u32 intr_info)
874 {
875 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
876 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
877 }
878
879 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
880 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
881 struct vmcs12 *vmcs12,
882 u32 reason, unsigned long qualification);
883
884 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
885 {
886 int i;
887
888 for (i = 0; i < vmx->nmsrs; ++i)
889 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
890 return i;
891 return -1;
892 }
893
894 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
895 {
896 struct {
897 u64 vpid : 16;
898 u64 rsvd : 48;
899 u64 gva;
900 } operand = { vpid, 0, gva };
901
902 asm volatile (__ex(ASM_VMX_INVVPID)
903 /* CF==1 or ZF==1 --> rc = -1 */
904 "; ja 1f ; ud2 ; 1:"
905 : : "a"(&operand), "c"(ext) : "cc", "memory");
906 }
907
908 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
909 {
910 struct {
911 u64 eptp, gpa;
912 } operand = {eptp, gpa};
913
914 asm volatile (__ex(ASM_VMX_INVEPT)
915 /* CF==1 or ZF==1 --> rc = -1 */
916 "; ja 1f ; ud2 ; 1:\n"
917 : : "a" (&operand), "c" (ext) : "cc", "memory");
918 }
919
920 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
921 {
922 int i;
923
924 i = __find_msr_index(vmx, msr);
925 if (i >= 0)
926 return &vmx->guest_msrs[i];
927 return NULL;
928 }
929
930 static void vmcs_clear(struct vmcs *vmcs)
931 {
932 u64 phys_addr = __pa(vmcs);
933 u8 error;
934
935 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
936 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
937 : "cc", "memory");
938 if (error)
939 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
940 vmcs, phys_addr);
941 }
942
943 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
944 {
945 vmcs_clear(loaded_vmcs->vmcs);
946 loaded_vmcs->cpu = -1;
947 loaded_vmcs->launched = 0;
948 }
949
950 static void vmcs_load(struct vmcs *vmcs)
951 {
952 u64 phys_addr = __pa(vmcs);
953 u8 error;
954
955 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
956 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
957 : "cc", "memory");
958 if (error)
959 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
960 vmcs, phys_addr);
961 }
962
963 static void __loaded_vmcs_clear(void *arg)
964 {
965 struct loaded_vmcs *loaded_vmcs = arg;
966 int cpu = raw_smp_processor_id();
967
968 if (loaded_vmcs->cpu != cpu)
969 return; /* vcpu migration can race with cpu offline */
970 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
971 per_cpu(current_vmcs, cpu) = NULL;
972 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
973 loaded_vmcs_init(loaded_vmcs);
974 }
975
976 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
977 {
978 if (loaded_vmcs->cpu != -1)
979 smp_call_function_single(
980 loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
981 }
982
983 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
984 {
985 if (vmx->vpid == 0)
986 return;
987
988 if (cpu_has_vmx_invvpid_single())
989 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
990 }
991
992 static inline void vpid_sync_vcpu_global(void)
993 {
994 if (cpu_has_vmx_invvpid_global())
995 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
996 }
997
998 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
999 {
1000 if (cpu_has_vmx_invvpid_single())
1001 vpid_sync_vcpu_single(vmx);
1002 else
1003 vpid_sync_vcpu_global();
1004 }
1005
1006 static inline void ept_sync_global(void)
1007 {
1008 if (cpu_has_vmx_invept_global())
1009 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1010 }
1011
1012 static inline void ept_sync_context(u64 eptp)
1013 {
1014 if (enable_ept) {
1015 if (cpu_has_vmx_invept_context())
1016 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1017 else
1018 ept_sync_global();
1019 }
1020 }
1021
1022 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1023 {
1024 if (enable_ept) {
1025 if (cpu_has_vmx_invept_individual_addr())
1026 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1027 eptp, gpa);
1028 else
1029 ept_sync_context(eptp);
1030 }
1031 }
1032
1033 static __always_inline unsigned long vmcs_readl(unsigned long field)
1034 {
1035 unsigned long value;
1036
1037 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1038 : "=a"(value) : "d"(field) : "cc");
1039 return value;
1040 }
1041
1042 static __always_inline u16 vmcs_read16(unsigned long field)
1043 {
1044 return vmcs_readl(field);
1045 }
1046
1047 static __always_inline u32 vmcs_read32(unsigned long field)
1048 {
1049 return vmcs_readl(field);
1050 }
1051
1052 static __always_inline u64 vmcs_read64(unsigned long field)
1053 {
1054 #ifdef CONFIG_X86_64
1055 return vmcs_readl(field);
1056 #else
1057 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1058 #endif
1059 }
1060
1061 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1062 {
1063 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1064 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1065 dump_stack();
1066 }
1067
1068 static void vmcs_writel(unsigned long field, unsigned long value)
1069 {
1070 u8 error;
1071
1072 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1073 : "=q"(error) : "a"(value), "d"(field) : "cc");
1074 if (unlikely(error))
1075 vmwrite_error(field, value);
1076 }
1077
1078 static void vmcs_write16(unsigned long field, u16 value)
1079 {
1080 vmcs_writel(field, value);
1081 }
1082
1083 static void vmcs_write32(unsigned long field, u32 value)
1084 {
1085 vmcs_writel(field, value);
1086 }
1087
1088 static void vmcs_write64(unsigned long field, u64 value)
1089 {
1090 vmcs_writel(field, value);
1091 #ifndef CONFIG_X86_64
1092 asm volatile ("");
1093 vmcs_writel(field+1, value >> 32);
1094 #endif
1095 }
1096
1097 static void vmcs_clear_bits(unsigned long field, u32 mask)
1098 {
1099 vmcs_writel(field, vmcs_readl(field) & ~mask);
1100 }
1101
1102 static void vmcs_set_bits(unsigned long field, u32 mask)
1103 {
1104 vmcs_writel(field, vmcs_readl(field) | mask);
1105 }
1106
1107 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1108 {
1109 vmx->segment_cache.bitmask = 0;
1110 }
1111
1112 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1113 unsigned field)
1114 {
1115 bool ret;
1116 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1117
1118 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1119 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1120 vmx->segment_cache.bitmask = 0;
1121 }
1122 ret = vmx->segment_cache.bitmask & mask;
1123 vmx->segment_cache.bitmask |= mask;
1124 return ret;
1125 }
1126
1127 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1128 {
1129 u16 *p = &vmx->segment_cache.seg[seg].selector;
1130
1131 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1132 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1133 return *p;
1134 }
1135
1136 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1137 {
1138 ulong *p = &vmx->segment_cache.seg[seg].base;
1139
1140 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1141 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1142 return *p;
1143 }
1144
1145 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1146 {
1147 u32 *p = &vmx->segment_cache.seg[seg].limit;
1148
1149 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1150 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1151 return *p;
1152 }
1153
1154 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1155 {
1156 u32 *p = &vmx->segment_cache.seg[seg].ar;
1157
1158 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1159 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1160 return *p;
1161 }
1162
1163 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1164 {
1165 u32 eb;
1166
1167 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1168 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1169 if ((vcpu->guest_debug &
1170 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1171 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1172 eb |= 1u << BP_VECTOR;
1173 if (to_vmx(vcpu)->rmode.vm86_active)
1174 eb = ~0;
1175 if (enable_ept)
1176 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1177 if (vcpu->fpu_active)
1178 eb &= ~(1u << NM_VECTOR);
1179
1180 /* When we are running a nested L2 guest and L1 specified for it a
1181 * certain exception bitmap, we must trap the same exceptions and pass
1182 * them to L1. When running L2, we will only handle the exceptions
1183 * specified above if L1 did not want them.
1184 */
1185 if (is_guest_mode(vcpu))
1186 eb |= get_vmcs12(vcpu)->exception_bitmap;
1187
1188 vmcs_write32(EXCEPTION_BITMAP, eb);
1189 }
1190
1191 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1192 {
1193 unsigned i;
1194 struct msr_autoload *m = &vmx->msr_autoload;
1195
1196 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
1197 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
1198 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
1199 return;
1200 }
1201
1202 for (i = 0; i < m->nr; ++i)
1203 if (m->guest[i].index == msr)
1204 break;
1205
1206 if (i == m->nr)
1207 return;
1208 --m->nr;
1209 m->guest[i] = m->guest[m->nr];
1210 m->host[i] = m->host[m->nr];
1211 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1212 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1213 }
1214
1215 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1216 u64 guest_val, u64 host_val)
1217 {
1218 unsigned i;
1219 struct msr_autoload *m = &vmx->msr_autoload;
1220
1221 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
1222 vmcs_write64(GUEST_IA32_EFER, guest_val);
1223 vmcs_write64(HOST_IA32_EFER, host_val);
1224 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
1225 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
1226 return;
1227 }
1228
1229 for (i = 0; i < m->nr; ++i)
1230 if (m->guest[i].index == msr)
1231 break;
1232
1233 if (i == m->nr) {
1234 ++m->nr;
1235 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1236 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1237 }
1238
1239 m->guest[i].index = msr;
1240 m->guest[i].value = guest_val;
1241 m->host[i].index = msr;
1242 m->host[i].value = host_val;
1243 }
1244
1245 static void reload_tss(void)
1246 {
1247 /*
1248 * VT restores TR but not its size. Useless.
1249 */
1250 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1251 struct desc_struct *descs;
1252
1253 descs = (void *)gdt->address;
1254 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1255 load_TR_desc();
1256 }
1257
1258 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1259 {
1260 u64 guest_efer;
1261 u64 ignore_bits;
1262
1263 guest_efer = vmx->vcpu.arch.efer;
1264
1265 /*
1266 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1267 * outside long mode
1268 */
1269 ignore_bits = EFER_NX | EFER_SCE;
1270 #ifdef CONFIG_X86_64
1271 ignore_bits |= EFER_LMA | EFER_LME;
1272 /* SCE is meaningful only in long mode on Intel */
1273 if (guest_efer & EFER_LMA)
1274 ignore_bits &= ~(u64)EFER_SCE;
1275 #endif
1276 guest_efer &= ~ignore_bits;
1277 guest_efer |= host_efer & ignore_bits;
1278 vmx->guest_msrs[efer_offset].data = guest_efer;
1279 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1280
1281 clear_atomic_switch_msr(vmx, MSR_EFER);
1282 /* On ept, can't emulate nx, and must switch nx atomically */
1283 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1284 guest_efer = vmx->vcpu.arch.efer;
1285 if (!(guest_efer & EFER_LMA))
1286 guest_efer &= ~EFER_LME;
1287 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1288 return false;
1289 }
1290
1291 return true;
1292 }
1293
1294 static unsigned long segment_base(u16 selector)
1295 {
1296 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1297 struct desc_struct *d;
1298 unsigned long table_base;
1299 unsigned long v;
1300
1301 if (!(selector & ~3))
1302 return 0;
1303
1304 table_base = gdt->address;
1305
1306 if (selector & 4) { /* from ldt */
1307 u16 ldt_selector = kvm_read_ldt();
1308
1309 if (!(ldt_selector & ~3))
1310 return 0;
1311
1312 table_base = segment_base(ldt_selector);
1313 }
1314 d = (struct desc_struct *)(table_base + (selector & ~7));
1315 v = get_desc_base(d);
1316 #ifdef CONFIG_X86_64
1317 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1318 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1319 #endif
1320 return v;
1321 }
1322
1323 static inline unsigned long kvm_read_tr_base(void)
1324 {
1325 u16 tr;
1326 asm("str %0" : "=g"(tr));
1327 return segment_base(tr);
1328 }
1329
1330 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1331 {
1332 struct vcpu_vmx *vmx = to_vmx(vcpu);
1333 int i;
1334
1335 if (vmx->host_state.loaded)
1336 return;
1337
1338 vmx->host_state.loaded = 1;
1339 /*
1340 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1341 * allow segment selectors with cpl > 0 or ti == 1.
1342 */
1343 vmx->host_state.ldt_sel = kvm_read_ldt();
1344 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1345 savesegment(fs, vmx->host_state.fs_sel);
1346 if (!(vmx->host_state.fs_sel & 7)) {
1347 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1348 vmx->host_state.fs_reload_needed = 0;
1349 } else {
1350 vmcs_write16(HOST_FS_SELECTOR, 0);
1351 vmx->host_state.fs_reload_needed = 1;
1352 }
1353 savesegment(gs, vmx->host_state.gs_sel);
1354 if (!(vmx->host_state.gs_sel & 7))
1355 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1356 else {
1357 vmcs_write16(HOST_GS_SELECTOR, 0);
1358 vmx->host_state.gs_ldt_reload_needed = 1;
1359 }
1360
1361 #ifdef CONFIG_X86_64
1362 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1363 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1364 #else
1365 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1366 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1367 #endif
1368
1369 #ifdef CONFIG_X86_64
1370 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1371 if (is_long_mode(&vmx->vcpu))
1372 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1373 #endif
1374 for (i = 0; i < vmx->save_nmsrs; ++i)
1375 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1376 vmx->guest_msrs[i].data,
1377 vmx->guest_msrs[i].mask);
1378 }
1379
1380 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1381 {
1382 if (!vmx->host_state.loaded)
1383 return;
1384
1385 ++vmx->vcpu.stat.host_state_reload;
1386 vmx->host_state.loaded = 0;
1387 #ifdef CONFIG_X86_64
1388 if (is_long_mode(&vmx->vcpu))
1389 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1390 #endif
1391 if (vmx->host_state.gs_ldt_reload_needed) {
1392 kvm_load_ldt(vmx->host_state.ldt_sel);
1393 #ifdef CONFIG_X86_64
1394 load_gs_index(vmx->host_state.gs_sel);
1395 #else
1396 loadsegment(gs, vmx->host_state.gs_sel);
1397 #endif
1398 }
1399 if (vmx->host_state.fs_reload_needed)
1400 loadsegment(fs, vmx->host_state.fs_sel);
1401 reload_tss();
1402 #ifdef CONFIG_X86_64
1403 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1404 #endif
1405 if (current_thread_info()->status & TS_USEDFPU)
1406 clts();
1407 load_gdt(&__get_cpu_var(host_gdt));
1408 }
1409
1410 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1411 {
1412 preempt_disable();
1413 __vmx_load_host_state(vmx);
1414 preempt_enable();
1415 }
1416
1417 /*
1418 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1419 * vcpu mutex is already taken.
1420 */
1421 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1422 {
1423 struct vcpu_vmx *vmx = to_vmx(vcpu);
1424 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1425
1426 if (!vmm_exclusive)
1427 kvm_cpu_vmxon(phys_addr);
1428 else if (vmx->loaded_vmcs->cpu != cpu)
1429 loaded_vmcs_clear(vmx->loaded_vmcs);
1430
1431 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1432 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1433 vmcs_load(vmx->loaded_vmcs->vmcs);
1434 }
1435
1436 if (vmx->loaded_vmcs->cpu != cpu) {
1437 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1438 unsigned long sysenter_esp;
1439
1440 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1441 local_irq_disable();
1442 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1443 &per_cpu(loaded_vmcss_on_cpu, cpu));
1444 local_irq_enable();
1445
1446 /*
1447 * Linux uses per-cpu TSS and GDT, so set these when switching
1448 * processors.
1449 */
1450 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1451 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
1452
1453 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1454 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1455 vmx->loaded_vmcs->cpu = cpu;
1456 }
1457 }
1458
1459 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1460 {
1461 __vmx_load_host_state(to_vmx(vcpu));
1462 if (!vmm_exclusive) {
1463 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1464 vcpu->cpu = -1;
1465 kvm_cpu_vmxoff();
1466 }
1467 }
1468
1469 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1470 {
1471 ulong cr0;
1472
1473 if (vcpu->fpu_active)
1474 return;
1475 vcpu->fpu_active = 1;
1476 cr0 = vmcs_readl(GUEST_CR0);
1477 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1478 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1479 vmcs_writel(GUEST_CR0, cr0);
1480 update_exception_bitmap(vcpu);
1481 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1482 if (is_guest_mode(vcpu))
1483 vcpu->arch.cr0_guest_owned_bits &=
1484 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1485 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1486 }
1487
1488 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1489
1490 /*
1491 * Return the cr0 value that a nested guest would read. This is a combination
1492 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1493 * its hypervisor (cr0_read_shadow).
1494 */
1495 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1496 {
1497 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1498 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1499 }
1500 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1501 {
1502 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1503 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1504 }
1505
1506 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1507 {
1508 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1509 * set this *before* calling this function.
1510 */
1511 vmx_decache_cr0_guest_bits(vcpu);
1512 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1513 update_exception_bitmap(vcpu);
1514 vcpu->arch.cr0_guest_owned_bits = 0;
1515 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1516 if (is_guest_mode(vcpu)) {
1517 /*
1518 * L1's specified read shadow might not contain the TS bit,
1519 * so now that we turned on shadowing of this bit, we need to
1520 * set this bit of the shadow. Like in nested_vmx_run we need
1521 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1522 * up-to-date here because we just decached cr0.TS (and we'll
1523 * only update vmcs12->guest_cr0 on nested exit).
1524 */
1525 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1526 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1527 (vcpu->arch.cr0 & X86_CR0_TS);
1528 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1529 } else
1530 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1531 }
1532
1533 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1534 {
1535 unsigned long rflags, save_rflags;
1536
1537 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1538 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1539 rflags = vmcs_readl(GUEST_RFLAGS);
1540 if (to_vmx(vcpu)->rmode.vm86_active) {
1541 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1542 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1543 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1544 }
1545 to_vmx(vcpu)->rflags = rflags;
1546 }
1547 return to_vmx(vcpu)->rflags;
1548 }
1549
1550 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1551 {
1552 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1553 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1554 to_vmx(vcpu)->rflags = rflags;
1555 if (to_vmx(vcpu)->rmode.vm86_active) {
1556 to_vmx(vcpu)->rmode.save_rflags = rflags;
1557 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1558 }
1559 vmcs_writel(GUEST_RFLAGS, rflags);
1560 }
1561
1562 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1563 {
1564 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1565 int ret = 0;
1566
1567 if (interruptibility & GUEST_INTR_STATE_STI)
1568 ret |= KVM_X86_SHADOW_INT_STI;
1569 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1570 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1571
1572 return ret & mask;
1573 }
1574
1575 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1576 {
1577 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1578 u32 interruptibility = interruptibility_old;
1579
1580 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1581
1582 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1583 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1584 else if (mask & KVM_X86_SHADOW_INT_STI)
1585 interruptibility |= GUEST_INTR_STATE_STI;
1586
1587 if ((interruptibility != interruptibility_old))
1588 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1589 }
1590
1591 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1592 {
1593 unsigned long rip;
1594
1595 rip = kvm_rip_read(vcpu);
1596 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1597 kvm_rip_write(vcpu, rip);
1598
1599 /* skipping an emulated instruction also counts */
1600 vmx_set_interrupt_shadow(vcpu, 0);
1601 }
1602
1603 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1604 {
1605 /* Ensure that we clear the HLT state in the VMCS. We don't need to
1606 * explicitly skip the instruction because if the HLT state is set, then
1607 * the instruction is already executing and RIP has already been
1608 * advanced. */
1609 if (!yield_on_hlt &&
1610 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1611 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1612 }
1613
1614 /*
1615 * KVM wants to inject page-faults which it got to the guest. This function
1616 * checks whether in a nested guest, we need to inject them to L1 or L2.
1617 * This function assumes it is called with the exit reason in vmcs02 being
1618 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1619 * is running).
1620 */
1621 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1622 {
1623 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1624
1625 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1626 if (!(vmcs12->exception_bitmap & PF_VECTOR))
1627 return 0;
1628
1629 nested_vmx_vmexit(vcpu);
1630 return 1;
1631 }
1632
1633 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1634 bool has_error_code, u32 error_code,
1635 bool reinject)
1636 {
1637 struct vcpu_vmx *vmx = to_vmx(vcpu);
1638 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1639
1640 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1641 nested_pf_handled(vcpu))
1642 return;
1643
1644 if (has_error_code) {
1645 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1646 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1647 }
1648
1649 if (vmx->rmode.vm86_active) {
1650 int inc_eip = 0;
1651 if (kvm_exception_is_soft(nr))
1652 inc_eip = vcpu->arch.event_exit_inst_len;
1653 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1654 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1655 return;
1656 }
1657
1658 if (kvm_exception_is_soft(nr)) {
1659 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1660 vmx->vcpu.arch.event_exit_inst_len);
1661 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1662 } else
1663 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1664
1665 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1666 vmx_clear_hlt(vcpu);
1667 }
1668
1669 static bool vmx_rdtscp_supported(void)
1670 {
1671 return cpu_has_vmx_rdtscp();
1672 }
1673
1674 /*
1675 * Swap MSR entry in host/guest MSR entry array.
1676 */
1677 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1678 {
1679 struct shared_msr_entry tmp;
1680
1681 tmp = vmx->guest_msrs[to];
1682 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1683 vmx->guest_msrs[from] = tmp;
1684 }
1685
1686 /*
1687 * Set up the vmcs to automatically save and restore system
1688 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1689 * mode, as fiddling with msrs is very expensive.
1690 */
1691 static void setup_msrs(struct vcpu_vmx *vmx)
1692 {
1693 int save_nmsrs, index;
1694 unsigned long *msr_bitmap;
1695
1696 vmx_load_host_state(vmx);
1697 save_nmsrs = 0;
1698 #ifdef CONFIG_X86_64
1699 if (is_long_mode(&vmx->vcpu)) {
1700 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1701 if (index >= 0)
1702 move_msr_up(vmx, index, save_nmsrs++);
1703 index = __find_msr_index(vmx, MSR_LSTAR);
1704 if (index >= 0)
1705 move_msr_up(vmx, index, save_nmsrs++);
1706 index = __find_msr_index(vmx, MSR_CSTAR);
1707 if (index >= 0)
1708 move_msr_up(vmx, index, save_nmsrs++);
1709 index = __find_msr_index(vmx, MSR_TSC_AUX);
1710 if (index >= 0 && vmx->rdtscp_enabled)
1711 move_msr_up(vmx, index, save_nmsrs++);
1712 /*
1713 * MSR_STAR is only needed on long mode guests, and only
1714 * if efer.sce is enabled.
1715 */
1716 index = __find_msr_index(vmx, MSR_STAR);
1717 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1718 move_msr_up(vmx, index, save_nmsrs++);
1719 }
1720 #endif
1721 index = __find_msr_index(vmx, MSR_EFER);
1722 if (index >= 0 && update_transition_efer(vmx, index))
1723 move_msr_up(vmx, index, save_nmsrs++);
1724
1725 vmx->save_nmsrs = save_nmsrs;
1726
1727 if (cpu_has_vmx_msr_bitmap()) {
1728 if (is_long_mode(&vmx->vcpu))
1729 msr_bitmap = vmx_msr_bitmap_longmode;
1730 else
1731 msr_bitmap = vmx_msr_bitmap_legacy;
1732
1733 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1734 }
1735 }
1736
1737 /*
1738 * reads and returns guest's timestamp counter "register"
1739 * guest_tsc = host_tsc + tsc_offset -- 21.3
1740 */
1741 static u64 guest_read_tsc(void)
1742 {
1743 u64 host_tsc, tsc_offset;
1744
1745 rdtscll(host_tsc);
1746 tsc_offset = vmcs_read64(TSC_OFFSET);
1747 return host_tsc + tsc_offset;
1748 }
1749
1750 /*
1751 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1752 * counter, even if a nested guest (L2) is currently running.
1753 */
1754 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu)
1755 {
1756 u64 host_tsc, tsc_offset;
1757
1758 rdtscll(host_tsc);
1759 tsc_offset = is_guest_mode(vcpu) ?
1760 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1761 vmcs_read64(TSC_OFFSET);
1762 return host_tsc + tsc_offset;
1763 }
1764
1765 /*
1766 * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1767 * ioctl. In this case the call-back should update internal vmx state to make
1768 * the changes effective.
1769 */
1770 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1771 {
1772 /* Nothing to do here */
1773 }
1774
1775 /*
1776 * writes 'offset' into guest's timestamp counter offset register
1777 */
1778 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1779 {
1780 if (is_guest_mode(vcpu)) {
1781 /*
1782 * We're here if L1 chose not to trap WRMSR to TSC. According
1783 * to the spec, this should set L1's TSC; The offset that L1
1784 * set for L2 remains unchanged, and still needs to be added
1785 * to the newly set TSC to get L2's TSC.
1786 */
1787 struct vmcs12 *vmcs12;
1788 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1789 /* recalculate vmcs02.TSC_OFFSET: */
1790 vmcs12 = get_vmcs12(vcpu);
1791 vmcs_write64(TSC_OFFSET, offset +
1792 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1793 vmcs12->tsc_offset : 0));
1794 } else {
1795 vmcs_write64(TSC_OFFSET, offset);
1796 }
1797 }
1798
1799 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1800 {
1801 u64 offset = vmcs_read64(TSC_OFFSET);
1802 vmcs_write64(TSC_OFFSET, offset + adjustment);
1803 if (is_guest_mode(vcpu)) {
1804 /* Even when running L2, the adjustment needs to apply to L1 */
1805 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1806 }
1807 }
1808
1809 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1810 {
1811 return target_tsc - native_read_tsc();
1812 }
1813
1814 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1815 {
1816 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1817 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1818 }
1819
1820 /*
1821 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1822 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1823 * all guests if the "nested" module option is off, and can also be disabled
1824 * for a single guest by disabling its VMX cpuid bit.
1825 */
1826 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1827 {
1828 return nested && guest_cpuid_has_vmx(vcpu);
1829 }
1830
1831 /*
1832 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1833 * returned for the various VMX controls MSRs when nested VMX is enabled.
1834 * The same values should also be used to verify that vmcs12 control fields are
1835 * valid during nested entry from L1 to L2.
1836 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1837 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1838 * bit in the high half is on if the corresponding bit in the control field
1839 * may be on. See also vmx_control_verify().
1840 * TODO: allow these variables to be modified (downgraded) by module options
1841 * or other means.
1842 */
1843 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1844 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1845 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1846 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1847 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1848 static __init void nested_vmx_setup_ctls_msrs(void)
1849 {
1850 /*
1851 * Note that as a general rule, the high half of the MSRs (bits in
1852 * the control fields which may be 1) should be initialized by the
1853 * intersection of the underlying hardware's MSR (i.e., features which
1854 * can be supported) and the list of features we want to expose -
1855 * because they are known to be properly supported in our code.
1856 * Also, usually, the low half of the MSRs (bits which must be 1) can
1857 * be set to 0, meaning that L1 may turn off any of these bits. The
1858 * reason is that if one of these bits is necessary, it will appear
1859 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1860 * fields of vmcs01 and vmcs02, will turn these bits off - and
1861 * nested_vmx_exit_handled() will not pass related exits to L1.
1862 * These rules have exceptions below.
1863 */
1864
1865 /* pin-based controls */
1866 /*
1867 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1868 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1869 */
1870 nested_vmx_pinbased_ctls_low = 0x16 ;
1871 nested_vmx_pinbased_ctls_high = 0x16 |
1872 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1873 PIN_BASED_VIRTUAL_NMIS;
1874
1875 /* exit controls */
1876 nested_vmx_exit_ctls_low = 0;
1877 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
1878 #ifdef CONFIG_X86_64
1879 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1880 #else
1881 nested_vmx_exit_ctls_high = 0;
1882 #endif
1883
1884 /* entry controls */
1885 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1886 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1887 nested_vmx_entry_ctls_low = 0;
1888 nested_vmx_entry_ctls_high &=
1889 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1890
1891 /* cpu-based controls */
1892 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1893 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1894 nested_vmx_procbased_ctls_low = 0;
1895 nested_vmx_procbased_ctls_high &=
1896 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1897 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1898 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1899 CPU_BASED_CR3_STORE_EXITING |
1900 #ifdef CONFIG_X86_64
1901 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1902 #endif
1903 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1904 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1905 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1906 /*
1907 * We can allow some features even when not supported by the
1908 * hardware. For example, L1 can specify an MSR bitmap - and we
1909 * can use it to avoid exits to L1 - even when L0 runs L2
1910 * without MSR bitmaps.
1911 */
1912 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1913
1914 /* secondary cpu-based controls */
1915 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
1916 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
1917 nested_vmx_secondary_ctls_low = 0;
1918 nested_vmx_secondary_ctls_high &=
1919 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1920 }
1921
1922 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
1923 {
1924 /*
1925 * Bits 0 in high must be 0, and bits 1 in low must be 1.
1926 */
1927 return ((control & high) | low) == control;
1928 }
1929
1930 static inline u64 vmx_control_msr(u32 low, u32 high)
1931 {
1932 return low | ((u64)high << 32);
1933 }
1934
1935 /*
1936 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1937 * also let it use VMX-specific MSRs.
1938 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
1939 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
1940 * like all other MSRs).
1941 */
1942 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1943 {
1944 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
1945 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
1946 /*
1947 * According to the spec, processors which do not support VMX
1948 * should throw a #GP(0) when VMX capability MSRs are read.
1949 */
1950 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
1951 return 1;
1952 }
1953
1954 switch (msr_index) {
1955 case MSR_IA32_FEATURE_CONTROL:
1956 *pdata = 0;
1957 break;
1958 case MSR_IA32_VMX_BASIC:
1959 /*
1960 * This MSR reports some information about VMX support. We
1961 * should return information about the VMX we emulate for the
1962 * guest, and the VMCS structure we give it - not about the
1963 * VMX support of the underlying hardware.
1964 */
1965 *pdata = VMCS12_REVISION |
1966 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
1967 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
1968 break;
1969 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
1970 case MSR_IA32_VMX_PINBASED_CTLS:
1971 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
1972 nested_vmx_pinbased_ctls_high);
1973 break;
1974 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
1975 case MSR_IA32_VMX_PROCBASED_CTLS:
1976 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
1977 nested_vmx_procbased_ctls_high);
1978 break;
1979 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
1980 case MSR_IA32_VMX_EXIT_CTLS:
1981 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
1982 nested_vmx_exit_ctls_high);
1983 break;
1984 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
1985 case MSR_IA32_VMX_ENTRY_CTLS:
1986 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
1987 nested_vmx_entry_ctls_high);
1988 break;
1989 case MSR_IA32_VMX_MISC:
1990 *pdata = 0;
1991 break;
1992 /*
1993 * These MSRs specify bits which the guest must keep fixed (on or off)
1994 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
1995 * We picked the standard core2 setting.
1996 */
1997 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
1998 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
1999 case MSR_IA32_VMX_CR0_FIXED0:
2000 *pdata = VMXON_CR0_ALWAYSON;
2001 break;
2002 case MSR_IA32_VMX_CR0_FIXED1:
2003 *pdata = -1ULL;
2004 break;
2005 case MSR_IA32_VMX_CR4_FIXED0:
2006 *pdata = VMXON_CR4_ALWAYSON;
2007 break;
2008 case MSR_IA32_VMX_CR4_FIXED1:
2009 *pdata = -1ULL;
2010 break;
2011 case MSR_IA32_VMX_VMCS_ENUM:
2012 *pdata = 0x1f;
2013 break;
2014 case MSR_IA32_VMX_PROCBASED_CTLS2:
2015 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2016 nested_vmx_secondary_ctls_high);
2017 break;
2018 case MSR_IA32_VMX_EPT_VPID_CAP:
2019 /* Currently, no nested ept or nested vpid */
2020 *pdata = 0;
2021 break;
2022 default:
2023 return 0;
2024 }
2025
2026 return 1;
2027 }
2028
2029 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2030 {
2031 if (!nested_vmx_allowed(vcpu))
2032 return 0;
2033
2034 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2035 /* TODO: the right thing. */
2036 return 1;
2037 /*
2038 * No need to treat VMX capability MSRs specially: If we don't handle
2039 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2040 */
2041 return 0;
2042 }
2043
2044 /*
2045 * Reads an msr value (of 'msr_index') into 'pdata'.
2046 * Returns 0 on success, non-0 otherwise.
2047 * Assumes vcpu_load() was already called.
2048 */
2049 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2050 {
2051 u64 data;
2052 struct shared_msr_entry *msr;
2053
2054 if (!pdata) {
2055 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2056 return -EINVAL;
2057 }
2058
2059 switch (msr_index) {
2060 #ifdef CONFIG_X86_64
2061 case MSR_FS_BASE:
2062 data = vmcs_readl(GUEST_FS_BASE);
2063 break;
2064 case MSR_GS_BASE:
2065 data = vmcs_readl(GUEST_GS_BASE);
2066 break;
2067 case MSR_KERNEL_GS_BASE:
2068 vmx_load_host_state(to_vmx(vcpu));
2069 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2070 break;
2071 #endif
2072 case MSR_EFER:
2073 return kvm_get_msr_common(vcpu, msr_index, pdata);
2074 case MSR_IA32_TSC:
2075 data = guest_read_tsc();
2076 break;
2077 case MSR_IA32_SYSENTER_CS:
2078 data = vmcs_read32(GUEST_SYSENTER_CS);
2079 break;
2080 case MSR_IA32_SYSENTER_EIP:
2081 data = vmcs_readl(GUEST_SYSENTER_EIP);
2082 break;
2083 case MSR_IA32_SYSENTER_ESP:
2084 data = vmcs_readl(GUEST_SYSENTER_ESP);
2085 break;
2086 case MSR_TSC_AUX:
2087 if (!to_vmx(vcpu)->rdtscp_enabled)
2088 return 1;
2089 /* Otherwise falls through */
2090 default:
2091 vmx_load_host_state(to_vmx(vcpu));
2092 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2093 return 0;
2094 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2095 if (msr) {
2096 vmx_load_host_state(to_vmx(vcpu));
2097 data = msr->data;
2098 break;
2099 }
2100 return kvm_get_msr_common(vcpu, msr_index, pdata);
2101 }
2102
2103 *pdata = data;
2104 return 0;
2105 }
2106
2107 /*
2108 * Writes msr value into into the appropriate "register".
2109 * Returns 0 on success, non-0 otherwise.
2110 * Assumes vcpu_load() was already called.
2111 */
2112 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2113 {
2114 struct vcpu_vmx *vmx = to_vmx(vcpu);
2115 struct shared_msr_entry *msr;
2116 int ret = 0;
2117
2118 switch (msr_index) {
2119 case MSR_EFER:
2120 vmx_load_host_state(vmx);
2121 ret = kvm_set_msr_common(vcpu, msr_index, data);
2122 break;
2123 #ifdef CONFIG_X86_64
2124 case MSR_FS_BASE:
2125 vmx_segment_cache_clear(vmx);
2126 vmcs_writel(GUEST_FS_BASE, data);
2127 break;
2128 case MSR_GS_BASE:
2129 vmx_segment_cache_clear(vmx);
2130 vmcs_writel(GUEST_GS_BASE, data);
2131 break;
2132 case MSR_KERNEL_GS_BASE:
2133 vmx_load_host_state(vmx);
2134 vmx->msr_guest_kernel_gs_base = data;
2135 break;
2136 #endif
2137 case MSR_IA32_SYSENTER_CS:
2138 vmcs_write32(GUEST_SYSENTER_CS, data);
2139 break;
2140 case MSR_IA32_SYSENTER_EIP:
2141 vmcs_writel(GUEST_SYSENTER_EIP, data);
2142 break;
2143 case MSR_IA32_SYSENTER_ESP:
2144 vmcs_writel(GUEST_SYSENTER_ESP, data);
2145 break;
2146 case MSR_IA32_TSC:
2147 kvm_write_tsc(vcpu, data);
2148 break;
2149 case MSR_IA32_CR_PAT:
2150 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2151 vmcs_write64(GUEST_IA32_PAT, data);
2152 vcpu->arch.pat = data;
2153 break;
2154 }
2155 ret = kvm_set_msr_common(vcpu, msr_index, data);
2156 break;
2157 case MSR_TSC_AUX:
2158 if (!vmx->rdtscp_enabled)
2159 return 1;
2160 /* Check reserved bit, higher 32 bits should be zero */
2161 if ((data >> 32) != 0)
2162 return 1;
2163 /* Otherwise falls through */
2164 default:
2165 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2166 break;
2167 msr = find_msr_entry(vmx, msr_index);
2168 if (msr) {
2169 vmx_load_host_state(vmx);
2170 msr->data = data;
2171 break;
2172 }
2173 ret = kvm_set_msr_common(vcpu, msr_index, data);
2174 }
2175
2176 return ret;
2177 }
2178
2179 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2180 {
2181 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2182 switch (reg) {
2183 case VCPU_REGS_RSP:
2184 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2185 break;
2186 case VCPU_REGS_RIP:
2187 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2188 break;
2189 case VCPU_EXREG_PDPTR:
2190 if (enable_ept)
2191 ept_save_pdptrs(vcpu);
2192 break;
2193 default:
2194 break;
2195 }
2196 }
2197
2198 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
2199 {
2200 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2201 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2202 else
2203 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2204
2205 update_exception_bitmap(vcpu);
2206 }
2207
2208 static __init int cpu_has_kvm_support(void)
2209 {
2210 return cpu_has_vmx();
2211 }
2212
2213 static __init int vmx_disabled_by_bios(void)
2214 {
2215 u64 msr;
2216
2217 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2218 if (msr & FEATURE_CONTROL_LOCKED) {
2219 /* launched w/ TXT and VMX disabled */
2220 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2221 && tboot_enabled())
2222 return 1;
2223 /* launched w/o TXT and VMX only enabled w/ TXT */
2224 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2225 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2226 && !tboot_enabled()) {
2227 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2228 "activate TXT before enabling KVM\n");
2229 return 1;
2230 }
2231 /* launched w/o TXT and VMX disabled */
2232 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2233 && !tboot_enabled())
2234 return 1;
2235 }
2236
2237 return 0;
2238 }
2239
2240 static void kvm_cpu_vmxon(u64 addr)
2241 {
2242 asm volatile (ASM_VMX_VMXON_RAX
2243 : : "a"(&addr), "m"(addr)
2244 : "memory", "cc");
2245 }
2246
2247 static int hardware_enable(void *garbage)
2248 {
2249 int cpu = raw_smp_processor_id();
2250 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2251 u64 old, test_bits;
2252
2253 if (read_cr4() & X86_CR4_VMXE)
2254 return -EBUSY;
2255
2256 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2257 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2258
2259 test_bits = FEATURE_CONTROL_LOCKED;
2260 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2261 if (tboot_enabled())
2262 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2263
2264 if ((old & test_bits) != test_bits) {
2265 /* enable and lock */
2266 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2267 }
2268 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2269
2270 if (vmm_exclusive) {
2271 kvm_cpu_vmxon(phys_addr);
2272 ept_sync_global();
2273 }
2274
2275 store_gdt(&__get_cpu_var(host_gdt));
2276
2277 return 0;
2278 }
2279
2280 static void vmclear_local_loaded_vmcss(void)
2281 {
2282 int cpu = raw_smp_processor_id();
2283 struct loaded_vmcs *v, *n;
2284
2285 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2286 loaded_vmcss_on_cpu_link)
2287 __loaded_vmcs_clear(v);
2288 }
2289
2290
2291 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2292 * tricks.
2293 */
2294 static void kvm_cpu_vmxoff(void)
2295 {
2296 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2297 }
2298
2299 static void hardware_disable(void *garbage)
2300 {
2301 if (vmm_exclusive) {
2302 vmclear_local_loaded_vmcss();
2303 kvm_cpu_vmxoff();
2304 }
2305 write_cr4(read_cr4() & ~X86_CR4_VMXE);
2306 }
2307
2308 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2309 u32 msr, u32 *result)
2310 {
2311 u32 vmx_msr_low, vmx_msr_high;
2312 u32 ctl = ctl_min | ctl_opt;
2313
2314 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2315
2316 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2317 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2318
2319 /* Ensure minimum (required) set of control bits are supported. */
2320 if (ctl_min & ~ctl)
2321 return -EIO;
2322
2323 *result = ctl;
2324 return 0;
2325 }
2326
2327 static __init bool allow_1_setting(u32 msr, u32 ctl)
2328 {
2329 u32 vmx_msr_low, vmx_msr_high;
2330
2331 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2332 return vmx_msr_high & ctl;
2333 }
2334
2335 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2336 {
2337 u32 vmx_msr_low, vmx_msr_high;
2338 u32 min, opt, min2, opt2;
2339 u32 _pin_based_exec_control = 0;
2340 u32 _cpu_based_exec_control = 0;
2341 u32 _cpu_based_2nd_exec_control = 0;
2342 u32 _vmexit_control = 0;
2343 u32 _vmentry_control = 0;
2344
2345 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2346 opt = PIN_BASED_VIRTUAL_NMIS;
2347 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2348 &_pin_based_exec_control) < 0)
2349 return -EIO;
2350
2351 min =
2352 #ifdef CONFIG_X86_64
2353 CPU_BASED_CR8_LOAD_EXITING |
2354 CPU_BASED_CR8_STORE_EXITING |
2355 #endif
2356 CPU_BASED_CR3_LOAD_EXITING |
2357 CPU_BASED_CR3_STORE_EXITING |
2358 CPU_BASED_USE_IO_BITMAPS |
2359 CPU_BASED_MOV_DR_EXITING |
2360 CPU_BASED_USE_TSC_OFFSETING |
2361 CPU_BASED_MWAIT_EXITING |
2362 CPU_BASED_MONITOR_EXITING |
2363 CPU_BASED_INVLPG_EXITING;
2364
2365 if (yield_on_hlt)
2366 min |= CPU_BASED_HLT_EXITING;
2367
2368 opt = CPU_BASED_TPR_SHADOW |
2369 CPU_BASED_USE_MSR_BITMAPS |
2370 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2371 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2372 &_cpu_based_exec_control) < 0)
2373 return -EIO;
2374 #ifdef CONFIG_X86_64
2375 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2376 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2377 ~CPU_BASED_CR8_STORE_EXITING;
2378 #endif
2379 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2380 min2 = 0;
2381 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2382 SECONDARY_EXEC_WBINVD_EXITING |
2383 SECONDARY_EXEC_ENABLE_VPID |
2384 SECONDARY_EXEC_ENABLE_EPT |
2385 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2386 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2387 SECONDARY_EXEC_RDTSCP;
2388 if (adjust_vmx_controls(min2, opt2,
2389 MSR_IA32_VMX_PROCBASED_CTLS2,
2390 &_cpu_based_2nd_exec_control) < 0)
2391 return -EIO;
2392 }
2393 #ifndef CONFIG_X86_64
2394 if (!(_cpu_based_2nd_exec_control &
2395 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2396 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2397 #endif
2398 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2399 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2400 enabled */
2401 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2402 CPU_BASED_CR3_STORE_EXITING |
2403 CPU_BASED_INVLPG_EXITING);
2404 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2405 vmx_capability.ept, vmx_capability.vpid);
2406 }
2407
2408 min = 0;
2409 #ifdef CONFIG_X86_64
2410 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2411 #endif
2412 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2413 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2414 &_vmexit_control) < 0)
2415 return -EIO;
2416
2417 min = 0;
2418 opt = VM_ENTRY_LOAD_IA32_PAT;
2419 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2420 &_vmentry_control) < 0)
2421 return -EIO;
2422
2423 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2424
2425 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2426 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2427 return -EIO;
2428
2429 #ifdef CONFIG_X86_64
2430 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2431 if (vmx_msr_high & (1u<<16))
2432 return -EIO;
2433 #endif
2434
2435 /* Require Write-Back (WB) memory type for VMCS accesses. */
2436 if (((vmx_msr_high >> 18) & 15) != 6)
2437 return -EIO;
2438
2439 vmcs_conf->size = vmx_msr_high & 0x1fff;
2440 vmcs_conf->order = get_order(vmcs_config.size);
2441 vmcs_conf->revision_id = vmx_msr_low;
2442
2443 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2444 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2445 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2446 vmcs_conf->vmexit_ctrl = _vmexit_control;
2447 vmcs_conf->vmentry_ctrl = _vmentry_control;
2448
2449 cpu_has_load_ia32_efer =
2450 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2451 VM_ENTRY_LOAD_IA32_EFER)
2452 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2453 VM_EXIT_LOAD_IA32_EFER);
2454
2455 return 0;
2456 }
2457
2458 static struct vmcs *alloc_vmcs_cpu(int cpu)
2459 {
2460 int node = cpu_to_node(cpu);
2461 struct page *pages;
2462 struct vmcs *vmcs;
2463
2464 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2465 if (!pages)
2466 return NULL;
2467 vmcs = page_address(pages);
2468 memset(vmcs, 0, vmcs_config.size);
2469 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2470 return vmcs;
2471 }
2472
2473 static struct vmcs *alloc_vmcs(void)
2474 {
2475 return alloc_vmcs_cpu(raw_smp_processor_id());
2476 }
2477
2478 static void free_vmcs(struct vmcs *vmcs)
2479 {
2480 free_pages((unsigned long)vmcs, vmcs_config.order);
2481 }
2482
2483 /*
2484 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2485 */
2486 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2487 {
2488 if (!loaded_vmcs->vmcs)
2489 return;
2490 loaded_vmcs_clear(loaded_vmcs);
2491 free_vmcs(loaded_vmcs->vmcs);
2492 loaded_vmcs->vmcs = NULL;
2493 }
2494
2495 static void free_kvm_area(void)
2496 {
2497 int cpu;
2498
2499 for_each_possible_cpu(cpu) {
2500 free_vmcs(per_cpu(vmxarea, cpu));
2501 per_cpu(vmxarea, cpu) = NULL;
2502 }
2503 }
2504
2505 static __init int alloc_kvm_area(void)
2506 {
2507 int cpu;
2508
2509 for_each_possible_cpu(cpu) {
2510 struct vmcs *vmcs;
2511
2512 vmcs = alloc_vmcs_cpu(cpu);
2513 if (!vmcs) {
2514 free_kvm_area();
2515 return -ENOMEM;
2516 }
2517
2518 per_cpu(vmxarea, cpu) = vmcs;
2519 }
2520 return 0;
2521 }
2522
2523 static __init int hardware_setup(void)
2524 {
2525 if (setup_vmcs_config(&vmcs_config) < 0)
2526 return -EIO;
2527
2528 if (boot_cpu_has(X86_FEATURE_NX))
2529 kvm_enable_efer_bits(EFER_NX);
2530
2531 if (!cpu_has_vmx_vpid())
2532 enable_vpid = 0;
2533
2534 if (!cpu_has_vmx_ept() ||
2535 !cpu_has_vmx_ept_4levels()) {
2536 enable_ept = 0;
2537 enable_unrestricted_guest = 0;
2538 }
2539
2540 if (!cpu_has_vmx_unrestricted_guest())
2541 enable_unrestricted_guest = 0;
2542
2543 if (!cpu_has_vmx_flexpriority())
2544 flexpriority_enabled = 0;
2545
2546 if (!cpu_has_vmx_tpr_shadow())
2547 kvm_x86_ops->update_cr8_intercept = NULL;
2548
2549 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2550 kvm_disable_largepages();
2551
2552 if (!cpu_has_vmx_ple())
2553 ple_gap = 0;
2554
2555 if (nested)
2556 nested_vmx_setup_ctls_msrs();
2557
2558 return alloc_kvm_area();
2559 }
2560
2561 static __exit void hardware_unsetup(void)
2562 {
2563 free_kvm_area();
2564 }
2565
2566 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2567 {
2568 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2569
2570 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
2571 vmcs_write16(sf->selector, save->selector);
2572 vmcs_writel(sf->base, save->base);
2573 vmcs_write32(sf->limit, save->limit);
2574 vmcs_write32(sf->ar_bytes, save->ar);
2575 } else {
2576 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2577 << AR_DPL_SHIFT;
2578 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2579 }
2580 }
2581
2582 static void enter_pmode(struct kvm_vcpu *vcpu)
2583 {
2584 unsigned long flags;
2585 struct vcpu_vmx *vmx = to_vmx(vcpu);
2586
2587 vmx->emulation_required = 1;
2588 vmx->rmode.vm86_active = 0;
2589
2590 vmx_segment_cache_clear(vmx);
2591
2592 vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
2593 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2594 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2595 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
2596
2597 flags = vmcs_readl(GUEST_RFLAGS);
2598 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2599 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2600 vmcs_writel(GUEST_RFLAGS, flags);
2601
2602 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2603 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2604
2605 update_exception_bitmap(vcpu);
2606
2607 if (emulate_invalid_guest_state)
2608 return;
2609
2610 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2611 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2612 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2613 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
2614
2615 vmx_segment_cache_clear(vmx);
2616
2617 vmcs_write16(GUEST_SS_SELECTOR, 0);
2618 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2619
2620 vmcs_write16(GUEST_CS_SELECTOR,
2621 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2622 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2623 }
2624
2625 static gva_t rmode_tss_base(struct kvm *kvm)
2626 {
2627 if (!kvm->arch.tss_addr) {
2628 struct kvm_memslots *slots;
2629 gfn_t base_gfn;
2630
2631 slots = kvm_memslots(kvm);
2632 base_gfn = slots->memslots[0].base_gfn +
2633 kvm->memslots->memslots[0].npages - 3;
2634 return base_gfn << PAGE_SHIFT;
2635 }
2636 return kvm->arch.tss_addr;
2637 }
2638
2639 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2640 {
2641 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2642
2643 save->selector = vmcs_read16(sf->selector);
2644 save->base = vmcs_readl(sf->base);
2645 save->limit = vmcs_read32(sf->limit);
2646 save->ar = vmcs_read32(sf->ar_bytes);
2647 vmcs_write16(sf->selector, save->base >> 4);
2648 vmcs_write32(sf->base, save->base & 0xffff0);
2649 vmcs_write32(sf->limit, 0xffff);
2650 vmcs_write32(sf->ar_bytes, 0xf3);
2651 if (save->base & 0xf)
2652 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2653 " aligned when entering protected mode (seg=%d)",
2654 seg);
2655 }
2656
2657 static void enter_rmode(struct kvm_vcpu *vcpu)
2658 {
2659 unsigned long flags;
2660 struct vcpu_vmx *vmx = to_vmx(vcpu);
2661
2662 if (enable_unrestricted_guest)
2663 return;
2664
2665 vmx->emulation_required = 1;
2666 vmx->rmode.vm86_active = 1;
2667
2668 /*
2669 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2670 * vcpu. Call it here with phys address pointing 16M below 4G.
2671 */
2672 if (!vcpu->kvm->arch.tss_addr) {
2673 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2674 "called before entering vcpu\n");
2675 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2676 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2677 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2678 }
2679
2680 vmx_segment_cache_clear(vmx);
2681
2682 vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
2683 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
2684 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2685
2686 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
2687 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2688
2689 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
2690 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2691
2692 flags = vmcs_readl(GUEST_RFLAGS);
2693 vmx->rmode.save_rflags = flags;
2694
2695 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2696
2697 vmcs_writel(GUEST_RFLAGS, flags);
2698 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2699 update_exception_bitmap(vcpu);
2700
2701 if (emulate_invalid_guest_state)
2702 goto continue_rmode;
2703
2704 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
2705 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
2706 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
2707
2708 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
2709 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
2710 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
2711 vmcs_writel(GUEST_CS_BASE, 0xf0000);
2712 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
2713
2714 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
2715 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
2716 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
2717 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
2718
2719 continue_rmode:
2720 kvm_mmu_reset_context(vcpu);
2721 }
2722
2723 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2724 {
2725 struct vcpu_vmx *vmx = to_vmx(vcpu);
2726 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2727
2728 if (!msr)
2729 return;
2730
2731 /*
2732 * Force kernel_gs_base reloading before EFER changes, as control
2733 * of this msr depends on is_long_mode().
2734 */
2735 vmx_load_host_state(to_vmx(vcpu));
2736 vcpu->arch.efer = efer;
2737 if (efer & EFER_LMA) {
2738 vmcs_write32(VM_ENTRY_CONTROLS,
2739 vmcs_read32(VM_ENTRY_CONTROLS) |
2740 VM_ENTRY_IA32E_MODE);
2741 msr->data = efer;
2742 } else {
2743 vmcs_write32(VM_ENTRY_CONTROLS,
2744 vmcs_read32(VM_ENTRY_CONTROLS) &
2745 ~VM_ENTRY_IA32E_MODE);
2746
2747 msr->data = efer & ~EFER_LME;
2748 }
2749 setup_msrs(vmx);
2750 }
2751
2752 #ifdef CONFIG_X86_64
2753
2754 static void enter_lmode(struct kvm_vcpu *vcpu)
2755 {
2756 u32 guest_tr_ar;
2757
2758 vmx_segment_cache_clear(to_vmx(vcpu));
2759
2760 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2761 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2762 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
2763 __func__);
2764 vmcs_write32(GUEST_TR_AR_BYTES,
2765 (guest_tr_ar & ~AR_TYPE_MASK)
2766 | AR_TYPE_BUSY_64_TSS);
2767 }
2768 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2769 }
2770
2771 static void exit_lmode(struct kvm_vcpu *vcpu)
2772 {
2773 vmcs_write32(VM_ENTRY_CONTROLS,
2774 vmcs_read32(VM_ENTRY_CONTROLS)
2775 & ~VM_ENTRY_IA32E_MODE);
2776 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2777 }
2778
2779 #endif
2780
2781 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2782 {
2783 vpid_sync_context(to_vmx(vcpu));
2784 if (enable_ept) {
2785 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2786 return;
2787 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2788 }
2789 }
2790
2791 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2792 {
2793 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2794
2795 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2796 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2797 }
2798
2799 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2800 {
2801 if (enable_ept && is_paging(vcpu))
2802 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2803 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2804 }
2805
2806 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2807 {
2808 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2809
2810 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2811 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2812 }
2813
2814 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2815 {
2816 if (!test_bit(VCPU_EXREG_PDPTR,
2817 (unsigned long *)&vcpu->arch.regs_dirty))
2818 return;
2819
2820 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2821 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2822 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2823 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2824 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2825 }
2826 }
2827
2828 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2829 {
2830 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2831 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2832 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2833 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2834 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2835 }
2836
2837 __set_bit(VCPU_EXREG_PDPTR,
2838 (unsigned long *)&vcpu->arch.regs_avail);
2839 __set_bit(VCPU_EXREG_PDPTR,
2840 (unsigned long *)&vcpu->arch.regs_dirty);
2841 }
2842
2843 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2844
2845 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2846 unsigned long cr0,
2847 struct kvm_vcpu *vcpu)
2848 {
2849 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2850 vmx_decache_cr3(vcpu);
2851 if (!(cr0 & X86_CR0_PG)) {
2852 /* From paging/starting to nonpaging */
2853 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2854 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2855 (CPU_BASED_CR3_LOAD_EXITING |
2856 CPU_BASED_CR3_STORE_EXITING));
2857 vcpu->arch.cr0 = cr0;
2858 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2859 } else if (!is_paging(vcpu)) {
2860 /* From nonpaging to paging */
2861 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2862 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
2863 ~(CPU_BASED_CR3_LOAD_EXITING |
2864 CPU_BASED_CR3_STORE_EXITING));
2865 vcpu->arch.cr0 = cr0;
2866 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2867 }
2868
2869 if (!(cr0 & X86_CR0_WP))
2870 *hw_cr0 &= ~X86_CR0_WP;
2871 }
2872
2873 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2874 {
2875 struct vcpu_vmx *vmx = to_vmx(vcpu);
2876 unsigned long hw_cr0;
2877
2878 if (enable_unrestricted_guest)
2879 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2880 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2881 else
2882 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
2883
2884 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2885 enter_pmode(vcpu);
2886
2887 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2888 enter_rmode(vcpu);
2889
2890 #ifdef CONFIG_X86_64
2891 if (vcpu->arch.efer & EFER_LME) {
2892 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2893 enter_lmode(vcpu);
2894 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2895 exit_lmode(vcpu);
2896 }
2897 #endif
2898
2899 if (enable_ept)
2900 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2901
2902 if (!vcpu->fpu_active)
2903 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
2904
2905 vmcs_writel(CR0_READ_SHADOW, cr0);
2906 vmcs_writel(GUEST_CR0, hw_cr0);
2907 vcpu->arch.cr0 = cr0;
2908 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2909 }
2910
2911 static u64 construct_eptp(unsigned long root_hpa)
2912 {
2913 u64 eptp;
2914
2915 /* TODO write the value reading from MSR */
2916 eptp = VMX_EPT_DEFAULT_MT |
2917 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
2918 eptp |= (root_hpa & PAGE_MASK);
2919
2920 return eptp;
2921 }
2922
2923 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2924 {
2925 unsigned long guest_cr3;
2926 u64 eptp;
2927
2928 guest_cr3 = cr3;
2929 if (enable_ept) {
2930 eptp = construct_eptp(cr3);
2931 vmcs_write64(EPT_POINTER, eptp);
2932 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
2933 vcpu->kvm->arch.ept_identity_map_addr;
2934 ept_load_pdptrs(vcpu);
2935 }
2936
2937 vmx_flush_tlb(vcpu);
2938 vmcs_writel(GUEST_CR3, guest_cr3);
2939 }
2940
2941 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2942 {
2943 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
2944 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2945
2946 if (cr4 & X86_CR4_VMXE) {
2947 /*
2948 * To use VMXON (and later other VMX instructions), a guest
2949 * must first be able to turn on cr4.VMXE (see handle_vmon()).
2950 * So basically the check on whether to allow nested VMX
2951 * is here.
2952 */
2953 if (!nested_vmx_allowed(vcpu))
2954 return 1;
2955 } else if (to_vmx(vcpu)->nested.vmxon)
2956 return 1;
2957
2958 vcpu->arch.cr4 = cr4;
2959 if (enable_ept) {
2960 if (!is_paging(vcpu)) {
2961 hw_cr4 &= ~X86_CR4_PAE;
2962 hw_cr4 |= X86_CR4_PSE;
2963 } else if (!(cr4 & X86_CR4_PAE)) {
2964 hw_cr4 &= ~X86_CR4_PAE;
2965 }
2966 }
2967
2968 vmcs_writel(CR4_READ_SHADOW, cr4);
2969 vmcs_writel(GUEST_CR4, hw_cr4);
2970 return 0;
2971 }
2972
2973 static void vmx_get_segment(struct kvm_vcpu *vcpu,
2974 struct kvm_segment *var, int seg)
2975 {
2976 struct vcpu_vmx *vmx = to_vmx(vcpu);
2977 struct kvm_save_segment *save;
2978 u32 ar;
2979
2980 if (vmx->rmode.vm86_active
2981 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
2982 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
2983 || seg == VCPU_SREG_GS)
2984 && !emulate_invalid_guest_state) {
2985 switch (seg) {
2986 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
2987 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
2988 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
2989 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
2990 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
2991 default: BUG();
2992 }
2993 var->selector = save->selector;
2994 var->base = save->base;
2995 var->limit = save->limit;
2996 ar = save->ar;
2997 if (seg == VCPU_SREG_TR
2998 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
2999 goto use_saved_rmode_seg;
3000 }
3001 var->base = vmx_read_guest_seg_base(vmx, seg);
3002 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3003 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3004 ar = vmx_read_guest_seg_ar(vmx, seg);
3005 use_saved_rmode_seg:
3006 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
3007 ar = 0;
3008 var->type = ar & 15;
3009 var->s = (ar >> 4) & 1;
3010 var->dpl = (ar >> 5) & 3;
3011 var->present = (ar >> 7) & 1;
3012 var->avl = (ar >> 12) & 1;
3013 var->l = (ar >> 13) & 1;
3014 var->db = (ar >> 14) & 1;
3015 var->g = (ar >> 15) & 1;
3016 var->unusable = (ar >> 16) & 1;
3017 }
3018
3019 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3020 {
3021 struct kvm_segment s;
3022
3023 if (to_vmx(vcpu)->rmode.vm86_active) {
3024 vmx_get_segment(vcpu, &s, seg);
3025 return s.base;
3026 }
3027 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3028 }
3029
3030 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
3031 {
3032 if (!is_protmode(vcpu))
3033 return 0;
3034
3035 if (!is_long_mode(vcpu)
3036 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3037 return 3;
3038
3039 return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
3040 }
3041
3042 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3043 {
3044 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3045 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3046 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
3047 }
3048 return to_vmx(vcpu)->cpl;
3049 }
3050
3051
3052 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3053 {
3054 u32 ar;
3055
3056 if (var->unusable)
3057 ar = 1 << 16;
3058 else {
3059 ar = var->type & 15;
3060 ar |= (var->s & 1) << 4;
3061 ar |= (var->dpl & 3) << 5;
3062 ar |= (var->present & 1) << 7;
3063 ar |= (var->avl & 1) << 12;
3064 ar |= (var->l & 1) << 13;
3065 ar |= (var->db & 1) << 14;
3066 ar |= (var->g & 1) << 15;
3067 }
3068 if (ar == 0) /* a 0 value means unusable */
3069 ar = AR_UNUSABLE_MASK;
3070
3071 return ar;
3072 }
3073
3074 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3075 struct kvm_segment *var, int seg)
3076 {
3077 struct vcpu_vmx *vmx = to_vmx(vcpu);
3078 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3079 u32 ar;
3080
3081 vmx_segment_cache_clear(vmx);
3082
3083 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
3084 vmcs_write16(sf->selector, var->selector);
3085 vmx->rmode.tr.selector = var->selector;
3086 vmx->rmode.tr.base = var->base;
3087 vmx->rmode.tr.limit = var->limit;
3088 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
3089 return;
3090 }
3091 vmcs_writel(sf->base, var->base);
3092 vmcs_write32(sf->limit, var->limit);
3093 vmcs_write16(sf->selector, var->selector);
3094 if (vmx->rmode.vm86_active && var->s) {
3095 /*
3096 * Hack real-mode segments into vm86 compatibility.
3097 */
3098 if (var->base == 0xffff0000 && var->selector == 0xf000)
3099 vmcs_writel(sf->base, 0xf0000);
3100 ar = 0xf3;
3101 } else
3102 ar = vmx_segment_access_rights(var);
3103
3104 /*
3105 * Fix the "Accessed" bit in AR field of segment registers for older
3106 * qemu binaries.
3107 * IA32 arch specifies that at the time of processor reset the
3108 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3109 * is setting it to 0 in the usedland code. This causes invalid guest
3110 * state vmexit when "unrestricted guest" mode is turned on.
3111 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3112 * tree. Newer qemu binaries with that qemu fix would not need this
3113 * kvm hack.
3114 */
3115 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3116 ar |= 0x1; /* Accessed */
3117
3118 vmcs_write32(sf->ar_bytes, ar);
3119 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3120 }
3121
3122 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3123 {
3124 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3125
3126 *db = (ar >> 14) & 1;
3127 *l = (ar >> 13) & 1;
3128 }
3129
3130 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3131 {
3132 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3133 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3134 }
3135
3136 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3137 {
3138 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3139 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3140 }
3141
3142 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3143 {
3144 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3145 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3146 }
3147
3148 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3149 {
3150 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3151 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3152 }
3153
3154 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3155 {
3156 struct kvm_segment var;
3157 u32 ar;
3158
3159 vmx_get_segment(vcpu, &var, seg);
3160 ar = vmx_segment_access_rights(&var);
3161
3162 if (var.base != (var.selector << 4))
3163 return false;
3164 if (var.limit != 0xffff)
3165 return false;
3166 if (ar != 0xf3)
3167 return false;
3168
3169 return true;
3170 }
3171
3172 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3173 {
3174 struct kvm_segment cs;
3175 unsigned int cs_rpl;
3176
3177 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3178 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3179
3180 if (cs.unusable)
3181 return false;
3182 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3183 return false;
3184 if (!cs.s)
3185 return false;
3186 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3187 if (cs.dpl > cs_rpl)
3188 return false;
3189 } else {
3190 if (cs.dpl != cs_rpl)
3191 return false;
3192 }
3193 if (!cs.present)
3194 return false;
3195
3196 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3197 return true;
3198 }
3199
3200 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3201 {
3202 struct kvm_segment ss;
3203 unsigned int ss_rpl;
3204
3205 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3206 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3207
3208 if (ss.unusable)
3209 return true;
3210 if (ss.type != 3 && ss.type != 7)
3211 return false;
3212 if (!ss.s)
3213 return false;
3214 if (ss.dpl != ss_rpl) /* DPL != RPL */
3215 return false;
3216 if (!ss.present)
3217 return false;
3218
3219 return true;
3220 }
3221
3222 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3223 {
3224 struct kvm_segment var;
3225 unsigned int rpl;
3226
3227 vmx_get_segment(vcpu, &var, seg);
3228 rpl = var.selector & SELECTOR_RPL_MASK;
3229
3230 if (var.unusable)
3231 return true;
3232 if (!var.s)
3233 return false;
3234 if (!var.present)
3235 return false;
3236 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3237 if (var.dpl < rpl) /* DPL < RPL */
3238 return false;
3239 }
3240
3241 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3242 * rights flags
3243 */
3244 return true;
3245 }
3246
3247 static bool tr_valid(struct kvm_vcpu *vcpu)
3248 {
3249 struct kvm_segment tr;
3250
3251 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3252
3253 if (tr.unusable)
3254 return false;
3255 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3256 return false;
3257 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3258 return false;
3259 if (!tr.present)
3260 return false;
3261
3262 return true;
3263 }
3264
3265 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3266 {
3267 struct kvm_segment ldtr;
3268
3269 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3270
3271 if (ldtr.unusable)
3272 return true;
3273 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3274 return false;
3275 if (ldtr.type != 2)
3276 return false;
3277 if (!ldtr.present)
3278 return false;
3279
3280 return true;
3281 }
3282
3283 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3284 {
3285 struct kvm_segment cs, ss;
3286
3287 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3288 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3289
3290 return ((cs.selector & SELECTOR_RPL_MASK) ==
3291 (ss.selector & SELECTOR_RPL_MASK));
3292 }
3293
3294 /*
3295 * Check if guest state is valid. Returns true if valid, false if
3296 * not.
3297 * We assume that registers are always usable
3298 */
3299 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3300 {
3301 /* real mode guest state checks */
3302 if (!is_protmode(vcpu)) {
3303 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3304 return false;
3305 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3306 return false;
3307 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3308 return false;
3309 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3310 return false;
3311 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3312 return false;
3313 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3314 return false;
3315 } else {
3316 /* protected mode guest state checks */
3317 if (!cs_ss_rpl_check(vcpu))
3318 return false;
3319 if (!code_segment_valid(vcpu))
3320 return false;
3321 if (!stack_segment_valid(vcpu))
3322 return false;
3323 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3324 return false;
3325 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3326 return false;
3327 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3328 return false;
3329 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3330 return false;
3331 if (!tr_valid(vcpu))
3332 return false;
3333 if (!ldtr_valid(vcpu))
3334 return false;
3335 }
3336 /* TODO:
3337 * - Add checks on RIP
3338 * - Add checks on RFLAGS
3339 */
3340
3341 return true;
3342 }
3343
3344 static int init_rmode_tss(struct kvm *kvm)
3345 {
3346 gfn_t fn;
3347 u16 data = 0;
3348 int r, idx, ret = 0;
3349
3350 idx = srcu_read_lock(&kvm->srcu);
3351 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3352 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3353 if (r < 0)
3354 goto out;
3355 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3356 r = kvm_write_guest_page(kvm, fn++, &data,
3357 TSS_IOPB_BASE_OFFSET, sizeof(u16));
3358 if (r < 0)
3359 goto out;
3360 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3361 if (r < 0)
3362 goto out;
3363 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3364 if (r < 0)
3365 goto out;
3366 data = ~0;
3367 r = kvm_write_guest_page(kvm, fn, &data,
3368 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3369 sizeof(u8));
3370 if (r < 0)
3371 goto out;
3372
3373 ret = 1;
3374 out:
3375 srcu_read_unlock(&kvm->srcu, idx);
3376 return ret;
3377 }
3378
3379 static int init_rmode_identity_map(struct kvm *kvm)
3380 {
3381 int i, idx, r, ret;
3382 pfn_t identity_map_pfn;
3383 u32 tmp;
3384
3385 if (!enable_ept)
3386 return 1;
3387 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3388 printk(KERN_ERR "EPT: identity-mapping pagetable "
3389 "haven't been allocated!\n");
3390 return 0;
3391 }
3392 if (likely(kvm->arch.ept_identity_pagetable_done))
3393 return 1;
3394 ret = 0;
3395 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3396 idx = srcu_read_lock(&kvm->srcu);
3397 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3398 if (r < 0)
3399 goto out;
3400 /* Set up identity-mapping pagetable for EPT in real mode */
3401 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3402 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3403 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3404 r = kvm_write_guest_page(kvm, identity_map_pfn,
3405 &tmp, i * sizeof(tmp), sizeof(tmp));
3406 if (r < 0)
3407 goto out;
3408 }
3409 kvm->arch.ept_identity_pagetable_done = true;
3410 ret = 1;
3411 out:
3412 srcu_read_unlock(&kvm->srcu, idx);
3413 return ret;
3414 }
3415
3416 static void seg_setup(int seg)
3417 {
3418 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3419 unsigned int ar;
3420
3421 vmcs_write16(sf->selector, 0);
3422 vmcs_writel(sf->base, 0);
3423 vmcs_write32(sf->limit, 0xffff);
3424 if (enable_unrestricted_guest) {
3425 ar = 0x93;
3426 if (seg == VCPU_SREG_CS)
3427 ar |= 0x08; /* code segment */
3428 } else
3429 ar = 0xf3;
3430
3431 vmcs_write32(sf->ar_bytes, ar);
3432 }
3433
3434 static int alloc_apic_access_page(struct kvm *kvm)
3435 {
3436 struct kvm_userspace_memory_region kvm_userspace_mem;
3437 int r = 0;
3438
3439 mutex_lock(&kvm->slots_lock);
3440 if (kvm->arch.apic_access_page)
3441 goto out;
3442 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3443 kvm_userspace_mem.flags = 0;
3444 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3445 kvm_userspace_mem.memory_size = PAGE_SIZE;
3446 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3447 if (r)
3448 goto out;
3449
3450 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
3451 out:
3452 mutex_unlock(&kvm->slots_lock);
3453 return r;
3454 }
3455
3456 static int alloc_identity_pagetable(struct kvm *kvm)
3457 {
3458 struct kvm_userspace_memory_region kvm_userspace_mem;
3459 int r = 0;
3460
3461 mutex_lock(&kvm->slots_lock);
3462 if (kvm->arch.ept_identity_pagetable)
3463 goto out;
3464 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3465 kvm_userspace_mem.flags = 0;
3466 kvm_userspace_mem.guest_phys_addr =
3467 kvm->arch.ept_identity_map_addr;
3468 kvm_userspace_mem.memory_size = PAGE_SIZE;
3469 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3470 if (r)
3471 goto out;
3472
3473 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
3474 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3475 out:
3476 mutex_unlock(&kvm->slots_lock);
3477 return r;
3478 }
3479
3480 static void allocate_vpid(struct vcpu_vmx *vmx)
3481 {
3482 int vpid;
3483
3484 vmx->vpid = 0;
3485 if (!enable_vpid)
3486 return;
3487 spin_lock(&vmx_vpid_lock);
3488 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3489 if (vpid < VMX_NR_VPIDS) {
3490 vmx->vpid = vpid;
3491 __set_bit(vpid, vmx_vpid_bitmap);
3492 }
3493 spin_unlock(&vmx_vpid_lock);
3494 }
3495
3496 static void free_vpid(struct vcpu_vmx *vmx)
3497 {
3498 if (!enable_vpid)
3499 return;
3500 spin_lock(&vmx_vpid_lock);
3501 if (vmx->vpid != 0)
3502 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3503 spin_unlock(&vmx_vpid_lock);
3504 }
3505
3506 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
3507 {
3508 int f = sizeof(unsigned long);
3509
3510 if (!cpu_has_vmx_msr_bitmap())
3511 return;
3512
3513 /*
3514 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3515 * have the write-low and read-high bitmap offsets the wrong way round.
3516 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3517 */
3518 if (msr <= 0x1fff) {
3519 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3520 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
3521 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3522 msr &= 0x1fff;
3523 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3524 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
3525 }
3526 }
3527
3528 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3529 {
3530 if (!longmode_only)
3531 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3532 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3533 }
3534
3535 /*
3536 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3537 * will not change in the lifetime of the guest.
3538 * Note that host-state that does change is set elsewhere. E.g., host-state
3539 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3540 */
3541 static void vmx_set_constant_host_state(void)
3542 {
3543 u32 low32, high32;
3544 unsigned long tmpl;
3545 struct desc_ptr dt;
3546
3547 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
3548 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3549 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3550
3551 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
3552 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3553 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3554 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3555 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3556
3557 native_store_idt(&dt);
3558 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3559
3560 asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3561 vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3562
3563 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3564 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3565 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3566 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3567
3568 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3569 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3570 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3571 }
3572 }
3573
3574 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3575 {
3576 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3577 if (enable_ept)
3578 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3579 if (is_guest_mode(&vmx->vcpu))
3580 vmx->vcpu.arch.cr4_guest_owned_bits &=
3581 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3582 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3583 }
3584
3585 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3586 {
3587 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3588 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3589 exec_control &= ~CPU_BASED_TPR_SHADOW;
3590 #ifdef CONFIG_X86_64
3591 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3592 CPU_BASED_CR8_LOAD_EXITING;
3593 #endif
3594 }
3595 if (!enable_ept)
3596 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3597 CPU_BASED_CR3_LOAD_EXITING |
3598 CPU_BASED_INVLPG_EXITING;
3599 return exec_control;
3600 }
3601
3602 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3603 {
3604 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3605 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3606 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3607 if (vmx->vpid == 0)
3608 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3609 if (!enable_ept) {
3610 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3611 enable_unrestricted_guest = 0;
3612 }
3613 if (!enable_unrestricted_guest)
3614 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3615 if (!ple_gap)
3616 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3617 return exec_control;
3618 }
3619
3620 static void ept_set_mmio_spte_mask(void)
3621 {
3622 /*
3623 * EPT Misconfigurations can be generated if the value of bits 2:0
3624 * of an EPT paging-structure entry is 110b (write/execute).
3625 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3626 * spte.
3627 */
3628 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3629 }
3630
3631 /*
3632 * Sets up the vmcs for emulated real mode.
3633 */
3634 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3635 {
3636 #ifdef CONFIG_X86_64
3637 unsigned long a;
3638 #endif
3639 int i;
3640
3641 /* I/O */
3642 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3643 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
3644
3645 if (cpu_has_vmx_msr_bitmap())
3646 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
3647
3648 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3649
3650 /* Control */
3651 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3652 vmcs_config.pin_based_exec_ctrl);
3653
3654 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
3655
3656 if (cpu_has_secondary_exec_ctrls()) {
3657 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3658 vmx_secondary_exec_control(vmx));
3659 }
3660
3661 if (ple_gap) {
3662 vmcs_write32(PLE_GAP, ple_gap);
3663 vmcs_write32(PLE_WINDOW, ple_window);
3664 }
3665
3666 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3667 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
3668 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
3669
3670 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
3671 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
3672 vmx_set_constant_host_state();
3673 #ifdef CONFIG_X86_64
3674 rdmsrl(MSR_FS_BASE, a);
3675 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3676 rdmsrl(MSR_GS_BASE, a);
3677 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3678 #else
3679 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3680 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3681 #endif
3682
3683 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3684 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3685 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
3686 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3687 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
3688
3689 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3690 u32 msr_low, msr_high;
3691 u64 host_pat;
3692 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3693 host_pat = msr_low | ((u64) msr_high << 32);
3694 /* Write the default value follow host pat */
3695 vmcs_write64(GUEST_IA32_PAT, host_pat);
3696 /* Keep arch.pat sync with GUEST_IA32_PAT */
3697 vmx->vcpu.arch.pat = host_pat;
3698 }
3699
3700 for (i = 0; i < NR_VMX_MSR; ++i) {
3701 u32 index = vmx_msr_index[i];
3702 u32 data_low, data_high;
3703 int j = vmx->nmsrs;
3704
3705 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3706 continue;
3707 if (wrmsr_safe(index, data_low, data_high) < 0)
3708 continue;
3709 vmx->guest_msrs[j].index = i;
3710 vmx->guest_msrs[j].data = 0;
3711 vmx->guest_msrs[j].mask = -1ull;
3712 ++vmx->nmsrs;
3713 }
3714
3715 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
3716
3717 /* 22.2.1, 20.8.1 */
3718 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3719
3720 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
3721 set_cr4_guest_host_mask(vmx);
3722
3723 kvm_write_tsc(&vmx->vcpu, 0);
3724
3725 return 0;
3726 }
3727
3728 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3729 {
3730 struct vcpu_vmx *vmx = to_vmx(vcpu);
3731 u64 msr;
3732 int ret;
3733
3734 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3735
3736 vmx->rmode.vm86_active = 0;
3737
3738 vmx->soft_vnmi_blocked = 0;
3739
3740 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
3741 kvm_set_cr8(&vmx->vcpu, 0);
3742 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
3743 if (kvm_vcpu_is_bsp(&vmx->vcpu))
3744 msr |= MSR_IA32_APICBASE_BSP;
3745 kvm_set_apic_base(&vmx->vcpu, msr);
3746
3747 ret = fx_init(&vmx->vcpu);
3748 if (ret != 0)
3749 goto out;
3750
3751 vmx_segment_cache_clear(vmx);
3752
3753 seg_setup(VCPU_SREG_CS);
3754 /*
3755 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3756 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3757 */
3758 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
3759 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3760 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3761 } else {
3762 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3763 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
3764 }
3765
3766 seg_setup(VCPU_SREG_DS);
3767 seg_setup(VCPU_SREG_ES);
3768 seg_setup(VCPU_SREG_FS);
3769 seg_setup(VCPU_SREG_GS);
3770 seg_setup(VCPU_SREG_SS);
3771
3772 vmcs_write16(GUEST_TR_SELECTOR, 0);
3773 vmcs_writel(GUEST_TR_BASE, 0);
3774 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3775 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3776
3777 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3778 vmcs_writel(GUEST_LDTR_BASE, 0);
3779 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3780 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3781
3782 vmcs_write32(GUEST_SYSENTER_CS, 0);
3783 vmcs_writel(GUEST_SYSENTER_ESP, 0);
3784 vmcs_writel(GUEST_SYSENTER_EIP, 0);
3785
3786 vmcs_writel(GUEST_RFLAGS, 0x02);
3787 if (kvm_vcpu_is_bsp(&vmx->vcpu))
3788 kvm_rip_write(vcpu, 0xfff0);
3789 else
3790 kvm_rip_write(vcpu, 0);
3791 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
3792
3793 vmcs_writel(GUEST_DR7, 0x400);
3794
3795 vmcs_writel(GUEST_GDTR_BASE, 0);
3796 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3797
3798 vmcs_writel(GUEST_IDTR_BASE, 0);
3799 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3800
3801 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3802 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3803 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3804
3805 /* Special registers */
3806 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3807
3808 setup_msrs(vmx);
3809
3810 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
3811
3812 if (cpu_has_vmx_tpr_shadow()) {
3813 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3814 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3815 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
3816 __pa(vmx->vcpu.arch.apic->regs));
3817 vmcs_write32(TPR_THRESHOLD, 0);
3818 }
3819
3820 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3821 vmcs_write64(APIC_ACCESS_ADDR,
3822 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
3823
3824 if (vmx->vpid != 0)
3825 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3826
3827 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
3828 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
3829 vmx_set_cr4(&vmx->vcpu, 0);
3830 vmx_set_efer(&vmx->vcpu, 0);
3831 vmx_fpu_activate(&vmx->vcpu);
3832 update_exception_bitmap(&vmx->vcpu);
3833
3834 vpid_sync_context(vmx);
3835
3836 ret = 0;
3837
3838 /* HACK: Don't enable emulation on guest boot/reset */
3839 vmx->emulation_required = 0;
3840
3841 out:
3842 return ret;
3843 }
3844
3845 /*
3846 * In nested virtualization, check if L1 asked to exit on external interrupts.
3847 * For most existing hypervisors, this will always return true.
3848 */
3849 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
3850 {
3851 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
3852 PIN_BASED_EXT_INTR_MASK;
3853 }
3854
3855 static void enable_irq_window(struct kvm_vcpu *vcpu)
3856 {
3857 u32 cpu_based_vm_exec_control;
3858 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
3859 /* We can get here when nested_run_pending caused
3860 * vmx_interrupt_allowed() to return false. In this case, do
3861 * nothing - the interrupt will be injected later.
3862 */
3863 return;
3864
3865 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3866 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3867 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3868 }
3869
3870 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3871 {
3872 u32 cpu_based_vm_exec_control;
3873
3874 if (!cpu_has_virtual_nmis()) {
3875 enable_irq_window(vcpu);
3876 return;
3877 }
3878
3879 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
3880 enable_irq_window(vcpu);
3881 return;
3882 }
3883 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3884 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3885 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3886 }
3887
3888 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
3889 {
3890 struct vcpu_vmx *vmx = to_vmx(vcpu);
3891 uint32_t intr;
3892 int irq = vcpu->arch.interrupt.nr;
3893
3894 trace_kvm_inj_virq(irq);
3895
3896 ++vcpu->stat.irq_injections;
3897 if (vmx->rmode.vm86_active) {
3898 int inc_eip = 0;
3899 if (vcpu->arch.interrupt.soft)
3900 inc_eip = vcpu->arch.event_exit_inst_len;
3901 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
3902 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3903 return;
3904 }
3905 intr = irq | INTR_INFO_VALID_MASK;
3906 if (vcpu->arch.interrupt.soft) {
3907 intr |= INTR_TYPE_SOFT_INTR;
3908 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3909 vmx->vcpu.arch.event_exit_inst_len);
3910 } else
3911 intr |= INTR_TYPE_EXT_INTR;
3912 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
3913 vmx_clear_hlt(vcpu);
3914 }
3915
3916 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
3917 {
3918 struct vcpu_vmx *vmx = to_vmx(vcpu);
3919
3920 if (is_guest_mode(vcpu))
3921 return;
3922
3923 if (!cpu_has_virtual_nmis()) {
3924 /*
3925 * Tracking the NMI-blocked state in software is built upon
3926 * finding the next open IRQ window. This, in turn, depends on
3927 * well-behaving guests: They have to keep IRQs disabled at
3928 * least as long as the NMI handler runs. Otherwise we may
3929 * cause NMI nesting, maybe breaking the guest. But as this is
3930 * highly unlikely, we can live with the residual risk.
3931 */
3932 vmx->soft_vnmi_blocked = 1;
3933 vmx->vnmi_blocked_time = 0;
3934 }
3935
3936 ++vcpu->stat.nmi_injections;
3937 vmx->nmi_known_unmasked = false;
3938 if (vmx->rmode.vm86_active) {
3939 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
3940 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3941 return;
3942 }
3943 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
3944 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
3945 vmx_clear_hlt(vcpu);
3946 }
3947
3948 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
3949 {
3950 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
3951 return 0;
3952
3953 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3954 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
3955 | GUEST_INTR_STATE_NMI));
3956 }
3957
3958 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
3959 {
3960 if (!cpu_has_virtual_nmis())
3961 return to_vmx(vcpu)->soft_vnmi_blocked;
3962 if (to_vmx(vcpu)->nmi_known_unmasked)
3963 return false;
3964 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3965 }
3966
3967 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3968 {
3969 struct vcpu_vmx *vmx = to_vmx(vcpu);
3970
3971 if (!cpu_has_virtual_nmis()) {
3972 if (vmx->soft_vnmi_blocked != masked) {
3973 vmx->soft_vnmi_blocked = masked;
3974 vmx->vnmi_blocked_time = 0;
3975 }
3976 } else {
3977 vmx->nmi_known_unmasked = !masked;
3978 if (masked)
3979 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3980 GUEST_INTR_STATE_NMI);
3981 else
3982 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3983 GUEST_INTR_STATE_NMI);
3984 }
3985 }
3986
3987 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
3988 {
3989 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
3990 struct vmcs12 *vmcs12;
3991 if (to_vmx(vcpu)->nested.nested_run_pending)
3992 return 0;
3993 nested_vmx_vmexit(vcpu);
3994 vmcs12 = get_vmcs12(vcpu);
3995 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
3996 vmcs12->vm_exit_intr_info = 0;
3997 /* fall through to normal code, but now in L1, not L2 */
3998 }
3999
4000 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4001 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4002 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4003 }
4004
4005 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4006 {
4007 int ret;
4008 struct kvm_userspace_memory_region tss_mem = {
4009 .slot = TSS_PRIVATE_MEMSLOT,
4010 .guest_phys_addr = addr,
4011 .memory_size = PAGE_SIZE * 3,
4012 .flags = 0,
4013 };
4014
4015 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4016 if (ret)
4017 return ret;
4018 kvm->arch.tss_addr = addr;
4019 if (!init_rmode_tss(kvm))
4020 return -ENOMEM;
4021
4022 return 0;
4023 }
4024
4025 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4026 int vec, u32 err_code)
4027 {
4028 /*
4029 * Instruction with address size override prefix opcode 0x67
4030 * Cause the #SS fault with 0 error code in VM86 mode.
4031 */
4032 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
4033 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
4034 return 1;
4035 /*
4036 * Forward all other exceptions that are valid in real mode.
4037 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4038 * the required debugging infrastructure rework.
4039 */
4040 switch (vec) {
4041 case DB_VECTOR:
4042 if (vcpu->guest_debug &
4043 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4044 return 0;
4045 kvm_queue_exception(vcpu, vec);
4046 return 1;
4047 case BP_VECTOR:
4048 /*
4049 * Update instruction length as we may reinject the exception
4050 * from user space while in guest debugging mode.
4051 */
4052 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4053 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4054 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4055 return 0;
4056 /* fall through */
4057 case DE_VECTOR:
4058 case OF_VECTOR:
4059 case BR_VECTOR:
4060 case UD_VECTOR:
4061 case DF_VECTOR:
4062 case SS_VECTOR:
4063 case GP_VECTOR:
4064 case MF_VECTOR:
4065 kvm_queue_exception(vcpu, vec);
4066 return 1;
4067 }
4068 return 0;
4069 }
4070
4071 /*
4072 * Trigger machine check on the host. We assume all the MSRs are already set up
4073 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4074 * We pass a fake environment to the machine check handler because we want
4075 * the guest to be always treated like user space, no matter what context
4076 * it used internally.
4077 */
4078 static void kvm_machine_check(void)
4079 {
4080 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4081 struct pt_regs regs = {
4082 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4083 .flags = X86_EFLAGS_IF,
4084 };
4085
4086 do_machine_check(&regs, 0);
4087 #endif
4088 }
4089
4090 static int handle_machine_check(struct kvm_vcpu *vcpu)
4091 {
4092 /* already handled by vcpu_run */
4093 return 1;
4094 }
4095
4096 static int handle_exception(struct kvm_vcpu *vcpu)
4097 {
4098 struct vcpu_vmx *vmx = to_vmx(vcpu);
4099 struct kvm_run *kvm_run = vcpu->run;
4100 u32 intr_info, ex_no, error_code;
4101 unsigned long cr2, rip, dr6;
4102 u32 vect_info;
4103 enum emulation_result er;
4104
4105 vect_info = vmx->idt_vectoring_info;
4106 intr_info = vmx->exit_intr_info;
4107
4108 if (is_machine_check(intr_info))
4109 return handle_machine_check(vcpu);
4110
4111 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4112 !is_page_fault(intr_info)) {
4113 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4114 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4115 vcpu->run->internal.ndata = 2;
4116 vcpu->run->internal.data[0] = vect_info;
4117 vcpu->run->internal.data[1] = intr_info;
4118 return 0;
4119 }
4120
4121 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4122 return 1; /* already handled by vmx_vcpu_run() */
4123
4124 if (is_no_device(intr_info)) {
4125 vmx_fpu_activate(vcpu);
4126 return 1;
4127 }
4128
4129 if (is_invalid_opcode(intr_info)) {
4130 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4131 if (er != EMULATE_DONE)
4132 kvm_queue_exception(vcpu, UD_VECTOR);
4133 return 1;
4134 }
4135
4136 error_code = 0;
4137 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4138 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4139 if (is_page_fault(intr_info)) {
4140 /* EPT won't cause page fault directly */
4141 BUG_ON(enable_ept);
4142 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4143 trace_kvm_page_fault(cr2, error_code);
4144
4145 if (kvm_event_needs_reinjection(vcpu))
4146 kvm_mmu_unprotect_page_virt(vcpu, cr2);
4147 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4148 }
4149
4150 if (vmx->rmode.vm86_active &&
4151 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
4152 error_code)) {
4153 if (vcpu->arch.halt_request) {
4154 vcpu->arch.halt_request = 0;
4155 return kvm_emulate_halt(vcpu);
4156 }
4157 return 1;
4158 }
4159
4160 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4161 switch (ex_no) {
4162 case DB_VECTOR:
4163 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4164 if (!(vcpu->guest_debug &
4165 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4166 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4167 kvm_queue_exception(vcpu, DB_VECTOR);
4168 return 1;
4169 }
4170 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4171 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4172 /* fall through */
4173 case BP_VECTOR:
4174 /*
4175 * Update instruction length as we may reinject #BP from
4176 * user space while in guest debugging mode. Reading it for
4177 * #DB as well causes no harm, it is not used in that case.
4178 */
4179 vmx->vcpu.arch.event_exit_inst_len =
4180 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4181 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4182 rip = kvm_rip_read(vcpu);
4183 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4184 kvm_run->debug.arch.exception = ex_no;
4185 break;
4186 default:
4187 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4188 kvm_run->ex.exception = ex_no;
4189 kvm_run->ex.error_code = error_code;
4190 break;
4191 }
4192 return 0;
4193 }
4194
4195 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4196 {
4197 ++vcpu->stat.irq_exits;
4198 return 1;
4199 }
4200
4201 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4202 {
4203 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4204 return 0;
4205 }
4206
4207 static int handle_io(struct kvm_vcpu *vcpu)
4208 {
4209 unsigned long exit_qualification;
4210 int size, in, string;
4211 unsigned port;
4212
4213 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4214 string = (exit_qualification & 16) != 0;
4215 in = (exit_qualification & 8) != 0;
4216
4217 ++vcpu->stat.io_exits;
4218
4219 if (string || in)
4220 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4221
4222 port = exit_qualification >> 16;
4223 size = (exit_qualification & 7) + 1;
4224 skip_emulated_instruction(vcpu);
4225
4226 return kvm_fast_pio_out(vcpu, size, port);
4227 }
4228
4229 static void
4230 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4231 {
4232 /*
4233 * Patch in the VMCALL instruction:
4234 */
4235 hypercall[0] = 0x0f;
4236 hypercall[1] = 0x01;
4237 hypercall[2] = 0xc1;
4238 }
4239
4240 /* called to set cr0 as approriate for a mov-to-cr0 exit. */
4241 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4242 {
4243 if (to_vmx(vcpu)->nested.vmxon &&
4244 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4245 return 1;
4246
4247 if (is_guest_mode(vcpu)) {
4248 /*
4249 * We get here when L2 changed cr0 in a way that did not change
4250 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4251 * but did change L0 shadowed bits. This can currently happen
4252 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4253 * loading) while pretending to allow the guest to change it.
4254 */
4255 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4256 (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4257 return 1;
4258 vmcs_writel(CR0_READ_SHADOW, val);
4259 return 0;
4260 } else
4261 return kvm_set_cr0(vcpu, val);
4262 }
4263
4264 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4265 {
4266 if (is_guest_mode(vcpu)) {
4267 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4268 (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4269 return 1;
4270 vmcs_writel(CR4_READ_SHADOW, val);
4271 return 0;
4272 } else
4273 return kvm_set_cr4(vcpu, val);
4274 }
4275
4276 /* called to set cr0 as approriate for clts instruction exit. */
4277 static void handle_clts(struct kvm_vcpu *vcpu)
4278 {
4279 if (is_guest_mode(vcpu)) {
4280 /*
4281 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4282 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4283 * just pretend it's off (also in arch.cr0 for fpu_activate).
4284 */
4285 vmcs_writel(CR0_READ_SHADOW,
4286 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4287 vcpu->arch.cr0 &= ~X86_CR0_TS;
4288 } else
4289 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4290 }
4291
4292 static int handle_cr(struct kvm_vcpu *vcpu)
4293 {
4294 unsigned long exit_qualification, val;
4295 int cr;
4296 int reg;
4297 int err;
4298
4299 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4300 cr = exit_qualification & 15;
4301 reg = (exit_qualification >> 8) & 15;
4302 switch ((exit_qualification >> 4) & 3) {
4303 case 0: /* mov to cr */
4304 val = kvm_register_read(vcpu, reg);
4305 trace_kvm_cr_write(cr, val);
4306 switch (cr) {
4307 case 0:
4308 err = handle_set_cr0(vcpu, val);
4309 kvm_complete_insn_gp(vcpu, err);
4310 return 1;
4311 case 3:
4312 err = kvm_set_cr3(vcpu, val);
4313 kvm_complete_insn_gp(vcpu, err);
4314 return 1;
4315 case 4:
4316 err = handle_set_cr4(vcpu, val);
4317 kvm_complete_insn_gp(vcpu, err);
4318 return 1;
4319 case 8: {
4320 u8 cr8_prev = kvm_get_cr8(vcpu);
4321 u8 cr8 = kvm_register_read(vcpu, reg);
4322 err = kvm_set_cr8(vcpu, cr8);
4323 kvm_complete_insn_gp(vcpu, err);
4324 if (irqchip_in_kernel(vcpu->kvm))
4325 return 1;
4326 if (cr8_prev <= cr8)
4327 return 1;
4328 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4329 return 0;
4330 }
4331 };
4332 break;
4333 case 2: /* clts */
4334 handle_clts(vcpu);
4335 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4336 skip_emulated_instruction(vcpu);
4337 vmx_fpu_activate(vcpu);
4338 return 1;
4339 case 1: /*mov from cr*/
4340 switch (cr) {
4341 case 3:
4342 val = kvm_read_cr3(vcpu);
4343 kvm_register_write(vcpu, reg, val);
4344 trace_kvm_cr_read(cr, val);
4345 skip_emulated_instruction(vcpu);
4346 return 1;
4347 case 8:
4348 val = kvm_get_cr8(vcpu);
4349 kvm_register_write(vcpu, reg, val);
4350 trace_kvm_cr_read(cr, val);
4351 skip_emulated_instruction(vcpu);
4352 return 1;
4353 }
4354 break;
4355 case 3: /* lmsw */
4356 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4357 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4358 kvm_lmsw(vcpu, val);
4359
4360 skip_emulated_instruction(vcpu);
4361 return 1;
4362 default:
4363 break;
4364 }
4365 vcpu->run->exit_reason = 0;
4366 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4367 (int)(exit_qualification >> 4) & 3, cr);
4368 return 0;
4369 }
4370
4371 static int handle_dr(struct kvm_vcpu *vcpu)
4372 {
4373 unsigned long exit_qualification;
4374 int dr, reg;
4375
4376 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4377 if (!kvm_require_cpl(vcpu, 0))
4378 return 1;
4379 dr = vmcs_readl(GUEST_DR7);
4380 if (dr & DR7_GD) {
4381 /*
4382 * As the vm-exit takes precedence over the debug trap, we
4383 * need to emulate the latter, either for the host or the
4384 * guest debugging itself.
4385 */
4386 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4387 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4388 vcpu->run->debug.arch.dr7 = dr;
4389 vcpu->run->debug.arch.pc =
4390 vmcs_readl(GUEST_CS_BASE) +
4391 vmcs_readl(GUEST_RIP);
4392 vcpu->run->debug.arch.exception = DB_VECTOR;
4393 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4394 return 0;
4395 } else {
4396 vcpu->arch.dr7 &= ~DR7_GD;
4397 vcpu->arch.dr6 |= DR6_BD;
4398 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4399 kvm_queue_exception(vcpu, DB_VECTOR);
4400 return 1;
4401 }
4402 }
4403
4404 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4405 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4406 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4407 if (exit_qualification & TYPE_MOV_FROM_DR) {
4408 unsigned long val;
4409 if (!kvm_get_dr(vcpu, dr, &val))
4410 kvm_register_write(vcpu, reg, val);
4411 } else
4412 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4413 skip_emulated_instruction(vcpu);
4414 return 1;
4415 }
4416
4417 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4418 {
4419 vmcs_writel(GUEST_DR7, val);
4420 }
4421
4422 static int handle_cpuid(struct kvm_vcpu *vcpu)
4423 {
4424 kvm_emulate_cpuid(vcpu);
4425 return 1;
4426 }
4427
4428 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4429 {
4430 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4431 u64 data;
4432
4433 if (vmx_get_msr(vcpu, ecx, &data)) {
4434 trace_kvm_msr_read_ex(ecx);
4435 kvm_inject_gp(vcpu, 0);
4436 return 1;
4437 }
4438
4439 trace_kvm_msr_read(ecx, data);
4440
4441 /* FIXME: handling of bits 32:63 of rax, rdx */
4442 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4443 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4444 skip_emulated_instruction(vcpu);
4445 return 1;
4446 }
4447
4448 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4449 {
4450 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4451 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4452 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4453
4454 if (vmx_set_msr(vcpu, ecx, data) != 0) {
4455 trace_kvm_msr_write_ex(ecx, data);
4456 kvm_inject_gp(vcpu, 0);
4457 return 1;
4458 }
4459
4460 trace_kvm_msr_write(ecx, data);
4461 skip_emulated_instruction(vcpu);
4462 return 1;
4463 }
4464
4465 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4466 {
4467 kvm_make_request(KVM_REQ_EVENT, vcpu);
4468 return 1;
4469 }
4470
4471 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4472 {
4473 u32 cpu_based_vm_exec_control;
4474
4475 /* clear pending irq */
4476 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4477 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4478 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4479
4480 kvm_make_request(KVM_REQ_EVENT, vcpu);
4481
4482 ++vcpu->stat.irq_window_exits;
4483
4484 /*
4485 * If the user space waits to inject interrupts, exit as soon as
4486 * possible
4487 */
4488 if (!irqchip_in_kernel(vcpu->kvm) &&
4489 vcpu->run->request_interrupt_window &&
4490 !kvm_cpu_has_interrupt(vcpu)) {
4491 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4492 return 0;
4493 }
4494 return 1;
4495 }
4496
4497 static int handle_halt(struct kvm_vcpu *vcpu)
4498 {
4499 skip_emulated_instruction(vcpu);
4500 return kvm_emulate_halt(vcpu);
4501 }
4502
4503 static int handle_vmcall(struct kvm_vcpu *vcpu)
4504 {
4505 skip_emulated_instruction(vcpu);
4506 kvm_emulate_hypercall(vcpu);
4507 return 1;
4508 }
4509
4510 static int handle_invd(struct kvm_vcpu *vcpu)
4511 {
4512 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4513 }
4514
4515 static int handle_invlpg(struct kvm_vcpu *vcpu)
4516 {
4517 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4518
4519 kvm_mmu_invlpg(vcpu, exit_qualification);
4520 skip_emulated_instruction(vcpu);
4521 return 1;
4522 }
4523
4524 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4525 {
4526 skip_emulated_instruction(vcpu);
4527 kvm_emulate_wbinvd(vcpu);
4528 return 1;
4529 }
4530
4531 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4532 {
4533 u64 new_bv = kvm_read_edx_eax(vcpu);
4534 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4535
4536 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4537 skip_emulated_instruction(vcpu);
4538 return 1;
4539 }
4540
4541 static int handle_apic_access(struct kvm_vcpu *vcpu)
4542 {
4543 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4544 }
4545
4546 static int handle_task_switch(struct kvm_vcpu *vcpu)
4547 {
4548 struct vcpu_vmx *vmx = to_vmx(vcpu);
4549 unsigned long exit_qualification;
4550 bool has_error_code = false;
4551 u32 error_code = 0;
4552 u16 tss_selector;
4553 int reason, type, idt_v;
4554
4555 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4556 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4557
4558 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4559
4560 reason = (u32)exit_qualification >> 30;
4561 if (reason == TASK_SWITCH_GATE && idt_v) {
4562 switch (type) {
4563 case INTR_TYPE_NMI_INTR:
4564 vcpu->arch.nmi_injected = false;
4565 vmx_set_nmi_mask(vcpu, true);
4566 break;
4567 case INTR_TYPE_EXT_INTR:
4568 case INTR_TYPE_SOFT_INTR:
4569 kvm_clear_interrupt_queue(vcpu);
4570 break;
4571 case INTR_TYPE_HARD_EXCEPTION:
4572 if (vmx->idt_vectoring_info &
4573 VECTORING_INFO_DELIVER_CODE_MASK) {
4574 has_error_code = true;
4575 error_code =
4576 vmcs_read32(IDT_VECTORING_ERROR_CODE);
4577 }
4578 /* fall through */
4579 case INTR_TYPE_SOFT_EXCEPTION:
4580 kvm_clear_exception_queue(vcpu);
4581 break;
4582 default:
4583 break;
4584 }
4585 }
4586 tss_selector = exit_qualification;
4587
4588 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4589 type != INTR_TYPE_EXT_INTR &&
4590 type != INTR_TYPE_NMI_INTR))
4591 skip_emulated_instruction(vcpu);
4592
4593 if (kvm_task_switch(vcpu, tss_selector, reason,
4594 has_error_code, error_code) == EMULATE_FAIL) {
4595 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4596 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4597 vcpu->run->internal.ndata = 0;
4598 return 0;
4599 }
4600
4601 /* clear all local breakpoint enable flags */
4602 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4603
4604 /*
4605 * TODO: What about debug traps on tss switch?
4606 * Are we supposed to inject them and update dr6?
4607 */
4608
4609 return 1;
4610 }
4611
4612 static int handle_ept_violation(struct kvm_vcpu *vcpu)
4613 {
4614 unsigned long exit_qualification;
4615 gpa_t gpa;
4616 int gla_validity;
4617
4618 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4619
4620 if (exit_qualification & (1 << 6)) {
4621 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
4622 return -EINVAL;
4623 }
4624
4625 gla_validity = (exit_qualification >> 7) & 0x3;
4626 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4627 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4628 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4629 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
4630 vmcs_readl(GUEST_LINEAR_ADDRESS));
4631 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4632 (long unsigned int)exit_qualification);
4633 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4634 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
4635 return 0;
4636 }
4637
4638 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4639 trace_kvm_page_fault(gpa, exit_qualification);
4640 return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
4641 }
4642
4643 static u64 ept_rsvd_mask(u64 spte, int level)
4644 {
4645 int i;
4646 u64 mask = 0;
4647
4648 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4649 mask |= (1ULL << i);
4650
4651 if (level > 2)
4652 /* bits 7:3 reserved */
4653 mask |= 0xf8;
4654 else if (level == 2) {
4655 if (spte & (1ULL << 7))
4656 /* 2MB ref, bits 20:12 reserved */
4657 mask |= 0x1ff000;
4658 else
4659 /* bits 6:3 reserved */
4660 mask |= 0x78;
4661 }
4662
4663 return mask;
4664 }
4665
4666 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4667 int level)
4668 {
4669 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4670
4671 /* 010b (write-only) */
4672 WARN_ON((spte & 0x7) == 0x2);
4673
4674 /* 110b (write/execute) */
4675 WARN_ON((spte & 0x7) == 0x6);
4676
4677 /* 100b (execute-only) and value not supported by logical processor */
4678 if (!cpu_has_vmx_ept_execute_only())
4679 WARN_ON((spte & 0x7) == 0x4);
4680
4681 /* not 000b */
4682 if ((spte & 0x7)) {
4683 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4684
4685 if (rsvd_bits != 0) {
4686 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4687 __func__, rsvd_bits);
4688 WARN_ON(1);
4689 }
4690
4691 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4692 u64 ept_mem_type = (spte & 0x38) >> 3;
4693
4694 if (ept_mem_type == 2 || ept_mem_type == 3 ||
4695 ept_mem_type == 7) {
4696 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4697 __func__, ept_mem_type);
4698 WARN_ON(1);
4699 }
4700 }
4701 }
4702 }
4703
4704 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
4705 {
4706 u64 sptes[4];
4707 int nr_sptes, i, ret;
4708 gpa_t gpa;
4709
4710 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4711
4712 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4713 if (likely(ret == 1))
4714 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4715 EMULATE_DONE;
4716 if (unlikely(!ret))
4717 return 1;
4718
4719 /* It is the real ept misconfig */
4720 printk(KERN_ERR "EPT: Misconfiguration.\n");
4721 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4722
4723 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4724
4725 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4726 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4727
4728 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4729 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
4730
4731 return 0;
4732 }
4733
4734 static int handle_nmi_window(struct kvm_vcpu *vcpu)
4735 {
4736 u32 cpu_based_vm_exec_control;
4737
4738 /* clear pending NMI */
4739 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4740 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4741 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4742 ++vcpu->stat.nmi_window_exits;
4743 kvm_make_request(KVM_REQ_EVENT, vcpu);
4744
4745 return 1;
4746 }
4747
4748 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
4749 {
4750 struct vcpu_vmx *vmx = to_vmx(vcpu);
4751 enum emulation_result err = EMULATE_DONE;
4752 int ret = 1;
4753 u32 cpu_exec_ctrl;
4754 bool intr_window_requested;
4755
4756 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4757 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
4758
4759 while (!guest_state_valid(vcpu)) {
4760 if (intr_window_requested
4761 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
4762 return handle_interrupt_window(&vmx->vcpu);
4763
4764 err = emulate_instruction(vcpu, 0);
4765
4766 if (err == EMULATE_DO_MMIO) {
4767 ret = 0;
4768 goto out;
4769 }
4770
4771 if (err != EMULATE_DONE)
4772 return 0;
4773
4774 if (signal_pending(current))
4775 goto out;
4776 if (need_resched())
4777 schedule();
4778 }
4779
4780 vmx->emulation_required = 0;
4781 out:
4782 return ret;
4783 }
4784
4785 /*
4786 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4787 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4788 */
4789 static int handle_pause(struct kvm_vcpu *vcpu)
4790 {
4791 skip_emulated_instruction(vcpu);
4792 kvm_vcpu_on_spin(vcpu);
4793
4794 return 1;
4795 }
4796
4797 static int handle_invalid_op(struct kvm_vcpu *vcpu)
4798 {
4799 kvm_queue_exception(vcpu, UD_VECTOR);
4800 return 1;
4801 }
4802
4803 /*
4804 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
4805 * We could reuse a single VMCS for all the L2 guests, but we also want the
4806 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
4807 * allows keeping them loaded on the processor, and in the future will allow
4808 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
4809 * every entry if they never change.
4810 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
4811 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
4812 *
4813 * The following functions allocate and free a vmcs02 in this pool.
4814 */
4815
4816 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
4817 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
4818 {
4819 struct vmcs02_list *item;
4820 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4821 if (item->vmptr == vmx->nested.current_vmptr) {
4822 list_move(&item->list, &vmx->nested.vmcs02_pool);
4823 return &item->vmcs02;
4824 }
4825
4826 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
4827 /* Recycle the least recently used VMCS. */
4828 item = list_entry(vmx->nested.vmcs02_pool.prev,
4829 struct vmcs02_list, list);
4830 item->vmptr = vmx->nested.current_vmptr;
4831 list_move(&item->list, &vmx->nested.vmcs02_pool);
4832 return &item->vmcs02;
4833 }
4834
4835 /* Create a new VMCS */
4836 item = (struct vmcs02_list *)
4837 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
4838 if (!item)
4839 return NULL;
4840 item->vmcs02.vmcs = alloc_vmcs();
4841 if (!item->vmcs02.vmcs) {
4842 kfree(item);
4843 return NULL;
4844 }
4845 loaded_vmcs_init(&item->vmcs02);
4846 item->vmptr = vmx->nested.current_vmptr;
4847 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
4848 vmx->nested.vmcs02_num++;
4849 return &item->vmcs02;
4850 }
4851
4852 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
4853 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
4854 {
4855 struct vmcs02_list *item;
4856 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4857 if (item->vmptr == vmptr) {
4858 free_loaded_vmcs(&item->vmcs02);
4859 list_del(&item->list);
4860 kfree(item);
4861 vmx->nested.vmcs02_num--;
4862 return;
4863 }
4864 }
4865
4866 /*
4867 * Free all VMCSs saved for this vcpu, except the one pointed by
4868 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
4869 * currently used, if running L2), and vmcs01 when running L2.
4870 */
4871 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
4872 {
4873 struct vmcs02_list *item, *n;
4874 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4875 if (vmx->loaded_vmcs != &item->vmcs02)
4876 free_loaded_vmcs(&item->vmcs02);
4877 list_del(&item->list);
4878 kfree(item);
4879 }
4880 vmx->nested.vmcs02_num = 0;
4881
4882 if (vmx->loaded_vmcs != &vmx->vmcs01)
4883 free_loaded_vmcs(&vmx->vmcs01);
4884 }
4885
4886 /*
4887 * Emulate the VMXON instruction.
4888 * Currently, we just remember that VMX is active, and do not save or even
4889 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
4890 * do not currently need to store anything in that guest-allocated memory
4891 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
4892 * argument is different from the VMXON pointer (which the spec says they do).
4893 */
4894 static int handle_vmon(struct kvm_vcpu *vcpu)
4895 {
4896 struct kvm_segment cs;
4897 struct vcpu_vmx *vmx = to_vmx(vcpu);
4898
4899 /* The Intel VMX Instruction Reference lists a bunch of bits that
4900 * are prerequisite to running VMXON, most notably cr4.VMXE must be
4901 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
4902 * Otherwise, we should fail with #UD. We test these now:
4903 */
4904 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
4905 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
4906 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4907 kvm_queue_exception(vcpu, UD_VECTOR);
4908 return 1;
4909 }
4910
4911 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4912 if (is_long_mode(vcpu) && !cs.l) {
4913 kvm_queue_exception(vcpu, UD_VECTOR);
4914 return 1;
4915 }
4916
4917 if (vmx_get_cpl(vcpu)) {
4918 kvm_inject_gp(vcpu, 0);
4919 return 1;
4920 }
4921
4922 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
4923 vmx->nested.vmcs02_num = 0;
4924
4925 vmx->nested.vmxon = true;
4926
4927 skip_emulated_instruction(vcpu);
4928 return 1;
4929 }
4930
4931 /*
4932 * Intel's VMX Instruction Reference specifies a common set of prerequisites
4933 * for running VMX instructions (except VMXON, whose prerequisites are
4934 * slightly different). It also specifies what exception to inject otherwise.
4935 */
4936 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
4937 {
4938 struct kvm_segment cs;
4939 struct vcpu_vmx *vmx = to_vmx(vcpu);
4940
4941 if (!vmx->nested.vmxon) {
4942 kvm_queue_exception(vcpu, UD_VECTOR);
4943 return 0;
4944 }
4945
4946 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4947 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
4948 (is_long_mode(vcpu) && !cs.l)) {
4949 kvm_queue_exception(vcpu, UD_VECTOR);
4950 return 0;
4951 }
4952
4953 if (vmx_get_cpl(vcpu)) {
4954 kvm_inject_gp(vcpu, 0);
4955 return 0;
4956 }
4957
4958 return 1;
4959 }
4960
4961 /*
4962 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
4963 * just stops using VMX.
4964 */
4965 static void free_nested(struct vcpu_vmx *vmx)
4966 {
4967 if (!vmx->nested.vmxon)
4968 return;
4969 vmx->nested.vmxon = false;
4970 if (vmx->nested.current_vmptr != -1ull) {
4971 kunmap(vmx->nested.current_vmcs12_page);
4972 nested_release_page(vmx->nested.current_vmcs12_page);
4973 vmx->nested.current_vmptr = -1ull;
4974 vmx->nested.current_vmcs12 = NULL;
4975 }
4976 /* Unpin physical memory we referred to in current vmcs02 */
4977 if (vmx->nested.apic_access_page) {
4978 nested_release_page(vmx->nested.apic_access_page);
4979 vmx->nested.apic_access_page = 0;
4980 }
4981
4982 nested_free_all_saved_vmcss(vmx);
4983 }
4984
4985 /* Emulate the VMXOFF instruction */
4986 static int handle_vmoff(struct kvm_vcpu *vcpu)
4987 {
4988 if (!nested_vmx_check_permission(vcpu))
4989 return 1;
4990 free_nested(to_vmx(vcpu));
4991 skip_emulated_instruction(vcpu);
4992 return 1;
4993 }
4994
4995 /*
4996 * Decode the memory-address operand of a vmx instruction, as recorded on an
4997 * exit caused by such an instruction (run by a guest hypervisor).
4998 * On success, returns 0. When the operand is invalid, returns 1 and throws
4999 * #UD or #GP.
5000 */
5001 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5002 unsigned long exit_qualification,
5003 u32 vmx_instruction_info, gva_t *ret)
5004 {
5005 /*
5006 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5007 * Execution", on an exit, vmx_instruction_info holds most of the
5008 * addressing components of the operand. Only the displacement part
5009 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5010 * For how an actual address is calculated from all these components,
5011 * refer to Vol. 1, "Operand Addressing".
5012 */
5013 int scaling = vmx_instruction_info & 3;
5014 int addr_size = (vmx_instruction_info >> 7) & 7;
5015 bool is_reg = vmx_instruction_info & (1u << 10);
5016 int seg_reg = (vmx_instruction_info >> 15) & 7;
5017 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5018 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5019 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5020 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5021
5022 if (is_reg) {
5023 kvm_queue_exception(vcpu, UD_VECTOR);
5024 return 1;
5025 }
5026
5027 /* Addr = segment_base + offset */
5028 /* offset = base + [index * scale] + displacement */
5029 *ret = vmx_get_segment_base(vcpu, seg_reg);
5030 if (base_is_valid)
5031 *ret += kvm_register_read(vcpu, base_reg);
5032 if (index_is_valid)
5033 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5034 *ret += exit_qualification; /* holds the displacement */
5035
5036 if (addr_size == 1) /* 32 bit */
5037 *ret &= 0xffffffff;
5038
5039 /*
5040 * TODO: throw #GP (and return 1) in various cases that the VM*
5041 * instructions require it - e.g., offset beyond segment limit,
5042 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5043 * address, and so on. Currently these are not checked.
5044 */
5045 return 0;
5046 }
5047
5048 /*
5049 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5050 * set the success or error code of an emulated VMX instruction, as specified
5051 * by Vol 2B, VMX Instruction Reference, "Conventions".
5052 */
5053 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5054 {
5055 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5056 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5057 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5058 }
5059
5060 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5061 {
5062 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5063 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5064 X86_EFLAGS_SF | X86_EFLAGS_OF))
5065 | X86_EFLAGS_CF);
5066 }
5067
5068 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5069 u32 vm_instruction_error)
5070 {
5071 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5072 /*
5073 * failValid writes the error number to the current VMCS, which
5074 * can't be done there isn't a current VMCS.
5075 */
5076 nested_vmx_failInvalid(vcpu);
5077 return;
5078 }
5079 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5080 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5081 X86_EFLAGS_SF | X86_EFLAGS_OF))
5082 | X86_EFLAGS_ZF);
5083 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5084 }
5085
5086 /* Emulate the VMCLEAR instruction */
5087 static int handle_vmclear(struct kvm_vcpu *vcpu)
5088 {
5089 struct vcpu_vmx *vmx = to_vmx(vcpu);
5090 gva_t gva;
5091 gpa_t vmptr;
5092 struct vmcs12 *vmcs12;
5093 struct page *page;
5094 struct x86_exception e;
5095
5096 if (!nested_vmx_check_permission(vcpu))
5097 return 1;
5098
5099 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5100 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5101 return 1;
5102
5103 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5104 sizeof(vmptr), &e)) {
5105 kvm_inject_page_fault(vcpu, &e);
5106 return 1;
5107 }
5108
5109 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5110 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5111 skip_emulated_instruction(vcpu);
5112 return 1;
5113 }
5114
5115 if (vmptr == vmx->nested.current_vmptr) {
5116 kunmap(vmx->nested.current_vmcs12_page);
5117 nested_release_page(vmx->nested.current_vmcs12_page);
5118 vmx->nested.current_vmptr = -1ull;
5119 vmx->nested.current_vmcs12 = NULL;
5120 }
5121
5122 page = nested_get_page(vcpu, vmptr);
5123 if (page == NULL) {
5124 /*
5125 * For accurate processor emulation, VMCLEAR beyond available
5126 * physical memory should do nothing at all. However, it is
5127 * possible that a nested vmx bug, not a guest hypervisor bug,
5128 * resulted in this case, so let's shut down before doing any
5129 * more damage:
5130 */
5131 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5132 return 1;
5133 }
5134 vmcs12 = kmap(page);
5135 vmcs12->launch_state = 0;
5136 kunmap(page);
5137 nested_release_page(page);
5138
5139 nested_free_vmcs02(vmx, vmptr);
5140
5141 skip_emulated_instruction(vcpu);
5142 nested_vmx_succeed(vcpu);
5143 return 1;
5144 }
5145
5146 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5147
5148 /* Emulate the VMLAUNCH instruction */
5149 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5150 {
5151 return nested_vmx_run(vcpu, true);
5152 }
5153
5154 /* Emulate the VMRESUME instruction */
5155 static int handle_vmresume(struct kvm_vcpu *vcpu)
5156 {
5157
5158 return nested_vmx_run(vcpu, false);
5159 }
5160
5161 enum vmcs_field_type {
5162 VMCS_FIELD_TYPE_U16 = 0,
5163 VMCS_FIELD_TYPE_U64 = 1,
5164 VMCS_FIELD_TYPE_U32 = 2,
5165 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5166 };
5167
5168 static inline int vmcs_field_type(unsigned long field)
5169 {
5170 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5171 return VMCS_FIELD_TYPE_U32;
5172 return (field >> 13) & 0x3 ;
5173 }
5174
5175 static inline int vmcs_field_readonly(unsigned long field)
5176 {
5177 return (((field >> 10) & 0x3) == 1);
5178 }
5179
5180 /*
5181 * Read a vmcs12 field. Since these can have varying lengths and we return
5182 * one type, we chose the biggest type (u64) and zero-extend the return value
5183 * to that size. Note that the caller, handle_vmread, might need to use only
5184 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5185 * 64-bit fields are to be returned).
5186 */
5187 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5188 unsigned long field, u64 *ret)
5189 {
5190 short offset = vmcs_field_to_offset(field);
5191 char *p;
5192
5193 if (offset < 0)
5194 return 0;
5195
5196 p = ((char *)(get_vmcs12(vcpu))) + offset;
5197
5198 switch (vmcs_field_type(field)) {
5199 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5200 *ret = *((natural_width *)p);
5201 return 1;
5202 case VMCS_FIELD_TYPE_U16:
5203 *ret = *((u16 *)p);
5204 return 1;
5205 case VMCS_FIELD_TYPE_U32:
5206 *ret = *((u32 *)p);
5207 return 1;
5208 case VMCS_FIELD_TYPE_U64:
5209 *ret = *((u64 *)p);
5210 return 1;
5211 default:
5212 return 0; /* can never happen. */
5213 }
5214 }
5215
5216 /*
5217 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5218 * used before) all generate the same failure when it is missing.
5219 */
5220 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5221 {
5222 struct vcpu_vmx *vmx = to_vmx(vcpu);
5223 if (vmx->nested.current_vmptr == -1ull) {
5224 nested_vmx_failInvalid(vcpu);
5225 skip_emulated_instruction(vcpu);
5226 return 0;
5227 }
5228 return 1;
5229 }
5230
5231 static int handle_vmread(struct kvm_vcpu *vcpu)
5232 {
5233 unsigned long field;
5234 u64 field_value;
5235 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5236 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5237 gva_t gva = 0;
5238
5239 if (!nested_vmx_check_permission(vcpu) ||
5240 !nested_vmx_check_vmcs12(vcpu))
5241 return 1;
5242
5243 /* Decode instruction info and find the field to read */
5244 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5245 /* Read the field, zero-extended to a u64 field_value */
5246 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5247 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5248 skip_emulated_instruction(vcpu);
5249 return 1;
5250 }
5251 /*
5252 * Now copy part of this value to register or memory, as requested.
5253 * Note that the number of bits actually copied is 32 or 64 depending
5254 * on the guest's mode (32 or 64 bit), not on the given field's length.
5255 */
5256 if (vmx_instruction_info & (1u << 10)) {
5257 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5258 field_value);
5259 } else {
5260 if (get_vmx_mem_address(vcpu, exit_qualification,
5261 vmx_instruction_info, &gva))
5262 return 1;
5263 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5264 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5265 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5266 }
5267
5268 nested_vmx_succeed(vcpu);
5269 skip_emulated_instruction(vcpu);
5270 return 1;
5271 }
5272
5273
5274 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5275 {
5276 unsigned long field;
5277 gva_t gva;
5278 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5279 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5280 char *p;
5281 short offset;
5282 /* The value to write might be 32 or 64 bits, depending on L1's long
5283 * mode, and eventually we need to write that into a field of several
5284 * possible lengths. The code below first zero-extends the value to 64
5285 * bit (field_value), and then copies only the approriate number of
5286 * bits into the vmcs12 field.
5287 */
5288 u64 field_value = 0;
5289 struct x86_exception e;
5290
5291 if (!nested_vmx_check_permission(vcpu) ||
5292 !nested_vmx_check_vmcs12(vcpu))
5293 return 1;
5294
5295 if (vmx_instruction_info & (1u << 10))
5296 field_value = kvm_register_read(vcpu,
5297 (((vmx_instruction_info) >> 3) & 0xf));
5298 else {
5299 if (get_vmx_mem_address(vcpu, exit_qualification,
5300 vmx_instruction_info, &gva))
5301 return 1;
5302 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5303 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5304 kvm_inject_page_fault(vcpu, &e);
5305 return 1;
5306 }
5307 }
5308
5309
5310 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5311 if (vmcs_field_readonly(field)) {
5312 nested_vmx_failValid(vcpu,
5313 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5314 skip_emulated_instruction(vcpu);
5315 return 1;
5316 }
5317
5318 offset = vmcs_field_to_offset(field);
5319 if (offset < 0) {
5320 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5321 skip_emulated_instruction(vcpu);
5322 return 1;
5323 }
5324 p = ((char *) get_vmcs12(vcpu)) + offset;
5325
5326 switch (vmcs_field_type(field)) {
5327 case VMCS_FIELD_TYPE_U16:
5328 *(u16 *)p = field_value;
5329 break;
5330 case VMCS_FIELD_TYPE_U32:
5331 *(u32 *)p = field_value;
5332 break;
5333 case VMCS_FIELD_TYPE_U64:
5334 *(u64 *)p = field_value;
5335 break;
5336 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5337 *(natural_width *)p = field_value;
5338 break;
5339 default:
5340 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5341 skip_emulated_instruction(vcpu);
5342 return 1;
5343 }
5344
5345 nested_vmx_succeed(vcpu);
5346 skip_emulated_instruction(vcpu);
5347 return 1;
5348 }
5349
5350 /* Emulate the VMPTRLD instruction */
5351 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5352 {
5353 struct vcpu_vmx *vmx = to_vmx(vcpu);
5354 gva_t gva;
5355 gpa_t vmptr;
5356 struct x86_exception e;
5357
5358 if (!nested_vmx_check_permission(vcpu))
5359 return 1;
5360
5361 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5362 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5363 return 1;
5364
5365 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5366 sizeof(vmptr), &e)) {
5367 kvm_inject_page_fault(vcpu, &e);
5368 return 1;
5369 }
5370
5371 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5372 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5373 skip_emulated_instruction(vcpu);
5374 return 1;
5375 }
5376
5377 if (vmx->nested.current_vmptr != vmptr) {
5378 struct vmcs12 *new_vmcs12;
5379 struct page *page;
5380 page = nested_get_page(vcpu, vmptr);
5381 if (page == NULL) {
5382 nested_vmx_failInvalid(vcpu);
5383 skip_emulated_instruction(vcpu);
5384 return 1;
5385 }
5386 new_vmcs12 = kmap(page);
5387 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5388 kunmap(page);
5389 nested_release_page_clean(page);
5390 nested_vmx_failValid(vcpu,
5391 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5392 skip_emulated_instruction(vcpu);
5393 return 1;
5394 }
5395 if (vmx->nested.current_vmptr != -1ull) {
5396 kunmap(vmx->nested.current_vmcs12_page);
5397 nested_release_page(vmx->nested.current_vmcs12_page);
5398 }
5399
5400 vmx->nested.current_vmptr = vmptr;
5401 vmx->nested.current_vmcs12 = new_vmcs12;
5402 vmx->nested.current_vmcs12_page = page;
5403 }
5404
5405 nested_vmx_succeed(vcpu);
5406 skip_emulated_instruction(vcpu);
5407 return 1;
5408 }
5409
5410 /* Emulate the VMPTRST instruction */
5411 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5412 {
5413 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5414 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5415 gva_t vmcs_gva;
5416 struct x86_exception e;
5417
5418 if (!nested_vmx_check_permission(vcpu))
5419 return 1;
5420
5421 if (get_vmx_mem_address(vcpu, exit_qualification,
5422 vmx_instruction_info, &vmcs_gva))
5423 return 1;
5424 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5425 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5426 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5427 sizeof(u64), &e)) {
5428 kvm_inject_page_fault(vcpu, &e);
5429 return 1;
5430 }
5431 nested_vmx_succeed(vcpu);
5432 skip_emulated_instruction(vcpu);
5433 return 1;
5434 }
5435
5436 /*
5437 * The exit handlers return 1 if the exit was handled fully and guest execution
5438 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5439 * to be done to userspace and return 0.
5440 */
5441 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5442 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5443 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5444 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5445 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5446 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5447 [EXIT_REASON_CR_ACCESS] = handle_cr,
5448 [EXIT_REASON_DR_ACCESS] = handle_dr,
5449 [EXIT_REASON_CPUID] = handle_cpuid,
5450 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5451 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5452 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5453 [EXIT_REASON_HLT] = handle_halt,
5454 [EXIT_REASON_INVD] = handle_invd,
5455 [EXIT_REASON_INVLPG] = handle_invlpg,
5456 [EXIT_REASON_VMCALL] = handle_vmcall,
5457 [EXIT_REASON_VMCLEAR] = handle_vmclear,
5458 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
5459 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
5460 [EXIT_REASON_VMPTRST] = handle_vmptrst,
5461 [EXIT_REASON_VMREAD] = handle_vmread,
5462 [EXIT_REASON_VMRESUME] = handle_vmresume,
5463 [EXIT_REASON_VMWRITE] = handle_vmwrite,
5464 [EXIT_REASON_VMOFF] = handle_vmoff,
5465 [EXIT_REASON_VMON] = handle_vmon,
5466 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5467 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5468 [EXIT_REASON_WBINVD] = handle_wbinvd,
5469 [EXIT_REASON_XSETBV] = handle_xsetbv,
5470 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5471 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5472 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5473 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5474 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5475 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5476 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
5477 };
5478
5479 static const int kvm_vmx_max_exit_handlers =
5480 ARRAY_SIZE(kvm_vmx_exit_handlers);
5481
5482 /*
5483 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5484 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5485 * disinterest in the current event (read or write a specific MSR) by using an
5486 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5487 */
5488 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5489 struct vmcs12 *vmcs12, u32 exit_reason)
5490 {
5491 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5492 gpa_t bitmap;
5493
5494 if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5495 return 1;
5496
5497 /*
5498 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5499 * for the four combinations of read/write and low/high MSR numbers.
5500 * First we need to figure out which of the four to use:
5501 */
5502 bitmap = vmcs12->msr_bitmap;
5503 if (exit_reason == EXIT_REASON_MSR_WRITE)
5504 bitmap += 2048;
5505 if (msr_index >= 0xc0000000) {
5506 msr_index -= 0xc0000000;
5507 bitmap += 1024;
5508 }
5509
5510 /* Then read the msr_index'th bit from this bitmap: */
5511 if (msr_index < 1024*8) {
5512 unsigned char b;
5513 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5514 return 1 & (b >> (msr_index & 7));
5515 } else
5516 return 1; /* let L1 handle the wrong parameter */
5517 }
5518
5519 /*
5520 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5521 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5522 * intercept (via guest_host_mask etc.) the current event.
5523 */
5524 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5525 struct vmcs12 *vmcs12)
5526 {
5527 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5528 int cr = exit_qualification & 15;
5529 int reg = (exit_qualification >> 8) & 15;
5530 unsigned long val = kvm_register_read(vcpu, reg);
5531
5532 switch ((exit_qualification >> 4) & 3) {
5533 case 0: /* mov to cr */
5534 switch (cr) {
5535 case 0:
5536 if (vmcs12->cr0_guest_host_mask &
5537 (val ^ vmcs12->cr0_read_shadow))
5538 return 1;
5539 break;
5540 case 3:
5541 if ((vmcs12->cr3_target_count >= 1 &&
5542 vmcs12->cr3_target_value0 == val) ||
5543 (vmcs12->cr3_target_count >= 2 &&
5544 vmcs12->cr3_target_value1 == val) ||
5545 (vmcs12->cr3_target_count >= 3 &&
5546 vmcs12->cr3_target_value2 == val) ||
5547 (vmcs12->cr3_target_count >= 4 &&
5548 vmcs12->cr3_target_value3 == val))
5549 return 0;
5550 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5551 return 1;
5552 break;
5553 case 4:
5554 if (vmcs12->cr4_guest_host_mask &
5555 (vmcs12->cr4_read_shadow ^ val))
5556 return 1;
5557 break;
5558 case 8:
5559 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5560 return 1;
5561 break;
5562 }
5563 break;
5564 case 2: /* clts */
5565 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5566 (vmcs12->cr0_read_shadow & X86_CR0_TS))
5567 return 1;
5568 break;
5569 case 1: /* mov from cr */
5570 switch (cr) {
5571 case 3:
5572 if (vmcs12->cpu_based_vm_exec_control &
5573 CPU_BASED_CR3_STORE_EXITING)
5574 return 1;
5575 break;
5576 case 8:
5577 if (vmcs12->cpu_based_vm_exec_control &
5578 CPU_BASED_CR8_STORE_EXITING)
5579 return 1;
5580 break;
5581 }
5582 break;
5583 case 3: /* lmsw */
5584 /*
5585 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5586 * cr0. Other attempted changes are ignored, with no exit.
5587 */
5588 if (vmcs12->cr0_guest_host_mask & 0xe &
5589 (val ^ vmcs12->cr0_read_shadow))
5590 return 1;
5591 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5592 !(vmcs12->cr0_read_shadow & 0x1) &&
5593 (val & 0x1))
5594 return 1;
5595 break;
5596 }
5597 return 0;
5598 }
5599
5600 /*
5601 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5602 * should handle it ourselves in L0 (and then continue L2). Only call this
5603 * when in is_guest_mode (L2).
5604 */
5605 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5606 {
5607 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5608 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5609 struct vcpu_vmx *vmx = to_vmx(vcpu);
5610 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5611
5612 if (vmx->nested.nested_run_pending)
5613 return 0;
5614
5615 if (unlikely(vmx->fail)) {
5616 printk(KERN_INFO "%s failed vm entry %x\n",
5617 __func__, vmcs_read32(VM_INSTRUCTION_ERROR));
5618 return 1;
5619 }
5620
5621 switch (exit_reason) {
5622 case EXIT_REASON_EXCEPTION_NMI:
5623 if (!is_exception(intr_info))
5624 return 0;
5625 else if (is_page_fault(intr_info))
5626 return enable_ept;
5627 return vmcs12->exception_bitmap &
5628 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5629 case EXIT_REASON_EXTERNAL_INTERRUPT:
5630 return 0;
5631 case EXIT_REASON_TRIPLE_FAULT:
5632 return 1;
5633 case EXIT_REASON_PENDING_INTERRUPT:
5634 case EXIT_REASON_NMI_WINDOW:
5635 /*
5636 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5637 * (aka Interrupt Window Exiting) only when L1 turned it on,
5638 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5639 * Same for NMI Window Exiting.
5640 */
5641 return 1;
5642 case EXIT_REASON_TASK_SWITCH:
5643 return 1;
5644 case EXIT_REASON_CPUID:
5645 return 1;
5646 case EXIT_REASON_HLT:
5647 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5648 case EXIT_REASON_INVD:
5649 return 1;
5650 case EXIT_REASON_INVLPG:
5651 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5652 case EXIT_REASON_RDPMC:
5653 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5654 case EXIT_REASON_RDTSC:
5655 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5656 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5657 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5658 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5659 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5660 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5661 /*
5662 * VMX instructions trap unconditionally. This allows L1 to
5663 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5664 */
5665 return 1;
5666 case EXIT_REASON_CR_ACCESS:
5667 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5668 case EXIT_REASON_DR_ACCESS:
5669 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5670 case EXIT_REASON_IO_INSTRUCTION:
5671 /* TODO: support IO bitmaps */
5672 return 1;
5673 case EXIT_REASON_MSR_READ:
5674 case EXIT_REASON_MSR_WRITE:
5675 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5676 case EXIT_REASON_INVALID_STATE:
5677 return 1;
5678 case EXIT_REASON_MWAIT_INSTRUCTION:
5679 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5680 case EXIT_REASON_MONITOR_INSTRUCTION:
5681 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5682 case EXIT_REASON_PAUSE_INSTRUCTION:
5683 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5684 nested_cpu_has2(vmcs12,
5685 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5686 case EXIT_REASON_MCE_DURING_VMENTRY:
5687 return 0;
5688 case EXIT_REASON_TPR_BELOW_THRESHOLD:
5689 return 1;
5690 case EXIT_REASON_APIC_ACCESS:
5691 return nested_cpu_has2(vmcs12,
5692 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5693 case EXIT_REASON_EPT_VIOLATION:
5694 case EXIT_REASON_EPT_MISCONFIG:
5695 return 0;
5696 case EXIT_REASON_WBINVD:
5697 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5698 case EXIT_REASON_XSETBV:
5699 return 1;
5700 default:
5701 return 1;
5702 }
5703 }
5704
5705 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5706 {
5707 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5708 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5709 }
5710
5711 /*
5712 * The guest has exited. See if we can fix it or if we need userspace
5713 * assistance.
5714 */
5715 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5716 {
5717 struct vcpu_vmx *vmx = to_vmx(vcpu);
5718 u32 exit_reason = vmx->exit_reason;
5719 u32 vectoring_info = vmx->idt_vectoring_info;
5720
5721 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
5722
5723 /* If guest state is invalid, start emulating */
5724 if (vmx->emulation_required && emulate_invalid_guest_state)
5725 return handle_invalid_guest_state(vcpu);
5726
5727 /*
5728 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5729 * we did not inject a still-pending event to L1 now because of
5730 * nested_run_pending, we need to re-enable this bit.
5731 */
5732 if (vmx->nested.nested_run_pending)
5733 kvm_make_request(KVM_REQ_EVENT, vcpu);
5734
5735 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5736 exit_reason == EXIT_REASON_VMRESUME))
5737 vmx->nested.nested_run_pending = 1;
5738 else
5739 vmx->nested.nested_run_pending = 0;
5740
5741 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5742 nested_vmx_vmexit(vcpu);
5743 return 1;
5744 }
5745
5746 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5747 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5748 vcpu->run->fail_entry.hardware_entry_failure_reason
5749 = exit_reason;
5750 return 0;
5751 }
5752
5753 if (unlikely(vmx->fail)) {
5754 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5755 vcpu->run->fail_entry.hardware_entry_failure_reason
5756 = vmcs_read32(VM_INSTRUCTION_ERROR);
5757 return 0;
5758 }
5759
5760 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5761 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5762 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5763 exit_reason != EXIT_REASON_TASK_SWITCH))
5764 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5765 "(0x%x) and exit reason is 0x%x\n",
5766 __func__, vectoring_info, exit_reason);
5767
5768 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
5769 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
5770 get_vmcs12(vcpu), vcpu)))) {
5771 if (vmx_interrupt_allowed(vcpu)) {
5772 vmx->soft_vnmi_blocked = 0;
5773 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
5774 vcpu->arch.nmi_pending) {
5775 /*
5776 * This CPU don't support us in finding the end of an
5777 * NMI-blocked window if the guest runs with IRQs
5778 * disabled. So we pull the trigger after 1 s of
5779 * futile waiting, but inform the user about this.
5780 */
5781 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5782 "state on VCPU %d after 1 s timeout\n",
5783 __func__, vcpu->vcpu_id);
5784 vmx->soft_vnmi_blocked = 0;
5785 }
5786 }
5787
5788 if (exit_reason < kvm_vmx_max_exit_handlers
5789 && kvm_vmx_exit_handlers[exit_reason])
5790 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5791 else {
5792 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5793 vcpu->run->hw.hardware_exit_reason = exit_reason;
5794 }
5795 return 0;
5796 }
5797
5798 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5799 {
5800 if (irr == -1 || tpr < irr) {
5801 vmcs_write32(TPR_THRESHOLD, 0);
5802 return;
5803 }
5804
5805 vmcs_write32(TPR_THRESHOLD, irr);
5806 }
5807
5808 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
5809 {
5810 u32 exit_intr_info;
5811
5812 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
5813 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
5814 return;
5815
5816 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5817 exit_intr_info = vmx->exit_intr_info;
5818
5819 /* Handle machine checks before interrupts are enabled */
5820 if (is_machine_check(exit_intr_info))
5821 kvm_machine_check();
5822
5823 /* We need to handle NMIs before interrupts are enabled */
5824 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
5825 (exit_intr_info & INTR_INFO_VALID_MASK)) {
5826 kvm_before_handle_nmi(&vmx->vcpu);
5827 asm("int $2");
5828 kvm_after_handle_nmi(&vmx->vcpu);
5829 }
5830 }
5831
5832 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
5833 {
5834 u32 exit_intr_info;
5835 bool unblock_nmi;
5836 u8 vector;
5837 bool idtv_info_valid;
5838
5839 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
5840
5841 if (cpu_has_virtual_nmis()) {
5842 if (vmx->nmi_known_unmasked)
5843 return;
5844 /*
5845 * Can't use vmx->exit_intr_info since we're not sure what
5846 * the exit reason is.
5847 */
5848 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5849 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
5850 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
5851 /*
5852 * SDM 3: 27.7.1.2 (September 2008)
5853 * Re-set bit "block by NMI" before VM entry if vmexit caused by
5854 * a guest IRET fault.
5855 * SDM 3: 23.2.2 (September 2008)
5856 * Bit 12 is undefined in any of the following cases:
5857 * If the VM exit sets the valid bit in the IDT-vectoring
5858 * information field.
5859 * If the VM exit is due to a double fault.
5860 */
5861 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
5862 vector != DF_VECTOR && !idtv_info_valid)
5863 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5864 GUEST_INTR_STATE_NMI);
5865 else
5866 vmx->nmi_known_unmasked =
5867 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
5868 & GUEST_INTR_STATE_NMI);
5869 } else if (unlikely(vmx->soft_vnmi_blocked))
5870 vmx->vnmi_blocked_time +=
5871 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
5872 }
5873
5874 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
5875 u32 idt_vectoring_info,
5876 int instr_len_field,
5877 int error_code_field)
5878 {
5879 u8 vector;
5880 int type;
5881 bool idtv_info_valid;
5882
5883 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
5884
5885 vmx->vcpu.arch.nmi_injected = false;
5886 kvm_clear_exception_queue(&vmx->vcpu);
5887 kvm_clear_interrupt_queue(&vmx->vcpu);
5888
5889 if (!idtv_info_valid)
5890 return;
5891
5892 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5893
5894 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
5895 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
5896
5897 switch (type) {
5898 case INTR_TYPE_NMI_INTR:
5899 vmx->vcpu.arch.nmi_injected = true;
5900 /*
5901 * SDM 3: 27.7.1.2 (September 2008)
5902 * Clear bit "block by NMI" before VM entry if a NMI
5903 * delivery faulted.
5904 */
5905 vmx_set_nmi_mask(&vmx->vcpu, false);
5906 break;
5907 case INTR_TYPE_SOFT_EXCEPTION:
5908 vmx->vcpu.arch.event_exit_inst_len =
5909 vmcs_read32(instr_len_field);
5910 /* fall through */
5911 case INTR_TYPE_HARD_EXCEPTION:
5912 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
5913 u32 err = vmcs_read32(error_code_field);
5914 kvm_queue_exception_e(&vmx->vcpu, vector, err);
5915 } else
5916 kvm_queue_exception(&vmx->vcpu, vector);
5917 break;
5918 case INTR_TYPE_SOFT_INTR:
5919 vmx->vcpu.arch.event_exit_inst_len =
5920 vmcs_read32(instr_len_field);
5921 /* fall through */
5922 case INTR_TYPE_EXT_INTR:
5923 kvm_queue_interrupt(&vmx->vcpu, vector,
5924 type == INTR_TYPE_SOFT_INTR);
5925 break;
5926 default:
5927 break;
5928 }
5929 }
5930
5931 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
5932 {
5933 if (is_guest_mode(&vmx->vcpu))
5934 return;
5935 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
5936 VM_EXIT_INSTRUCTION_LEN,
5937 IDT_VECTORING_ERROR_CODE);
5938 }
5939
5940 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
5941 {
5942 if (is_guest_mode(vcpu))
5943 return;
5944 __vmx_complete_interrupts(to_vmx(vcpu),
5945 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5946 VM_ENTRY_INSTRUCTION_LEN,
5947 VM_ENTRY_EXCEPTION_ERROR_CODE);
5948
5949 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
5950 }
5951
5952 #ifdef CONFIG_X86_64
5953 #define R "r"
5954 #define Q "q"
5955 #else
5956 #define R "e"
5957 #define Q "l"
5958 #endif
5959
5960 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
5961 {
5962 struct vcpu_vmx *vmx = to_vmx(vcpu);
5963
5964 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
5965 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5966 if (vmcs12->idt_vectoring_info_field &
5967 VECTORING_INFO_VALID_MASK) {
5968 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5969 vmcs12->idt_vectoring_info_field);
5970 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5971 vmcs12->vm_exit_instruction_len);
5972 if (vmcs12->idt_vectoring_info_field &
5973 VECTORING_INFO_DELIVER_CODE_MASK)
5974 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
5975 vmcs12->idt_vectoring_error_code);
5976 }
5977 }
5978
5979 /* Record the guest's net vcpu time for enforced NMI injections. */
5980 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
5981 vmx->entry_time = ktime_get();
5982
5983 /* Don't enter VMX if guest state is invalid, let the exit handler
5984 start emulation until we arrive back to a valid state */
5985 if (vmx->emulation_required && emulate_invalid_guest_state)
5986 return;
5987
5988 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
5989 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
5990 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
5991 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
5992
5993 /* When single-stepping over STI and MOV SS, we must clear the
5994 * corresponding interruptibility bits in the guest state. Otherwise
5995 * vmentry fails as it then expects bit 14 (BS) in pending debug
5996 * exceptions being set, but that's not correct for the guest debugging
5997 * case. */
5998 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5999 vmx_set_interrupt_shadow(vcpu, 0);
6000
6001 vmx->__launched = vmx->loaded_vmcs->launched;
6002 asm(
6003 /* Store host registers */
6004 "push %%"R"dx; push %%"R"bp;"
6005 "push %%"R"cx \n\t" /* placeholder for guest rcx */
6006 "push %%"R"cx \n\t"
6007 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
6008 "je 1f \n\t"
6009 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
6010 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
6011 "1: \n\t"
6012 /* Reload cr2 if changed */
6013 "mov %c[cr2](%0), %%"R"ax \n\t"
6014 "mov %%cr2, %%"R"dx \n\t"
6015 "cmp %%"R"ax, %%"R"dx \n\t"
6016 "je 2f \n\t"
6017 "mov %%"R"ax, %%cr2 \n\t"
6018 "2: \n\t"
6019 /* Check if vmlaunch of vmresume is needed */
6020 "cmpl $0, %c[launched](%0) \n\t"
6021 /* Load guest registers. Don't clobber flags. */
6022 "mov %c[rax](%0), %%"R"ax \n\t"
6023 "mov %c[rbx](%0), %%"R"bx \n\t"
6024 "mov %c[rdx](%0), %%"R"dx \n\t"
6025 "mov %c[rsi](%0), %%"R"si \n\t"
6026 "mov %c[rdi](%0), %%"R"di \n\t"
6027 "mov %c[rbp](%0), %%"R"bp \n\t"
6028 #ifdef CONFIG_X86_64
6029 "mov %c[r8](%0), %%r8 \n\t"
6030 "mov %c[r9](%0), %%r9 \n\t"
6031 "mov %c[r10](%0), %%r10 \n\t"
6032 "mov %c[r11](%0), %%r11 \n\t"
6033 "mov %c[r12](%0), %%r12 \n\t"
6034 "mov %c[r13](%0), %%r13 \n\t"
6035 "mov %c[r14](%0), %%r14 \n\t"
6036 "mov %c[r15](%0), %%r15 \n\t"
6037 #endif
6038 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
6039
6040 /* Enter guest mode */
6041 "jne .Llaunched \n\t"
6042 __ex(ASM_VMX_VMLAUNCH) "\n\t"
6043 "jmp .Lkvm_vmx_return \n\t"
6044 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
6045 ".Lkvm_vmx_return: "
6046 /* Save guest registers, load host registers, keep flags */
6047 "mov %0, %c[wordsize](%%"R"sp) \n\t"
6048 "pop %0 \n\t"
6049 "mov %%"R"ax, %c[rax](%0) \n\t"
6050 "mov %%"R"bx, %c[rbx](%0) \n\t"
6051 "pop"Q" %c[rcx](%0) \n\t"
6052 "mov %%"R"dx, %c[rdx](%0) \n\t"
6053 "mov %%"R"si, %c[rsi](%0) \n\t"
6054 "mov %%"R"di, %c[rdi](%0) \n\t"
6055 "mov %%"R"bp, %c[rbp](%0) \n\t"
6056 #ifdef CONFIG_X86_64
6057 "mov %%r8, %c[r8](%0) \n\t"
6058 "mov %%r9, %c[r9](%0) \n\t"
6059 "mov %%r10, %c[r10](%0) \n\t"
6060 "mov %%r11, %c[r11](%0) \n\t"
6061 "mov %%r12, %c[r12](%0) \n\t"
6062 "mov %%r13, %c[r13](%0) \n\t"
6063 "mov %%r14, %c[r14](%0) \n\t"
6064 "mov %%r15, %c[r15](%0) \n\t"
6065 #endif
6066 "mov %%cr2, %%"R"ax \n\t"
6067 "mov %%"R"ax, %c[cr2](%0) \n\t"
6068
6069 "pop %%"R"bp; pop %%"R"dx \n\t"
6070 "setbe %c[fail](%0) \n\t"
6071 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
6072 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
6073 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
6074 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
6075 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6076 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6077 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6078 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6079 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6080 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6081 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
6082 #ifdef CONFIG_X86_64
6083 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6084 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6085 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6086 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6087 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6088 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6089 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6090 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6091 #endif
6092 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6093 [wordsize]"i"(sizeof(ulong))
6094 : "cc", "memory"
6095 , R"ax", R"bx", R"di", R"si"
6096 #ifdef CONFIG_X86_64
6097 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6098 #endif
6099 );
6100
6101 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6102 | (1 << VCPU_EXREG_RFLAGS)
6103 | (1 << VCPU_EXREG_CPL)
6104 | (1 << VCPU_EXREG_PDPTR)
6105 | (1 << VCPU_EXREG_SEGMENTS)
6106 | (1 << VCPU_EXREG_CR3));
6107 vcpu->arch.regs_dirty = 0;
6108
6109 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6110
6111 if (is_guest_mode(vcpu)) {
6112 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6113 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6114 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6115 vmcs12->idt_vectoring_error_code =
6116 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6117 vmcs12->vm_exit_instruction_len =
6118 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6119 }
6120 }
6121
6122 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
6123 vmx->loaded_vmcs->launched = 1;
6124
6125 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
6126
6127 vmx_complete_atomic_exit(vmx);
6128 vmx_recover_nmi_blocking(vmx);
6129 vmx_complete_interrupts(vmx);
6130 }
6131
6132 #undef R
6133 #undef Q
6134
6135 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6136 {
6137 struct vcpu_vmx *vmx = to_vmx(vcpu);
6138
6139 free_vpid(vmx);
6140 free_nested(vmx);
6141 free_loaded_vmcs(vmx->loaded_vmcs);
6142 kfree(vmx->guest_msrs);
6143 kvm_vcpu_uninit(vcpu);
6144 kmem_cache_free(kvm_vcpu_cache, vmx);
6145 }
6146
6147 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6148 {
6149 int err;
6150 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
6151 int cpu;
6152
6153 if (!vmx)
6154 return ERR_PTR(-ENOMEM);
6155
6156 allocate_vpid(vmx);
6157
6158 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6159 if (err)
6160 goto free_vcpu;
6161
6162 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
6163 err = -ENOMEM;
6164 if (!vmx->guest_msrs) {
6165 goto uninit_vcpu;
6166 }
6167
6168 vmx->loaded_vmcs = &vmx->vmcs01;
6169 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6170 if (!vmx->loaded_vmcs->vmcs)
6171 goto free_msrs;
6172 if (!vmm_exclusive)
6173 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6174 loaded_vmcs_init(vmx->loaded_vmcs);
6175 if (!vmm_exclusive)
6176 kvm_cpu_vmxoff();
6177
6178 cpu = get_cpu();
6179 vmx_vcpu_load(&vmx->vcpu, cpu);
6180 vmx->vcpu.cpu = cpu;
6181 err = vmx_vcpu_setup(vmx);
6182 vmx_vcpu_put(&vmx->vcpu);
6183 put_cpu();
6184 if (err)
6185 goto free_vmcs;
6186 if (vm_need_virtualize_apic_accesses(kvm))
6187 err = alloc_apic_access_page(kvm);
6188 if (err)
6189 goto free_vmcs;
6190
6191 if (enable_ept) {
6192 if (!kvm->arch.ept_identity_map_addr)
6193 kvm->arch.ept_identity_map_addr =
6194 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
6195 err = -ENOMEM;
6196 if (alloc_identity_pagetable(kvm) != 0)
6197 goto free_vmcs;
6198 if (!init_rmode_identity_map(kvm))
6199 goto free_vmcs;
6200 }
6201
6202 vmx->nested.current_vmptr = -1ull;
6203 vmx->nested.current_vmcs12 = NULL;
6204
6205 return &vmx->vcpu;
6206
6207 free_vmcs:
6208 free_vmcs(vmx->loaded_vmcs->vmcs);
6209 free_msrs:
6210 kfree(vmx->guest_msrs);
6211 uninit_vcpu:
6212 kvm_vcpu_uninit(&vmx->vcpu);
6213 free_vcpu:
6214 free_vpid(vmx);
6215 kmem_cache_free(kvm_vcpu_cache, vmx);
6216 return ERR_PTR(err);
6217 }
6218
6219 static void __init vmx_check_processor_compat(void *rtn)
6220 {
6221 struct vmcs_config vmcs_conf;
6222
6223 *(int *)rtn = 0;
6224 if (setup_vmcs_config(&vmcs_conf) < 0)
6225 *(int *)rtn = -EIO;
6226 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6227 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6228 smp_processor_id());
6229 *(int *)rtn = -EIO;
6230 }
6231 }
6232
6233 static int get_ept_level(void)
6234 {
6235 return VMX_EPT_DEFAULT_GAW + 1;
6236 }
6237
6238 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6239 {
6240 u64 ret;
6241
6242 /* For VT-d and EPT combination
6243 * 1. MMIO: always map as UC
6244 * 2. EPT with VT-d:
6245 * a. VT-d without snooping control feature: can't guarantee the
6246 * result, try to trust guest.
6247 * b. VT-d with snooping control feature: snooping control feature of
6248 * VT-d engine can guarantee the cache correctness. Just set it
6249 * to WB to keep consistent with host. So the same as item 3.
6250 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6251 * consistent with host MTRR
6252 */
6253 if (is_mmio)
6254 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
6255 else if (vcpu->kvm->arch.iommu_domain &&
6256 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6257 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6258 VMX_EPT_MT_EPTE_SHIFT;
6259 else
6260 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
6261 | VMX_EPT_IPAT_BIT;
6262
6263 return ret;
6264 }
6265
6266 static int vmx_get_lpage_level(void)
6267 {
6268 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6269 return PT_DIRECTORY_LEVEL;
6270 else
6271 /* For shadow and EPT supported 1GB page */
6272 return PT_PDPE_LEVEL;
6273 }
6274
6275 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6276 {
6277 struct kvm_cpuid_entry2 *best;
6278 struct vcpu_vmx *vmx = to_vmx(vcpu);
6279 u32 exec_control;
6280
6281 vmx->rdtscp_enabled = false;
6282 if (vmx_rdtscp_supported()) {
6283 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6284 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6285 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6286 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6287 vmx->rdtscp_enabled = true;
6288 else {
6289 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6290 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6291 exec_control);
6292 }
6293 }
6294 }
6295 }
6296
6297 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6298 {
6299 if (func == 1 && nested)
6300 entry->ecx |= bit(X86_FEATURE_VMX);
6301 }
6302
6303 /*
6304 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6305 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6306 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6307 * guest in a way that will both be appropriate to L1's requests, and our
6308 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6309 * function also has additional necessary side-effects, like setting various
6310 * vcpu->arch fields.
6311 */
6312 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6313 {
6314 struct vcpu_vmx *vmx = to_vmx(vcpu);
6315 u32 exec_control;
6316
6317 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6318 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6319 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6320 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6321 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6322 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6323 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6324 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6325 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6326 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6327 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6328 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6329 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6330 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6331 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6332 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6333 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6334 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6335 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6336 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6337 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6338 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6339 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6340 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6341 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6342 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6343 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6344 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6345 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6346 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6347 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6348 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6349 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6350 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6351 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6352 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6353
6354 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6355 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6356 vmcs12->vm_entry_intr_info_field);
6357 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6358 vmcs12->vm_entry_exception_error_code);
6359 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6360 vmcs12->vm_entry_instruction_len);
6361 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6362 vmcs12->guest_interruptibility_info);
6363 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6364 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6365 vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6366 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6367 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6368 vmcs12->guest_pending_dbg_exceptions);
6369 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6370 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6371
6372 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6373
6374 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6375 (vmcs_config.pin_based_exec_ctrl |
6376 vmcs12->pin_based_vm_exec_control));
6377
6378 /*
6379 * Whether page-faults are trapped is determined by a combination of
6380 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6381 * If enable_ept, L0 doesn't care about page faults and we should
6382 * set all of these to L1's desires. However, if !enable_ept, L0 does
6383 * care about (at least some) page faults, and because it is not easy
6384 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6385 * to exit on each and every L2 page fault. This is done by setting
6386 * MASK=MATCH=0 and (see below) EB.PF=1.
6387 * Note that below we don't need special code to set EB.PF beyond the
6388 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6389 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6390 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6391 *
6392 * A problem with this approach (when !enable_ept) is that L1 may be
6393 * injected with more page faults than it asked for. This could have
6394 * caused problems, but in practice existing hypervisors don't care.
6395 * To fix this, we will need to emulate the PFEC checking (on the L1
6396 * page tables), using walk_addr(), when injecting PFs to L1.
6397 */
6398 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6399 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6400 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6401 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6402
6403 if (cpu_has_secondary_exec_ctrls()) {
6404 u32 exec_control = vmx_secondary_exec_control(vmx);
6405 if (!vmx->rdtscp_enabled)
6406 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6407 /* Take the following fields only from vmcs12 */
6408 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6409 if (nested_cpu_has(vmcs12,
6410 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6411 exec_control |= vmcs12->secondary_vm_exec_control;
6412
6413 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6414 /*
6415 * Translate L1 physical address to host physical
6416 * address for vmcs02. Keep the page pinned, so this
6417 * physical address remains valid. We keep a reference
6418 * to it so we can release it later.
6419 */
6420 if (vmx->nested.apic_access_page) /* shouldn't happen */
6421 nested_release_page(vmx->nested.apic_access_page);
6422 vmx->nested.apic_access_page =
6423 nested_get_page(vcpu, vmcs12->apic_access_addr);
6424 /*
6425 * If translation failed, no matter: This feature asks
6426 * to exit when accessing the given address, and if it
6427 * can never be accessed, this feature won't do
6428 * anything anyway.
6429 */
6430 if (!vmx->nested.apic_access_page)
6431 exec_control &=
6432 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6433 else
6434 vmcs_write64(APIC_ACCESS_ADDR,
6435 page_to_phys(vmx->nested.apic_access_page));
6436 }
6437
6438 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6439 }
6440
6441
6442 /*
6443 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6444 * Some constant fields are set here by vmx_set_constant_host_state().
6445 * Other fields are different per CPU, and will be set later when
6446 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6447 */
6448 vmx_set_constant_host_state();
6449
6450 /*
6451 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6452 * entry, but only if the current (host) sp changed from the value
6453 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6454 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6455 * here we just force the write to happen on entry.
6456 */
6457 vmx->host_rsp = 0;
6458
6459 exec_control = vmx_exec_control(vmx); /* L0's desires */
6460 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6461 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6462 exec_control &= ~CPU_BASED_TPR_SHADOW;
6463 exec_control |= vmcs12->cpu_based_vm_exec_control;
6464 /*
6465 * Merging of IO and MSR bitmaps not currently supported.
6466 * Rather, exit every time.
6467 */
6468 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6469 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6470 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6471
6472 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6473
6474 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6475 * bitwise-or of what L1 wants to trap for L2, and what we want to
6476 * trap. Note that CR0.TS also needs updating - we do this later.
6477 */
6478 update_exception_bitmap(vcpu);
6479 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6480 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6481
6482 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6483 vmcs_write32(VM_EXIT_CONTROLS,
6484 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6485 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6486 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6487
6488 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6489 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6490 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6491 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6492
6493
6494 set_cr4_guest_host_mask(vmx);
6495
6496 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6497 vmcs_write64(TSC_OFFSET,
6498 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6499 else
6500 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
6501
6502 if (enable_vpid) {
6503 /*
6504 * Trivially support vpid by letting L2s share their parent
6505 * L1's vpid. TODO: move to a more elaborate solution, giving
6506 * each L2 its own vpid and exposing the vpid feature to L1.
6507 */
6508 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6509 vmx_flush_tlb(vcpu);
6510 }
6511
6512 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6513 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6514 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6515 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6516 else
6517 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6518 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6519 vmx_set_efer(vcpu, vcpu->arch.efer);
6520
6521 /*
6522 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6523 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6524 * The CR0_READ_SHADOW is what L2 should have expected to read given
6525 * the specifications by L1; It's not enough to take
6526 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6527 * have more bits than L1 expected.
6528 */
6529 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6530 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6531
6532 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6533 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6534
6535 /* shadow page tables on either EPT or shadow page tables */
6536 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6537 kvm_mmu_reset_context(vcpu);
6538
6539 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6540 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6541 }
6542
6543 /*
6544 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6545 * for running an L2 nested guest.
6546 */
6547 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6548 {
6549 struct vmcs12 *vmcs12;
6550 struct vcpu_vmx *vmx = to_vmx(vcpu);
6551 int cpu;
6552 struct loaded_vmcs *vmcs02;
6553
6554 if (!nested_vmx_check_permission(vcpu) ||
6555 !nested_vmx_check_vmcs12(vcpu))
6556 return 1;
6557
6558 skip_emulated_instruction(vcpu);
6559 vmcs12 = get_vmcs12(vcpu);
6560
6561 /*
6562 * The nested entry process starts with enforcing various prerequisites
6563 * on vmcs12 as required by the Intel SDM, and act appropriately when
6564 * they fail: As the SDM explains, some conditions should cause the
6565 * instruction to fail, while others will cause the instruction to seem
6566 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6567 * To speed up the normal (success) code path, we should avoid checking
6568 * for misconfigurations which will anyway be caught by the processor
6569 * when using the merged vmcs02.
6570 */
6571 if (vmcs12->launch_state == launch) {
6572 nested_vmx_failValid(vcpu,
6573 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6574 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6575 return 1;
6576 }
6577
6578 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6579 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6580 /*TODO: Also verify bits beyond physical address width are 0*/
6581 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6582 return 1;
6583 }
6584
6585 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6586 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6587 /*TODO: Also verify bits beyond physical address width are 0*/
6588 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6589 return 1;
6590 }
6591
6592 if (vmcs12->vm_entry_msr_load_count > 0 ||
6593 vmcs12->vm_exit_msr_load_count > 0 ||
6594 vmcs12->vm_exit_msr_store_count > 0) {
6595 if (printk_ratelimit())
6596 printk(KERN_WARNING
6597 "%s: VMCS MSR_{LOAD,STORE} unsupported\n", __func__);
6598 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6599 return 1;
6600 }
6601
6602 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6603 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6604 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6605 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6606 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6607 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6608 !vmx_control_verify(vmcs12->vm_exit_controls,
6609 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6610 !vmx_control_verify(vmcs12->vm_entry_controls,
6611 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6612 {
6613 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6614 return 1;
6615 }
6616
6617 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6618 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6619 nested_vmx_failValid(vcpu,
6620 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6621 return 1;
6622 }
6623
6624 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6625 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6626 nested_vmx_entry_failure(vcpu, vmcs12,
6627 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6628 return 1;
6629 }
6630 if (vmcs12->vmcs_link_pointer != -1ull) {
6631 nested_vmx_entry_failure(vcpu, vmcs12,
6632 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6633 return 1;
6634 }
6635
6636 /*
6637 * We're finally done with prerequisite checking, and can start with
6638 * the nested entry.
6639 */
6640
6641 vmcs02 = nested_get_current_vmcs02(vmx);
6642 if (!vmcs02)
6643 return -ENOMEM;
6644
6645 enter_guest_mode(vcpu);
6646
6647 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6648
6649 cpu = get_cpu();
6650 vmx->loaded_vmcs = vmcs02;
6651 vmx_vcpu_put(vcpu);
6652 vmx_vcpu_load(vcpu, cpu);
6653 vcpu->cpu = cpu;
6654 put_cpu();
6655
6656 vmcs12->launch_state = 1;
6657
6658 prepare_vmcs02(vcpu, vmcs12);
6659
6660 /*
6661 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6662 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6663 * returned as far as L1 is concerned. It will only return (and set
6664 * the success flag) when L2 exits (see nested_vmx_vmexit()).
6665 */
6666 return 1;
6667 }
6668
6669 /*
6670 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6671 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6672 * This function returns the new value we should put in vmcs12.guest_cr0.
6673 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6674 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6675 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6676 * didn't trap the bit, because if L1 did, so would L0).
6677 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6678 * been modified by L2, and L1 knows it. So just leave the old value of
6679 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6680 * isn't relevant, because if L0 traps this bit it can set it to anything.
6681 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6682 * changed these bits, and therefore they need to be updated, but L0
6683 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6684 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6685 */
6686 static inline unsigned long
6687 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6688 {
6689 return
6690 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6691 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6692 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6693 vcpu->arch.cr0_guest_owned_bits));
6694 }
6695
6696 static inline unsigned long
6697 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6698 {
6699 return
6700 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6701 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6702 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6703 vcpu->arch.cr4_guest_owned_bits));
6704 }
6705
6706 /*
6707 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6708 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6709 * and this function updates it to reflect the changes to the guest state while
6710 * L2 was running (and perhaps made some exits which were handled directly by L0
6711 * without going back to L1), and to reflect the exit reason.
6712 * Note that we do not have to copy here all VMCS fields, just those that
6713 * could have changed by the L2 guest or the exit - i.e., the guest-state and
6714 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
6715 * which already writes to vmcs12 directly.
6716 */
6717 void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6718 {
6719 /* update guest state fields: */
6720 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
6721 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
6722
6723 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
6724 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6725 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
6726 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
6727
6728 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
6729 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
6730 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
6731 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
6732 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
6733 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
6734 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
6735 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
6736 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
6737 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
6738 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
6739 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
6740 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
6741 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
6742 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
6743 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
6744 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
6745 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
6746 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
6747 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
6748 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
6749 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
6750 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
6751 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
6752 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
6753 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
6754 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
6755 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
6756 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
6757 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
6758 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
6759 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
6760 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
6761 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
6762 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
6763 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
6764
6765 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
6766 vmcs12->guest_interruptibility_info =
6767 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
6768 vmcs12->guest_pending_dbg_exceptions =
6769 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
6770
6771 /* TODO: These cannot have changed unless we have MSR bitmaps and
6772 * the relevant bit asks not to trap the change */
6773 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
6774 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
6775 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
6776 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
6777 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
6778 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
6779
6780 /* update exit information fields: */
6781
6782 vmcs12->vm_exit_reason = vmcs_read32(VM_EXIT_REASON);
6783 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6784
6785 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6786 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6787 vmcs12->idt_vectoring_info_field =
6788 vmcs_read32(IDT_VECTORING_INFO_FIELD);
6789 vmcs12->idt_vectoring_error_code =
6790 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6791 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6792 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6793
6794 /* clear vm-entry fields which are to be cleared on exit */
6795 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6796 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
6797 }
6798
6799 /*
6800 * A part of what we need to when the nested L2 guest exits and we want to
6801 * run its L1 parent, is to reset L1's guest state to the host state specified
6802 * in vmcs12.
6803 * This function is to be called not only on normal nested exit, but also on
6804 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
6805 * Failures During or After Loading Guest State").
6806 * This function should be called when the active VMCS is L1's (vmcs01).
6807 */
6808 void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6809 {
6810 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
6811 vcpu->arch.efer = vmcs12->host_ia32_efer;
6812 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
6813 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6814 else
6815 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6816 vmx_set_efer(vcpu, vcpu->arch.efer);
6817
6818 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
6819 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
6820 /*
6821 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
6822 * actually changed, because it depends on the current state of
6823 * fpu_active (which may have changed).
6824 * Note that vmx_set_cr0 refers to efer set above.
6825 */
6826 kvm_set_cr0(vcpu, vmcs12->host_cr0);
6827 /*
6828 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
6829 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
6830 * but we also need to update cr0_guest_host_mask and exception_bitmap.
6831 */
6832 update_exception_bitmap(vcpu);
6833 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
6834 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6835
6836 /*
6837 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
6838 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
6839 */
6840 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
6841 kvm_set_cr4(vcpu, vmcs12->host_cr4);
6842
6843 /* shadow page tables on either EPT or shadow page tables */
6844 kvm_set_cr3(vcpu, vmcs12->host_cr3);
6845 kvm_mmu_reset_context(vcpu);
6846
6847 if (enable_vpid) {
6848 /*
6849 * Trivially support vpid by letting L2s share their parent
6850 * L1's vpid. TODO: move to a more elaborate solution, giving
6851 * each L2 its own vpid and exposing the vpid feature to L1.
6852 */
6853 vmx_flush_tlb(vcpu);
6854 }
6855
6856
6857 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
6858 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
6859 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
6860 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
6861 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
6862 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
6863 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
6864 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
6865 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
6866 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
6867 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
6868 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
6869 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
6870 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
6871 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
6872
6873 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
6874 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
6875 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
6876 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
6877 vmcs12->host_ia32_perf_global_ctrl);
6878 }
6879
6880 /*
6881 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
6882 * and modify vmcs12 to make it see what it would expect to see there if
6883 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
6884 */
6885 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
6886 {
6887 struct vcpu_vmx *vmx = to_vmx(vcpu);
6888 int cpu;
6889 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6890
6891 leave_guest_mode(vcpu);
6892 prepare_vmcs12(vcpu, vmcs12);
6893
6894 cpu = get_cpu();
6895 vmx->loaded_vmcs = &vmx->vmcs01;
6896 vmx_vcpu_put(vcpu);
6897 vmx_vcpu_load(vcpu, cpu);
6898 vcpu->cpu = cpu;
6899 put_cpu();
6900
6901 /* if no vmcs02 cache requested, remove the one we used */
6902 if (VMCS02_POOL_SIZE == 0)
6903 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
6904
6905 load_vmcs12_host_state(vcpu, vmcs12);
6906
6907 /* Update TSC_OFFSET if TSC was changed while L2 ran */
6908 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
6909
6910 /* This is needed for same reason as it was needed in prepare_vmcs02 */
6911 vmx->host_rsp = 0;
6912
6913 /* Unpin physical memory we referred to in vmcs02 */
6914 if (vmx->nested.apic_access_page) {
6915 nested_release_page(vmx->nested.apic_access_page);
6916 vmx->nested.apic_access_page = 0;
6917 }
6918
6919 /*
6920 * Exiting from L2 to L1, we're now back to L1 which thinks it just
6921 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
6922 * success or failure flag accordingly.
6923 */
6924 if (unlikely(vmx->fail)) {
6925 vmx->fail = 0;
6926 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
6927 } else
6928 nested_vmx_succeed(vcpu);
6929 }
6930
6931 /*
6932 * L1's failure to enter L2 is a subset of a normal exit, as explained in
6933 * 23.7 "VM-entry failures during or after loading guest state" (this also
6934 * lists the acceptable exit-reason and exit-qualification parameters).
6935 * It should only be called before L2 actually succeeded to run, and when
6936 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
6937 */
6938 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
6939 struct vmcs12 *vmcs12,
6940 u32 reason, unsigned long qualification)
6941 {
6942 load_vmcs12_host_state(vcpu, vmcs12);
6943 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
6944 vmcs12->exit_qualification = qualification;
6945 nested_vmx_succeed(vcpu);
6946 }
6947
6948 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
6949 struct x86_instruction_info *info,
6950 enum x86_intercept_stage stage)
6951 {
6952 return X86EMUL_CONTINUE;
6953 }
6954
6955 static struct kvm_x86_ops vmx_x86_ops = {
6956 .cpu_has_kvm_support = cpu_has_kvm_support,
6957 .disabled_by_bios = vmx_disabled_by_bios,
6958 .hardware_setup = hardware_setup,
6959 .hardware_unsetup = hardware_unsetup,
6960 .check_processor_compatibility = vmx_check_processor_compat,
6961 .hardware_enable = hardware_enable,
6962 .hardware_disable = hardware_disable,
6963 .cpu_has_accelerated_tpr = report_flexpriority,
6964
6965 .vcpu_create = vmx_create_vcpu,
6966 .vcpu_free = vmx_free_vcpu,
6967 .vcpu_reset = vmx_vcpu_reset,
6968
6969 .prepare_guest_switch = vmx_save_host_state,
6970 .vcpu_load = vmx_vcpu_load,
6971 .vcpu_put = vmx_vcpu_put,
6972
6973 .set_guest_debug = set_guest_debug,
6974 .get_msr = vmx_get_msr,
6975 .set_msr = vmx_set_msr,
6976 .get_segment_base = vmx_get_segment_base,
6977 .get_segment = vmx_get_segment,
6978 .set_segment = vmx_set_segment,
6979 .get_cpl = vmx_get_cpl,
6980 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
6981 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
6982 .decache_cr3 = vmx_decache_cr3,
6983 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6984 .set_cr0 = vmx_set_cr0,
6985 .set_cr3 = vmx_set_cr3,
6986 .set_cr4 = vmx_set_cr4,
6987 .set_efer = vmx_set_efer,
6988 .get_idt = vmx_get_idt,
6989 .set_idt = vmx_set_idt,
6990 .get_gdt = vmx_get_gdt,
6991 .set_gdt = vmx_set_gdt,
6992 .set_dr7 = vmx_set_dr7,
6993 .cache_reg = vmx_cache_reg,
6994 .get_rflags = vmx_get_rflags,
6995 .set_rflags = vmx_set_rflags,
6996 .fpu_activate = vmx_fpu_activate,
6997 .fpu_deactivate = vmx_fpu_deactivate,
6998
6999 .tlb_flush = vmx_flush_tlb,
7000
7001 .run = vmx_vcpu_run,
7002 .handle_exit = vmx_handle_exit,
7003 .skip_emulated_instruction = skip_emulated_instruction,
7004 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7005 .get_interrupt_shadow = vmx_get_interrupt_shadow,
7006 .patch_hypercall = vmx_patch_hypercall,
7007 .set_irq = vmx_inject_irq,
7008 .set_nmi = vmx_inject_nmi,
7009 .queue_exception = vmx_queue_exception,
7010 .cancel_injection = vmx_cancel_injection,
7011 .interrupt_allowed = vmx_interrupt_allowed,
7012 .nmi_allowed = vmx_nmi_allowed,
7013 .get_nmi_mask = vmx_get_nmi_mask,
7014 .set_nmi_mask = vmx_set_nmi_mask,
7015 .enable_nmi_window = enable_nmi_window,
7016 .enable_irq_window = enable_irq_window,
7017 .update_cr8_intercept = update_cr8_intercept,
7018
7019 .set_tss_addr = vmx_set_tss_addr,
7020 .get_tdp_level = get_ept_level,
7021 .get_mt_mask = vmx_get_mt_mask,
7022
7023 .get_exit_info = vmx_get_exit_info,
7024
7025 .get_lpage_level = vmx_get_lpage_level,
7026
7027 .cpuid_update = vmx_cpuid_update,
7028
7029 .rdtscp_supported = vmx_rdtscp_supported,
7030
7031 .set_supported_cpuid = vmx_set_supported_cpuid,
7032
7033 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7034
7035 .set_tsc_khz = vmx_set_tsc_khz,
7036 .write_tsc_offset = vmx_write_tsc_offset,
7037 .adjust_tsc_offset = vmx_adjust_tsc_offset,
7038 .compute_tsc_offset = vmx_compute_tsc_offset,
7039 .read_l1_tsc = vmx_read_l1_tsc,
7040
7041 .set_tdp_cr3 = vmx_set_cr3,
7042
7043 .check_intercept = vmx_check_intercept,
7044 };
7045
7046 static int __init vmx_init(void)
7047 {
7048 int r, i;
7049
7050 rdmsrl_safe(MSR_EFER, &host_efer);
7051
7052 for (i = 0; i < NR_VMX_MSR; ++i)
7053 kvm_define_shared_msr(i, vmx_msr_index[i]);
7054
7055 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
7056 if (!vmx_io_bitmap_a)
7057 return -ENOMEM;
7058
7059 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
7060 if (!vmx_io_bitmap_b) {
7061 r = -ENOMEM;
7062 goto out;
7063 }
7064
7065 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7066 if (!vmx_msr_bitmap_legacy) {
7067 r = -ENOMEM;
7068 goto out1;
7069 }
7070
7071 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7072 if (!vmx_msr_bitmap_longmode) {
7073 r = -ENOMEM;
7074 goto out2;
7075 }
7076
7077 /*
7078 * Allow direct access to the PC debug port (it is often used for I/O
7079 * delays, but the vmexits simply slow things down).
7080 */
7081 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7082 clear_bit(0x80, vmx_io_bitmap_a);
7083
7084 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
7085
7086 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7087 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
7088
7089 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7090
7091 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7092 __alignof__(struct vcpu_vmx), THIS_MODULE);
7093 if (r)
7094 goto out3;
7095
7096 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7097 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7098 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7099 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7100 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7101 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
7102
7103 if (enable_ept) {
7104 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
7105 VMX_EPT_EXECUTABLE_MASK);
7106 ept_set_mmio_spte_mask();
7107 kvm_enable_tdp();
7108 } else
7109 kvm_disable_tdp();
7110
7111 return 0;
7112
7113 out3:
7114 free_page((unsigned long)vmx_msr_bitmap_longmode);
7115 out2:
7116 free_page((unsigned long)vmx_msr_bitmap_legacy);
7117 out1:
7118 free_page((unsigned long)vmx_io_bitmap_b);
7119 out:
7120 free_page((unsigned long)vmx_io_bitmap_a);
7121 return r;
7122 }
7123
7124 static void __exit vmx_exit(void)
7125 {
7126 free_page((unsigned long)vmx_msr_bitmap_legacy);
7127 free_page((unsigned long)vmx_msr_bitmap_longmode);
7128 free_page((unsigned long)vmx_io_bitmap_b);
7129 free_page((unsigned long)vmx_io_bitmap_a);
7130
7131 kvm_exit();
7132 }
7133
7134 module_init(vmx_init)
7135 module_exit(vmx_exit)
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