arch/xtensa/include/asm/regs.h

   1 /*
   2  * Copyright (c) 2006 Tensilica, Inc.  All Rights Reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of version 2.1 of the GNU Lesser General Public
   6  * License as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it would be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  11  *
  12  * Further, this software is distributed without any warranty that it is
  13  * free of the rightful claim of any third person regarding infringement
  14  * or the like.  Any license provided herein, whether implied or
  15  * otherwise, applies only to this software file.  Patent licenses, if
  16  * any, provided herein do not apply to combinations of this program with
  17  * other software, or any other product whatsoever.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this program; if not, write the Free Software
  21  * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
  22  * USA.
  23  */
  24
  25 #ifndef _XTENSA_REGS_H
  26 #define _XTENSA_REGS_H
  27
  28 /* Special register numbers
  29  *
  30  * LBEG         0
  31  * LEND         1
  32  * LCOUNT       2
  33  * SAR          3
  34  * BR           4
  35  * SCOMPARE1    12
  36  * ACCHI        16
  37  * ACCLO        17
  38  * MR           32
  39  * WINDOWBASE   72
  40  * WINDOWSTART  73
  41  * PTEVADDR     83
  42  * RASID        90
  43  * ITLBCFG      91
  44  * DTLBCFG      92
  45  * IBREAKENABLE 96
  46  * DDR          104
  47  * IBREAKA      128
  48  * DBREAKA      144
  49  * DBREAKC      160
  50  * EPC          176
  51  * EPC1         177
  52  * DEPC         192
  53  * EPS          192
  54  * EPS1         193
  55  * EXCSAVE      208
  56  * EXCSAVE1     209
  57  * INTERRUPT    226
  58  * INTENABLE    228
  59  * PS           230
  60  * THREADPTR    231
  61  * EXCCAUSE     232
  62  * DEBUGCAUSE   233
  63  * CCOUNT       234
  64  * PRID         235
  65  * ICOUNT       236
  66  * ICOUNTLEVEL  237
  67  * EXCVADDR     238
  68  * CCOMPARE     240
  69  * MISC         244
  70  */
  71
  72 /*  Special names for read-only and write-only interrupt registers.  */
  73
  74 #define INTREAD         226
  75 #define INTSET          226
  76 #define INTCLEAR        227
  77
  78 #define XTREG_EPS(x)            (192+(x))
  79 #define XTREG_EPC(x)            (176+(x))
  80 #define XTREG_EXCSAVE(x)        (208+(x))
  81 #define XTREG_CCOMPARE(x)       (240+(x))
  82 #define XTREG_DBREAKC(x)        (160+(x))
  83
  84 /*  EXCCAUSE register fields  */
  85
  86 #define EXCCAUSE_EXCCAUSE_SHIFT 0
  87 #define EXCCAUSE_EXCCAUSE_MASK  0x3F
  88
  89 #define EXCCAUSE_ILLEGAL_INSTRUCTION            0
  90 #define EXCCAUSE_SYSTEM_CALL                    1
  91 #define EXCCAUSE_INSTRUCTION_FETCH_ERROR        2
  92 #define EXCCAUSE_LOAD_STORE_ERROR               3
  93 #define EXCCAUSE_LEVEL1_INTERRUPT               4
  94 #define EXCCAUSE_ALLOCA                         5
  95 #define EXCCAUSE_INTEGER_DIVIDE_BY_ZERO         6
  96 #define EXCCAUSE_SPECULATION                    7
  97 #define EXCCAUSE_PRIVILEGED                     8
  98 #define EXCCAUSE_UNALIGNED                      9
  99 #define EXCCAUSE_ITLB_MISS                      16
 100 #define EXCCAUSE_ITLB_MULTIHIT                  17
 101 #define EXCCAUSE_ITLB_PRIVILEGE                 18
 102 #define EXCCAUSE_ITLB_SIZE_RESTRICTION          19
 103 #define EXCCAUSE_FETCH_CACHE_ATTRIBUTE          20
 104 #define EXCCAUSE_DTLB_MISS                      24
 105 #define EXCCAUSE_DTLB_MULTIHIT                  25
 106 #define EXCCAUSE_DTLB_PRIVILEGE                 26
 107 #define EXCCAUSE_DTLB_SIZE_RESTRICTION          27
 108 #define EXCCAUSE_LOAD_CACHE_ATTRIBUTE           28
 109 #define EXCCAUSE_STORE_CACHE_ATTRIBUTE          29
 110 #define EXCCAUSE_COPROCESSOR0_DISABLED          32
 111 #define EXCCAUSE_COPROCESSOR1_DISABLED          33
 112 #define EXCCAUSE_COPROCESSOR2_DISABLED          34
 113 #define EXCCAUSE_COPROCESSOR3_DISABLED          35
 114 #define EXCCAUSE_COPROCESSOR4_DISABLED          36
 115 #define EXCCAUSE_COPROCESSOR5_DISABLED          37
 116 #define EXCCAUSE_COPROCESSOR6_DISABLED          38
 117 #define EXCCAUSE_COPROCESSOR7_DISABLED          39
 118
 119 /*  PS register fields.  */
 120
 121 #define PS_WOE_BIT              18
 122 #define PS_CALLINC_SHIFT        16
 123 #define PS_CALLINC_MASK         0x00030000
 124 #define PS_OWB_SHIFT            8
 125 #define PS_OWB_MASK             0x00000F00
 126 #define PS_RING_SHIFT           6
 127 #define PS_RING_MASK            0x000000C0
 128 #define PS_UM_BIT               5
 129 #define PS_EXCM_BIT             4
 130 #define PS_INTLEVEL_SHIFT       0
 131 #define PS_INTLEVEL_MASK        0x0000000F
 132
 133 /*  DBREAKCn register fields.  */
 134
 135 #define DBREAKC_MASK_BIT                0
 136 #define DBREAKC_MASK_MASK               0x0000003F
 137 #define DBREAKC_LOAD_BIT                30
 138 #define DBREAKC_LOAD_MASK               0x40000000
 139 #define DBREAKC_STOR_BIT                31
 140 #define DBREAKC_STOR_MASK               0x80000000
 141
 142 /*  DEBUGCAUSE register fields.  */
 143
 144 #define DEBUGCAUSE_DEBUGINT_BIT         5       /* External debug interrupt */
 145 #define DEBUGCAUSE_BREAKN_BIT           4       /* BREAK.N instruction */
 146 #define DEBUGCAUSE_BREAK_BIT            3       /* BREAK instruction */
 147 #define DEBUGCAUSE_DBREAK_BIT           2       /* DBREAK match */
 148 #define DEBUGCAUSE_IBREAK_BIT           1       /* IBREAK match */
 149 #define DEBUGCAUSE_ICOUNT_BIT           0       /* ICOUNT would incr. to zero */
 150
 151 #endif /* _XTENSA_SPECREG_H */
 152