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Add linux-next specific files for 20110831
[linux-2.6/next.git] / drivers / dma / ipu / ipu_idmac.c
blobd7f2fbdcf96891defe947642a7ba8dc5ea8f9106
1 /*
2 * Copyright (C) 2008
3 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
4 *
5 * Copyright (C) 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/dma-mapping.h>
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include <linux/err.h>
16 #include <linux/spinlock.h>
17 #include <linux/delay.h>
18 #include <linux/list.h>
19 #include <linux/clk.h>
20 #include <linux/vmalloc.h>
21 #include <linux/string.h>
22 #include <linux/interrupt.h>
23 #include <linux/io.h>
24 #include <linux/module.h>
25
26 #include <mach/ipu.h>
27
28 #include "ipu_intern.h"
29
30 #define FS_VF_IN_VALID 0x00000002
31 #define FS_ENC_IN_VALID 0x00000001
32
33 static int ipu_disable_channel(struct idmac *idmac, struct idmac_channel *ichan,
34 bool wait_for_stop);
35
36 /*
37 * There can be only one, we could allocate it dynamically, but then we'd have
38 * to add an extra parameter to some functions, and use something as ugly as
39 * struct ipu *ipu = to_ipu(to_idmac(ichan->dma_chan.device));
40 * in the ISR
41 */
42 static struct ipu ipu_data;
43
44 #define to_ipu(id) container_of(id, struct ipu, idmac)
45
46 static u32 __idmac_read_icreg(struct ipu *ipu, unsigned long reg)
47 {
48 return __raw_readl(ipu->reg_ic + reg);
49 }
50
51 #define idmac_read_icreg(ipu, reg) __idmac_read_icreg(ipu, reg - IC_CONF)
52
53 static void __idmac_write_icreg(struct ipu *ipu, u32 value, unsigned long reg)
54 {
55 __raw_writel(value, ipu->reg_ic + reg);
56 }
57
58 #define idmac_write_icreg(ipu, v, reg) __idmac_write_icreg(ipu, v, reg - IC_CONF)
59
60 static u32 idmac_read_ipureg(struct ipu *ipu, unsigned long reg)
61 {
62 return __raw_readl(ipu->reg_ipu + reg);
63 }
64
65 static void idmac_write_ipureg(struct ipu *ipu, u32 value, unsigned long reg)
66 {
67 __raw_writel(value, ipu->reg_ipu + reg);
68 }
69
70 /*****************************************************************************
71 * IPU / IC common functions
72 */
73 static void dump_idmac_reg(struct ipu *ipu)
74 {
75 dev_dbg(ipu->dev, "IDMAC_CONF 0x%x, IC_CONF 0x%x, IDMAC_CHA_EN 0x%x, "
76 "IDMAC_CHA_PRI 0x%x, IDMAC_CHA_BUSY 0x%x\n",
77 idmac_read_icreg(ipu, IDMAC_CONF),
78 idmac_read_icreg(ipu, IC_CONF),
79 idmac_read_icreg(ipu, IDMAC_CHA_EN),
80 idmac_read_icreg(ipu, IDMAC_CHA_PRI),
81 idmac_read_icreg(ipu, IDMAC_CHA_BUSY));
82 dev_dbg(ipu->dev, "BUF0_RDY 0x%x, BUF1_RDY 0x%x, CUR_BUF 0x%x, "
83 "DB_MODE 0x%x, TASKS_STAT 0x%x\n",
84 idmac_read_ipureg(ipu, IPU_CHA_BUF0_RDY),
85 idmac_read_ipureg(ipu, IPU_CHA_BUF1_RDY),
86 idmac_read_ipureg(ipu, IPU_CHA_CUR_BUF),
87 idmac_read_ipureg(ipu, IPU_CHA_DB_MODE_SEL),
88 idmac_read_ipureg(ipu, IPU_TASKS_STAT));
89 }
90
91 static uint32_t bytes_per_pixel(enum pixel_fmt fmt)
92 {
93 switch (fmt) {
94 case IPU_PIX_FMT_GENERIC: /* generic data */
95 case IPU_PIX_FMT_RGB332:
96 case IPU_PIX_FMT_YUV420P:
97 case IPU_PIX_FMT_YUV422P:
98 default:
99 return 1;
100 case IPU_PIX_FMT_RGB565:
101 case IPU_PIX_FMT_YUYV:
102 case IPU_PIX_FMT_UYVY:
103 return 2;
104 case IPU_PIX_FMT_BGR24:
105 case IPU_PIX_FMT_RGB24:
106 return 3;
107 case IPU_PIX_FMT_GENERIC_32: /* generic data */
108 case IPU_PIX_FMT_BGR32:
109 case IPU_PIX_FMT_RGB32:
110 case IPU_PIX_FMT_ABGR32:
111 return 4;
112 }
113 }
114
115 /* Enable direct write to memory by the Camera Sensor Interface */
116 static void ipu_ic_enable_task(struct ipu *ipu, enum ipu_channel channel)
117 {
118 uint32_t ic_conf, mask;
119
120 switch (channel) {
121 case IDMAC_IC_0:
122 mask = IC_CONF_PRPENC_EN;
123 break;
124 case IDMAC_IC_7:
125 mask = IC_CONF_RWS_EN | IC_CONF_PRPENC_EN;
126 break;
127 default:
128 return;
129 }
130 ic_conf = idmac_read_icreg(ipu, IC_CONF) | mask;
131 idmac_write_icreg(ipu, ic_conf, IC_CONF);
132 }
133
134 /* Called under spin_lock_irqsave(&ipu_data.lock) */
135 static void ipu_ic_disable_task(struct ipu *ipu, enum ipu_channel channel)
136 {
137 uint32_t ic_conf, mask;
138
139 switch (channel) {
140 case IDMAC_IC_0:
141 mask = IC_CONF_PRPENC_EN;
142 break;
143 case IDMAC_IC_7:
144 mask = IC_CONF_RWS_EN | IC_CONF_PRPENC_EN;
145 break;
146 default:
147 return;
148 }
149 ic_conf = idmac_read_icreg(ipu, IC_CONF) & ~mask;
150 idmac_write_icreg(ipu, ic_conf, IC_CONF);
151 }
152
153 static uint32_t ipu_channel_status(struct ipu *ipu, enum ipu_channel channel)
154 {
155 uint32_t stat = TASK_STAT_IDLE;
156 uint32_t task_stat_reg = idmac_read_ipureg(ipu, IPU_TASKS_STAT);
157
158 switch (channel) {
159 case IDMAC_IC_7:
160 stat = (task_stat_reg & TSTAT_CSI2MEM_MASK) >>
161 TSTAT_CSI2MEM_OFFSET;
162 break;
163 case IDMAC_IC_0:
164 case IDMAC_SDC_0:
165 case IDMAC_SDC_1:
166 default:
167 break;
168 }
169 return stat;
170 }
171
172 struct chan_param_mem_planar {
173 /* Word 0 */
174 u32 xv:10;
175 u32 yv:10;
176 u32 xb:12;
177
178 u32 yb:12;
179 u32 res1:2;
180 u32 nsb:1;
181 u32 lnpb:6;
182 u32 ubo_l:11;
183
184 u32 ubo_h:15;
185 u32 vbo_l:17;
186
187 u32 vbo_h:9;
188 u32 res2:3;
189 u32 fw:12;
190 u32 fh_l:8;
191
192 u32 fh_h:4;
193 u32 res3:28;
194
195 /* Word 1 */
196 u32 eba0;
197
198 u32 eba1;
199
200 u32 bpp:3;
201 u32 sl:14;
202 u32 pfs:3;
203 u32 bam:3;
204 u32 res4:2;
205 u32 npb:6;
206 u32 res5:1;
207
208 u32 sat:2;
209 u32 res6:30;
210 } __attribute__ ((packed));
211
212 struct chan_param_mem_interleaved {
213 /* Word 0 */
214 u32 xv:10;
215 u32 yv:10;
216 u32 xb:12;
217
218 u32 yb:12;
219 u32 sce:1;
220 u32 res1:1;
221 u32 nsb:1;
222 u32 lnpb:6;
223 u32 sx:10;
224 u32 sy_l:1;
225
226 u32 sy_h:9;
227 u32 ns:10;
228 u32 sm:10;
229 u32 sdx_l:3;
230
231 u32 sdx_h:2;
232 u32 sdy:5;
233 u32 sdrx:1;
234 u32 sdry:1;
235 u32 sdr1:1;
236 u32 res2:2;
237 u32 fw:12;
238 u32 fh_l:8;
239
240 u32 fh_h:4;
241 u32 res3:28;
242
243 /* Word 1 */
244 u32 eba0;
245
246 u32 eba1;
247
248 u32 bpp:3;
249 u32 sl:14;
250 u32 pfs:3;
251 u32 bam:3;
252 u32 res4:2;
253 u32 npb:6;
254 u32 res5:1;
255
256 u32 sat:2;
257 u32 scc:1;
258 u32 ofs0:5;
259 u32 ofs1:5;
260 u32 ofs2:5;
261 u32 ofs3:5;
262 u32 wid0:3;
263 u32 wid1:3;
264 u32 wid2:3;
265
266 u32 wid3:3;
267 u32 dec_sel:1;
268 u32 res6:28;
269 } __attribute__ ((packed));
270
271 union chan_param_mem {
272 struct chan_param_mem_planar pp;
273 struct chan_param_mem_interleaved ip;
274 };
275
276 static void ipu_ch_param_set_plane_offset(union chan_param_mem *params,
277 u32 u_offset, u32 v_offset)
278 {
279 params->pp.ubo_l = u_offset & 0x7ff;
280 params->pp.ubo_h = u_offset >> 11;
281 params->pp.vbo_l = v_offset & 0x1ffff;
282 params->pp.vbo_h = v_offset >> 17;
283 }
284
285 static void ipu_ch_param_set_size(union chan_param_mem *params,
286 uint32_t pixel_fmt, uint16_t width,
287 uint16_t height, uint16_t stride)
288 {
289 u32 u_offset;
290 u32 v_offset;
291
292 params->pp.fw = width - 1;
293 params->pp.fh_l = height - 1;
294 params->pp.fh_h = (height - 1) >> 8;
295 params->pp.sl = stride - 1;
296
297 switch (pixel_fmt) {
298 case IPU_PIX_FMT_GENERIC:
299 /*Represents 8-bit Generic data */
300 params->pp.bpp = 3;
301 params->pp.pfs = 7;
302 params->pp.npb = 31;
303 params->pp.sat = 2; /* SAT = use 32-bit access */
304 break;
305 case IPU_PIX_FMT_GENERIC_32:
306 /*Represents 32-bit Generic data */
307 params->pp.bpp = 0;
308 params->pp.pfs = 7;
309 params->pp.npb = 7;
310 params->pp.sat = 2; /* SAT = use 32-bit access */
311 break;
312 case IPU_PIX_FMT_RGB565:
313 params->ip.bpp = 2;
314 params->ip.pfs = 4;
315 params->ip.npb = 7;
316 params->ip.sat = 2; /* SAT = 32-bit access */
317 params->ip.ofs0 = 0; /* Red bit offset */
318 params->ip.ofs1 = 5; /* Green bit offset */
319 params->ip.ofs2 = 11; /* Blue bit offset */
320 params->ip.ofs3 = 16; /* Alpha bit offset */
321 params->ip.wid0 = 4; /* Red bit width - 1 */
322 params->ip.wid1 = 5; /* Green bit width - 1 */
323 params->ip.wid2 = 4; /* Blue bit width - 1 */
324 break;
325 case IPU_PIX_FMT_BGR24:
326 params->ip.bpp = 1; /* 24 BPP & RGB PFS */
327 params->ip.pfs = 4;
328 params->ip.npb = 7;
329 params->ip.sat = 2; /* SAT = 32-bit access */
330 params->ip.ofs0 = 0; /* Red bit offset */
331 params->ip.ofs1 = 8; /* Green bit offset */
332 params->ip.ofs2 = 16; /* Blue bit offset */
333 params->ip.ofs3 = 24; /* Alpha bit offset */
334 params->ip.wid0 = 7; /* Red bit width - 1 */
335 params->ip.wid1 = 7; /* Green bit width - 1 */
336 params->ip.wid2 = 7; /* Blue bit width - 1 */
337 break;
338 case IPU_PIX_FMT_RGB24:
339 params->ip.bpp = 1; /* 24 BPP & RGB PFS */
340 params->ip.pfs = 4;
341 params->ip.npb = 7;
342 params->ip.sat = 2; /* SAT = 32-bit access */
343 params->ip.ofs0 = 16; /* Red bit offset */
344 params->ip.ofs1 = 8; /* Green bit offset */
345 params->ip.ofs2 = 0; /* Blue bit offset */
346 params->ip.ofs3 = 24; /* Alpha bit offset */
347 params->ip.wid0 = 7; /* Red bit width - 1 */
348 params->ip.wid1 = 7; /* Green bit width - 1 */
349 params->ip.wid2 = 7; /* Blue bit width - 1 */
350 break;
351 case IPU_PIX_FMT_BGRA32:
352 case IPU_PIX_FMT_BGR32:
353 case IPU_PIX_FMT_ABGR32:
354 params->ip.bpp = 0;
355 params->ip.pfs = 4;
356 params->ip.npb = 7;
357 params->ip.sat = 2; /* SAT = 32-bit access */
358 params->ip.ofs0 = 8; /* Red bit offset */
359 params->ip.ofs1 = 16; /* Green bit offset */
360 params->ip.ofs2 = 24; /* Blue bit offset */
361 params->ip.ofs3 = 0; /* Alpha bit offset */
362 params->ip.wid0 = 7; /* Red bit width - 1 */
363 params->ip.wid1 = 7; /* Green bit width - 1 */
364 params->ip.wid2 = 7; /* Blue bit width - 1 */
365 params->ip.wid3 = 7; /* Alpha bit width - 1 */
366 break;
367 case IPU_PIX_FMT_RGBA32:
368 case IPU_PIX_FMT_RGB32:
369 params->ip.bpp = 0;
370 params->ip.pfs = 4;
371 params->ip.npb = 7;
372 params->ip.sat = 2; /* SAT = 32-bit access */
373 params->ip.ofs0 = 24; /* Red bit offset */
374 params->ip.ofs1 = 16; /* Green bit offset */
375 params->ip.ofs2 = 8; /* Blue bit offset */
376 params->ip.ofs3 = 0; /* Alpha bit offset */
377 params->ip.wid0 = 7; /* Red bit width - 1 */
378 params->ip.wid1 = 7; /* Green bit width - 1 */
379 params->ip.wid2 = 7; /* Blue bit width - 1 */
380 params->ip.wid3 = 7; /* Alpha bit width - 1 */
381 break;
382 case IPU_PIX_FMT_UYVY:
383 params->ip.bpp = 2;
384 params->ip.pfs = 6;
385 params->ip.npb = 7;
386 params->ip.sat = 2; /* SAT = 32-bit access */
387 break;
388 case IPU_PIX_FMT_YUV420P2:
389 case IPU_PIX_FMT_YUV420P:
390 params->ip.bpp = 3;
391 params->ip.pfs = 3;
392 params->ip.npb = 7;
393 params->ip.sat = 2; /* SAT = 32-bit access */
394 u_offset = stride * height;
395 v_offset = u_offset + u_offset / 4;
396 ipu_ch_param_set_plane_offset(params, u_offset, v_offset);
397 break;
398 case IPU_PIX_FMT_YVU422P:
399 params->ip.bpp = 3;
400 params->ip.pfs = 2;
401 params->ip.npb = 7;
402 params->ip.sat = 2; /* SAT = 32-bit access */
403 v_offset = stride * height;
404 u_offset = v_offset + v_offset / 2;
405 ipu_ch_param_set_plane_offset(params, u_offset, v_offset);
406 break;
407 case IPU_PIX_FMT_YUV422P:
408 params->ip.bpp = 3;
409 params->ip.pfs = 2;
410 params->ip.npb = 7;
411 params->ip.sat = 2; /* SAT = 32-bit access */
412 u_offset = stride * height;
413 v_offset = u_offset + u_offset / 2;
414 ipu_ch_param_set_plane_offset(params, u_offset, v_offset);
415 break;
416 default:
417 dev_err(ipu_data.dev,
418 "mx3 ipu: unimplemented pixel format %d\n", pixel_fmt);
419 break;
420 }
421
422 params->pp.nsb = 1;
423 }
424
425 static void ipu_ch_param_set_burst_size(union chan_param_mem *params,
426 uint16_t burst_pixels)
427 {
428 params->pp.npb = burst_pixels - 1;
429 }
430
431 static void ipu_ch_param_set_buffer(union chan_param_mem *params,
432 dma_addr_t buf0, dma_addr_t buf1)
433 {
434 params->pp.eba0 = buf0;
435 params->pp.eba1 = buf1;
436 }
437
438 static void ipu_ch_param_set_rotation(union chan_param_mem *params,
439 enum ipu_rotate_mode rotate)
440 {
441 params->pp.bam = rotate;
442 }
443
444 static void ipu_write_param_mem(uint32_t addr, uint32_t *data,
445 uint32_t num_words)
446 {
447 for (; num_words > 0; num_words--) {
448 dev_dbg(ipu_data.dev,
449 "write param mem - addr = 0x%08X, data = 0x%08X\n",
450 addr, *data);
451 idmac_write_ipureg(&ipu_data, addr, IPU_IMA_ADDR);
452 idmac_write_ipureg(&ipu_data, *data++, IPU_IMA_DATA);
453 addr++;
454 if ((addr & 0x7) == 5) {
455 addr &= ~0x7; /* set to word 0 */
456 addr += 8; /* increment to next row */
457 }
458 }
459 }
460
461 static int calc_resize_coeffs(uint32_t in_size, uint32_t out_size,
462 uint32_t *resize_coeff,
463 uint32_t *downsize_coeff)
464 {
465 uint32_t temp_size;
466 uint32_t temp_downsize;
467
468 *resize_coeff = 1 << 13;
469 *downsize_coeff = 1 << 13;
470
471 /* Cannot downsize more than 8:1 */
472 if (out_size << 3 < in_size)
473 return -EINVAL;
474
475 /* compute downsizing coefficient */
476 temp_downsize = 0;
477 temp_size = in_size;
478 while (temp_size >= out_size * 2 && temp_downsize < 2) {
479 temp_size >>= 1;
480 temp_downsize++;
481 }
482 *downsize_coeff = temp_downsize;
483
484 /*
485 * compute resizing coefficient using the following formula:
486 * resize_coeff = M*(SI -1)/(SO - 1)
487 * where M = 2^13, SI - input size, SO - output size
488 */
489 *resize_coeff = (8192L * (temp_size - 1)) / (out_size - 1);
490 if (*resize_coeff >= 16384L) {
491 dev_err(ipu_data.dev, "Warning! Overflow on resize coeff.\n");
492 *resize_coeff = 0x3FFF;
493 }
494
495 dev_dbg(ipu_data.dev, "resizing from %u -> %u pixels, "
496 "downsize=%u, resize=%u.%lu (reg=%u)\n", in_size, out_size,
497 *downsize_coeff, *resize_coeff >= 8192L ? 1 : 0,
498 ((*resize_coeff & 0x1FFF) * 10000L) / 8192L, *resize_coeff);
499
500 return 0;
501 }
502
503 static enum ipu_color_space format_to_colorspace(enum pixel_fmt fmt)
504 {
505 switch (fmt) {
506 case IPU_PIX_FMT_RGB565:
507 case IPU_PIX_FMT_BGR24:
508 case IPU_PIX_FMT_RGB24:
509 case IPU_PIX_FMT_BGR32:
510 case IPU_PIX_FMT_RGB32:
511 return IPU_COLORSPACE_RGB;
512 default:
513 return IPU_COLORSPACE_YCBCR;
514 }
515 }
516
517 static int ipu_ic_init_prpenc(struct ipu *ipu,
518 union ipu_channel_param *params, bool src_is_csi)
519 {
520 uint32_t reg, ic_conf;
521 uint32_t downsize_coeff, resize_coeff;
522 enum ipu_color_space in_fmt, out_fmt;
523
524 /* Setup vertical resizing */
525 calc_resize_coeffs(params->video.in_height,
526 params->video.out_height,
527 &resize_coeff, &downsize_coeff);
528 reg = (downsize_coeff << 30) | (resize_coeff << 16);
529
530 /* Setup horizontal resizing */
531 calc_resize_coeffs(params->video.in_width,
532 params->video.out_width,
533 &resize_coeff, &downsize_coeff);
534 reg |= (downsize_coeff << 14) | resize_coeff;
535
536 /* Setup color space conversion */
537 in_fmt = format_to_colorspace(params->video.in_pixel_fmt);
538 out_fmt = format_to_colorspace(params->video.out_pixel_fmt);
539
540 /*
541 * Colourspace conversion unsupported yet - see _init_csc() in
542 * Freescale sources
543 */
544 if (in_fmt != out_fmt) {
545 dev_err(ipu->dev, "Colourspace conversion unsupported!\n");
546 return -EOPNOTSUPP;
547 }
548
549 idmac_write_icreg(ipu, reg, IC_PRP_ENC_RSC);
550
551 ic_conf = idmac_read_icreg(ipu, IC_CONF);
552
553 if (src_is_csi)
554 ic_conf &= ~IC_CONF_RWS_EN;
555 else
556 ic_conf |= IC_CONF_RWS_EN;
557
558 idmac_write_icreg(ipu, ic_conf, IC_CONF);
559
560 return 0;
561 }
562
563 static uint32_t dma_param_addr(uint32_t dma_ch)
564 {
565 /* Channel Parameter Memory */
566 return 0x10000 | (dma_ch << 4);
567 }
568
569 static void ipu_channel_set_priority(struct ipu *ipu, enum ipu_channel channel,
570 bool prio)
571 {
572 u32 reg = idmac_read_icreg(ipu, IDMAC_CHA_PRI);
573
574 if (prio)
575 reg |= 1UL << channel;
576 else
577 reg &= ~(1UL << channel);
578
579 idmac_write_icreg(ipu, reg, IDMAC_CHA_PRI);
580
581 dump_idmac_reg(ipu);
582 }
583
584 static uint32_t ipu_channel_conf_mask(enum ipu_channel channel)
585 {
586 uint32_t mask;
587
588 switch (channel) {
589 case IDMAC_IC_0:
590 case IDMAC_IC_7:
591 mask = IPU_CONF_CSI_EN | IPU_CONF_IC_EN;
592 break;
593 case IDMAC_SDC_0:
594 case IDMAC_SDC_1:
595 mask = IPU_CONF_SDC_EN | IPU_CONF_DI_EN;
596 break;
597 default:
598 mask = 0;
599 break;
600 }
601
602 return mask;
603 }
604
605 /**
606 * ipu_enable_channel() - enable an IPU channel.
607 * @idmac: IPU DMAC context.
608 * @ichan: IDMAC channel.
609 * @return: 0 on success or negative error code on failure.
610 */
611 static int ipu_enable_channel(struct idmac *idmac, struct idmac_channel *ichan)
612 {
613 struct ipu *ipu = to_ipu(idmac);
614 enum ipu_channel channel = ichan->dma_chan.chan_id;
615 uint32_t reg;
616 unsigned long flags;
617
618 spin_lock_irqsave(&ipu->lock, flags);
619
620 /* Reset to buffer 0 */
621 idmac_write_ipureg(ipu, 1UL << channel, IPU_CHA_CUR_BUF);
622 ichan->active_buffer = 0;
623 ichan->status = IPU_CHANNEL_ENABLED;
624
625 switch (channel) {
626 case IDMAC_SDC_0:
627 case IDMAC_SDC_1:
628 case IDMAC_IC_7:
629 ipu_channel_set_priority(ipu, channel, true);
630 default:
631 break;
632 }
633
634 reg = idmac_read_icreg(ipu, IDMAC_CHA_EN);
635
636 idmac_write_icreg(ipu, reg | (1UL << channel), IDMAC_CHA_EN);
637
638 ipu_ic_enable_task(ipu, channel);
639
640 spin_unlock_irqrestore(&ipu->lock, flags);
641 return 0;
642 }
643
644 /**
645 * ipu_init_channel_buffer() - initialize a buffer for logical IPU channel.
646 * @ichan: IDMAC channel.
647 * @pixel_fmt: pixel format of buffer. Pixel format is a FOURCC ASCII code.
648 * @width: width of buffer in pixels.
649 * @height: height of buffer in pixels.
650 * @stride: stride length of buffer in pixels.
651 * @rot_mode: rotation mode of buffer. A rotation setting other than
652 * IPU_ROTATE_VERT_FLIP should only be used for input buffers of
653 * rotation channels.
654 * @phyaddr_0: buffer 0 physical address.
655 * @phyaddr_1: buffer 1 physical address. Setting this to a value other than
656 * NULL enables double buffering mode.
657 * @return: 0 on success or negative error code on failure.
658 */
659 static int ipu_init_channel_buffer(struct idmac_channel *ichan,
660 enum pixel_fmt pixel_fmt,
661 uint16_t width, uint16_t height,
662 uint32_t stride,
663 enum ipu_rotate_mode rot_mode,
664 dma_addr_t phyaddr_0, dma_addr_t phyaddr_1)
665 {
666 enum ipu_channel channel = ichan->dma_chan.chan_id;
667 struct idmac *idmac = to_idmac(ichan->dma_chan.device);
668 struct ipu *ipu = to_ipu(idmac);
669 union chan_param_mem params = {};
670 unsigned long flags;
671 uint32_t reg;
672 uint32_t stride_bytes;
673
674 stride_bytes = stride * bytes_per_pixel(pixel_fmt);
675
676 if (stride_bytes % 4) {
677 dev_err(ipu->dev,
678 "Stride length must be 32-bit aligned, stride = %d, bytes = %d\n",
679 stride, stride_bytes);
680 return -EINVAL;
681 }
682
683 /* IC channel's stride must be a multiple of 8 pixels */
684 if ((channel <= IDMAC_IC_13) && (stride % 8)) {
685 dev_err(ipu->dev, "Stride must be 8 pixel multiple\n");
686 return -EINVAL;
687 }
688
689 /* Build parameter memory data for DMA channel */
690 ipu_ch_param_set_size(&params, pixel_fmt, width, height, stride_bytes);
691 ipu_ch_param_set_buffer(&params, phyaddr_0, phyaddr_1);
692 ipu_ch_param_set_rotation(&params, rot_mode);
693 /* Some channels (rotation) have restriction on burst length */
694 switch (channel) {
695 case IDMAC_IC_7: /* Hangs with burst 8, 16, other values
696 invalid - Table 44-30 */
697 /*
698 ipu_ch_param_set_burst_size(&params, 8);
699 */
700 break;
701 case IDMAC_SDC_0:
702 case IDMAC_SDC_1:
703 /* In original code only IPU_PIX_FMT_RGB565 was setting burst */
704 ipu_ch_param_set_burst_size(&params, 16);
705 break;
706 case IDMAC_IC_0:
707 default:
708 break;
709 }
710
711 spin_lock_irqsave(&ipu->lock, flags);
712
713 ipu_write_param_mem(dma_param_addr(channel), (uint32_t *)&params, 10);
714
715 reg = idmac_read_ipureg(ipu, IPU_CHA_DB_MODE_SEL);
716
717 if (phyaddr_1)
718 reg |= 1UL << channel;
719 else
720 reg &= ~(1UL << channel);
721
722 idmac_write_ipureg(ipu, reg, IPU_CHA_DB_MODE_SEL);
723
724 ichan->status = IPU_CHANNEL_READY;
725
726 spin_unlock_irqrestore(&ipu->lock, flags);
727
728 return 0;
729 }
730
731 /**
732 * ipu_select_buffer() - mark a channel's buffer as ready.
733 * @channel: channel ID.
734 * @buffer_n: buffer number to mark ready.
735 */
736 static void ipu_select_buffer(enum ipu_channel channel, int buffer_n)
737 {
738 /* No locking - this is a write-one-to-set register, cleared by IPU */
739 if (buffer_n == 0)
740 /* Mark buffer 0 as ready. */
741 idmac_write_ipureg(&ipu_data, 1UL << channel, IPU_CHA_BUF0_RDY);
742 else
743 /* Mark buffer 1 as ready. */
744 idmac_write_ipureg(&ipu_data, 1UL << channel, IPU_CHA_BUF1_RDY);
745 }
746
747 /**
748 * ipu_update_channel_buffer() - update physical address of a channel buffer.
749 * @ichan: IDMAC channel.
750 * @buffer_n: buffer number to update.
751 * 0 or 1 are the only valid values.
752 * @phyaddr: buffer physical address.
753 */
754 /* Called under spin_lock(_irqsave)(&ichan->lock) */
755 static void ipu_update_channel_buffer(struct idmac_channel *ichan,
756 int buffer_n, dma_addr_t phyaddr)
757 {
758 enum ipu_channel channel = ichan->dma_chan.chan_id;
759 uint32_t reg;
760 unsigned long flags;
761
762 spin_lock_irqsave(&ipu_data.lock, flags);
763
764 if (buffer_n == 0) {
765 reg = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF0_RDY);
766 if (reg & (1UL << channel)) {
767 ipu_ic_disable_task(&ipu_data, channel);
768 ichan->status = IPU_CHANNEL_READY;
769 }
770
771 /* 44.3.3.1.9 - Row Number 1 (WORD1, offset 0) */
772 idmac_write_ipureg(&ipu_data, dma_param_addr(channel) +
773 0x0008UL, IPU_IMA_ADDR);
774 idmac_write_ipureg(&ipu_data, phyaddr, IPU_IMA_DATA);
775 } else {
776 reg = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF1_RDY);
777 if (reg & (1UL << channel)) {
778 ipu_ic_disable_task(&ipu_data, channel);
779 ichan->status = IPU_CHANNEL_READY;
780 }
781
782 /* Check if double-buffering is already enabled */
783 reg = idmac_read_ipureg(&ipu_data, IPU_CHA_DB_MODE_SEL);
784
785 if (!(reg & (1UL << channel)))
786 idmac_write_ipureg(&ipu_data, reg | (1UL << channel),
787 IPU_CHA_DB_MODE_SEL);
788
789 /* 44.3.3.1.9 - Row Number 1 (WORD1, offset 1) */
790 idmac_write_ipureg(&ipu_data, dma_param_addr(channel) +
791 0x0009UL, IPU_IMA_ADDR);
792 idmac_write_ipureg(&ipu_data, phyaddr, IPU_IMA_DATA);
793 }
794
795 spin_unlock_irqrestore(&ipu_data.lock, flags);
796 }
797
798 /* Called under spin_lock_irqsave(&ichan->lock) */
799 static int ipu_submit_buffer(struct idmac_channel *ichan,
800 struct idmac_tx_desc *desc, struct scatterlist *sg, int buf_idx)
801 {
802 unsigned int chan_id = ichan->dma_chan.chan_id;
803 struct device *dev = &ichan->dma_chan.dev->device;
804
805 if (async_tx_test_ack(&desc->txd))
806 return -EINTR;
807
808 /*
809 * On first invocation this shouldn't be necessary, the call to
810 * ipu_init_channel_buffer() above will set addresses for us, so we
811 * could make it conditional on status >= IPU_CHANNEL_ENABLED, but
812 * doing it again shouldn't hurt either.
813 */
814 ipu_update_channel_buffer(ichan, buf_idx, sg_dma_address(sg));
815
816 ipu_select_buffer(chan_id, buf_idx);
817 dev_dbg(dev, "Updated sg %p on channel 0x%x buffer %d\n",
818 sg, chan_id, buf_idx);
819
820 return 0;
821 }
822
823 /* Called under spin_lock_irqsave(&ichan->lock) */
824 static int ipu_submit_channel_buffers(struct idmac_channel *ichan,
825 struct idmac_tx_desc *desc)
826 {
827 struct scatterlist *sg;
828 int i, ret = 0;
829
830 for (i = 0, sg = desc->sg; i < 2 && sg; i++) {
831 if (!ichan->sg[i]) {
832 ichan->sg[i] = sg;
833
834 ret = ipu_submit_buffer(ichan, desc, sg, i);
835 if (ret < 0)
836 return ret;
837
838 sg = sg_next(sg);
839 }
840 }
841
842 return ret;
843 }
844
845 static dma_cookie_t idmac_tx_submit(struct dma_async_tx_descriptor *tx)
846 {
847 struct idmac_tx_desc *desc = to_tx_desc(tx);
848 struct idmac_channel *ichan = to_idmac_chan(tx->chan);
849 struct idmac *idmac = to_idmac(tx->chan->device);
850 struct ipu *ipu = to_ipu(idmac);
851 struct device *dev = &ichan->dma_chan.dev->device;
852 dma_cookie_t cookie;
853 unsigned long flags;
854 int ret;
855
856 /* Sanity check */
857 if (!list_empty(&desc->list)) {
858 /* The descriptor doesn't belong to client */
859 dev_err(dev, "Descriptor %p not prepared!\n", tx);
860 return -EBUSY;
861 }
862
863 mutex_lock(&ichan->chan_mutex);
864
865 async_tx_clear_ack(tx);
866
867 if (ichan->status < IPU_CHANNEL_READY) {
868 struct idmac_video_param *video = &ichan->params.video;
869 /*
870 * Initial buffer assignment - the first two sg-entries from
871 * the descriptor will end up in the IDMAC buffers
872 */
873 dma_addr_t dma_1 = sg_is_last(desc->sg) ? 0 :
874 sg_dma_address(&desc->sg[1]);
875
876 WARN_ON(ichan->sg[0] || ichan->sg[1]);
877
878 cookie = ipu_init_channel_buffer(ichan,
879 video->out_pixel_fmt,
880 video->out_width,
881 video->out_height,
882 video->out_stride,
883 IPU_ROTATE_NONE,
884 sg_dma_address(&desc->sg[0]),
885 dma_1);
886 if (cookie < 0)
887 goto out;
888 }
889
890 dev_dbg(dev, "Submitting sg %p\n", &desc->sg[0]);
891
892 cookie = ichan->dma_chan.cookie;
893
894 if (++cookie < 0)
895 cookie = 1;
896
897 /* from dmaengine.h: "last cookie value returned to client" */
898 ichan->dma_chan.cookie = cookie;
899 tx->cookie = cookie;
900
901 /* ipu->lock can be taken under ichan->lock, but not v.v. */
902 spin_lock_irqsave(&ichan->lock, flags);
903
904 list_add_tail(&desc->list, &ichan->queue);
905 /* submit_buffers() atomically verifies and fills empty sg slots */
906 ret = ipu_submit_channel_buffers(ichan, desc);
907
908 spin_unlock_irqrestore(&ichan->lock, flags);
909
910 if (ret < 0) {
911 cookie = ret;
912 goto dequeue;
913 }
914
915 if (ichan->status < IPU_CHANNEL_ENABLED) {
916 ret = ipu_enable_channel(idmac, ichan);
917 if (ret < 0) {
918 cookie = ret;
919 goto dequeue;
920 }
921 }
922
923 dump_idmac_reg(ipu);
924
925 dequeue:
926 if (cookie < 0) {
927 spin_lock_irqsave(&ichan->lock, flags);
928 list_del_init(&desc->list);
929 spin_unlock_irqrestore(&ichan->lock, flags);
930 tx->cookie = cookie;
931 ichan->dma_chan.cookie = cookie;
932 }
933
934 out:
935 mutex_unlock(&ichan->chan_mutex);
936
937 return cookie;
938 }
939
940 /* Called with ichan->chan_mutex held */
941 static int idmac_desc_alloc(struct idmac_channel *ichan, int n)
942 {
943 struct idmac_tx_desc *desc = vmalloc(n * sizeof(struct idmac_tx_desc));
944 struct idmac *idmac = to_idmac(ichan->dma_chan.device);
945
946 if (!desc)
947 return -ENOMEM;
948
949 /* No interrupts, just disable the tasklet for a moment */
950 tasklet_disable(&to_ipu(idmac)->tasklet);
951
952 ichan->n_tx_desc = n;
953 ichan->desc = desc;
954 INIT_LIST_HEAD(&ichan->queue);
955 INIT_LIST_HEAD(&ichan->free_list);
956
957 while (n--) {
958 struct dma_async_tx_descriptor *txd = &desc->txd;
959
960 memset(txd, 0, sizeof(*txd));
961 dma_async_tx_descriptor_init(txd, &ichan->dma_chan);
962 txd->tx_submit = idmac_tx_submit;
963
964 list_add(&desc->list, &ichan->free_list);
965
966 desc++;
967 }
968
969 tasklet_enable(&to_ipu(idmac)->tasklet);
970
971 return 0;
972 }
973
974 /**
975 * ipu_init_channel() - initialize an IPU channel.
976 * @idmac: IPU DMAC context.
977 * @ichan: pointer to the channel object.
978 * @return 0 on success or negative error code on failure.
979 */
980 static int ipu_init_channel(struct idmac *idmac, struct idmac_channel *ichan)
981 {
982 union ipu_channel_param *params = &ichan->params;
983 uint32_t ipu_conf;
984 enum ipu_channel channel = ichan->dma_chan.chan_id;
985 unsigned long flags;
986 uint32_t reg;
987 struct ipu *ipu = to_ipu(idmac);
988 int ret = 0, n_desc = 0;
989
990 dev_dbg(ipu->dev, "init channel = %d\n", channel);
991
992 if (channel != IDMAC_SDC_0 && channel != IDMAC_SDC_1 &&
993 channel != IDMAC_IC_7)
994 return -EINVAL;
995
996 spin_lock_irqsave(&ipu->lock, flags);
997
998 switch (channel) {
999 case IDMAC_IC_7:
1000 n_desc = 16;
1001 reg = idmac_read_icreg(ipu, IC_CONF);
1002 idmac_write_icreg(ipu, reg & ~IC_CONF_CSI_MEM_WR_EN, IC_CONF);
1003 break;
1004 case IDMAC_IC_0:
1005 n_desc = 16;
1006 reg = idmac_read_ipureg(ipu, IPU_FS_PROC_FLOW);
1007 idmac_write_ipureg(ipu, reg & ~FS_ENC_IN_VALID, IPU_FS_PROC_FLOW);
1008 ret = ipu_ic_init_prpenc(ipu, params, true);
1009 break;
1010 case IDMAC_SDC_0:
1011 case IDMAC_SDC_1:
1012 n_desc = 4;
1013 default:
1014 break;
1015 }
1016
1017 ipu->channel_init_mask |= 1L << channel;
1018
1019 /* Enable IPU sub module */
1020 ipu_conf = idmac_read_ipureg(ipu, IPU_CONF) |
1021 ipu_channel_conf_mask(channel);
1022 idmac_write_ipureg(ipu, ipu_conf, IPU_CONF);
1023
1024 spin_unlock_irqrestore(&ipu->lock, flags);
1025
1026 if (n_desc && !ichan->desc)
1027 ret = idmac_desc_alloc(ichan, n_desc);
1028
1029 dump_idmac_reg(ipu);
1030
1031 return ret;
1032 }
1033
1034 /**
1035 * ipu_uninit_channel() - uninitialize an IPU channel.
1036 * @idmac: IPU DMAC context.
1037 * @ichan: pointer to the channel object.
1038 */
1039 static void ipu_uninit_channel(struct idmac *idmac, struct idmac_channel *ichan)
1040 {
1041 enum ipu_channel channel = ichan->dma_chan.chan_id;
1042 unsigned long flags;
1043 uint32_t reg;
1044 unsigned long chan_mask = 1UL << channel;
1045 uint32_t ipu_conf;
1046 struct ipu *ipu = to_ipu(idmac);
1047
1048 spin_lock_irqsave(&ipu->lock, flags);
1049
1050 if (!(ipu->channel_init_mask & chan_mask)) {
1051 dev_err(ipu->dev, "Channel already uninitialized %d\n",
1052 channel);
1053 spin_unlock_irqrestore(&ipu->lock, flags);
1054 return;
1055 }
1056
1057 /* Reset the double buffer */
1058 reg = idmac_read_ipureg(ipu, IPU_CHA_DB_MODE_SEL);
1059 idmac_write_ipureg(ipu, reg & ~chan_mask, IPU_CHA_DB_MODE_SEL);
1060
1061 ichan->sec_chan_en = false;
1062
1063 switch (channel) {
1064 case IDMAC_IC_7:
1065 reg = idmac_read_icreg(ipu, IC_CONF);
1066 idmac_write_icreg(ipu, reg & ~(IC_CONF_RWS_EN | IC_CONF_PRPENC_EN),
1067 IC_CONF);
1068 break;
1069 case IDMAC_IC_0:
1070 reg = idmac_read_icreg(ipu, IC_CONF);
1071 idmac_write_icreg(ipu, reg & ~(IC_CONF_PRPENC_EN | IC_CONF_PRPENC_CSC1),
1072 IC_CONF);
1073 break;
1074 case IDMAC_SDC_0:
1075 case IDMAC_SDC_1:
1076 default:
1077 break;
1078 }
1079
1080 ipu->channel_init_mask &= ~(1L << channel);
1081
1082 ipu_conf = idmac_read_ipureg(ipu, IPU_CONF) &
1083 ~ipu_channel_conf_mask(channel);
1084 idmac_write_ipureg(ipu, ipu_conf, IPU_CONF);
1085
1086 spin_unlock_irqrestore(&ipu->lock, flags);
1087
1088 ichan->n_tx_desc = 0;
1089 vfree(ichan->desc);
1090 ichan->desc = NULL;
1091 }
1092
1093 /**
1094 * ipu_disable_channel() - disable an IPU channel.
1095 * @idmac: IPU DMAC context.
1096 * @ichan: channel object pointer.
1097 * @wait_for_stop: flag to set whether to wait for channel end of frame or
1098 * return immediately.
1099 * @return: 0 on success or negative error code on failure.
1100 */
1101 static int ipu_disable_channel(struct idmac *idmac, struct idmac_channel *ichan,
1102 bool wait_for_stop)
1103 {
1104 enum ipu_channel channel = ichan->dma_chan.chan_id;
1105 struct ipu *ipu = to_ipu(idmac);
1106 uint32_t reg;
1107 unsigned long flags;
1108 unsigned long chan_mask = 1UL << channel;
1109 unsigned int timeout;
1110
1111 if (wait_for_stop && channel != IDMAC_SDC_1 && channel != IDMAC_SDC_0) {
1112 timeout = 40;
1113 /* This waiting always fails. Related to spurious irq problem */
1114 while ((idmac_read_icreg(ipu, IDMAC_CHA_BUSY) & chan_mask) ||
1115 (ipu_channel_status(ipu, channel) == TASK_STAT_ACTIVE)) {
1116 timeout--;
1117 msleep(10);
1118
1119 if (!timeout) {
1120 dev_dbg(ipu->dev,
1121 "Warning: timeout waiting for channel %u to "
1122 "stop: buf0_rdy = 0x%08X, buf1_rdy = 0x%08X, "
1123 "busy = 0x%08X, tstat = 0x%08X\n", channel,
1124 idmac_read_ipureg(ipu, IPU_CHA_BUF0_RDY),
1125 idmac_read_ipureg(ipu, IPU_CHA_BUF1_RDY),
1126 idmac_read_icreg(ipu, IDMAC_CHA_BUSY),
1127 idmac_read_ipureg(ipu, IPU_TASKS_STAT));
1128 break;
1129 }
1130 }
1131 dev_dbg(ipu->dev, "timeout = %d * 10ms\n", 40 - timeout);
1132 }
1133 /* SDC BG and FG must be disabled before DMA is disabled */
1134 if (wait_for_stop && (channel == IDMAC_SDC_0 ||
1135 channel == IDMAC_SDC_1)) {
1136 for (timeout = 5;
1137 timeout && !ipu_irq_status(ichan->eof_irq); timeout--)
1138 msleep(5);
1139 }
1140
1141 spin_lock_irqsave(&ipu->lock, flags);
1142
1143 /* Disable IC task */
1144 ipu_ic_disable_task(ipu, channel);
1145
1146 /* Disable DMA channel(s) */
1147 reg = idmac_read_icreg(ipu, IDMAC_CHA_EN);
1148 idmac_write_icreg(ipu, reg & ~chan_mask, IDMAC_CHA_EN);
1149
1150 spin_unlock_irqrestore(&ipu->lock, flags);
1151
1152 return 0;
1153 }
1154
1155 static struct scatterlist *idmac_sg_next(struct idmac_channel *ichan,
1156 struct idmac_tx_desc **desc, struct scatterlist *sg)
1157 {
1158 struct scatterlist *sgnew = sg ? sg_next(sg) : NULL;
1159
1160 if (sgnew)
1161 /* next sg-element in this list */
1162 return sgnew;
1163
1164 if ((*desc)->list.next == &ichan->queue)
1165 /* No more descriptors on the queue */
1166 return NULL;
1167
1168 /* Fetch next descriptor */
1169 *desc = list_entry((*desc)->list.next, struct idmac_tx_desc, list);
1170 return (*desc)->sg;
1171 }
1172
1173 /*
1174 * We have several possibilities here:
1175 * current BUF next BUF
1176 *
1177 * not last sg next not last sg
1178 * not last sg next last sg
1179 * last sg first sg from next descriptor
1180 * last sg NULL
1181 *
1182 * Besides, the descriptor queue might be empty or not. We process all these
1183 * cases carefully.
1184 */
1185 static irqreturn_t idmac_interrupt(int irq, void *dev_id)
1186 {
1187 struct idmac_channel *ichan = dev_id;
1188 struct device *dev = &ichan->dma_chan.dev->device;
1189 unsigned int chan_id = ichan->dma_chan.chan_id;
1190 struct scatterlist **sg, *sgnext, *sgnew = NULL;
1191 /* Next transfer descriptor */
1192 struct idmac_tx_desc *desc, *descnew;
1193 dma_async_tx_callback callback;
1194 void *callback_param;
1195 bool done = false;
1196 u32 ready0, ready1, curbuf, err;
1197 unsigned long flags;
1198
1199 /* IDMAC has cleared the respective BUFx_RDY bit, we manage the buffer */
1200
1201 dev_dbg(dev, "IDMAC irq %d, buf %d\n", irq, ichan->active_buffer);
1202
1203 spin_lock_irqsave(&ipu_data.lock, flags);
1204
1205 ready0 = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF0_RDY);
1206 ready1 = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF1_RDY);
1207 curbuf = idmac_read_ipureg(&ipu_data, IPU_CHA_CUR_BUF);
1208 err = idmac_read_ipureg(&ipu_data, IPU_INT_STAT_4);
1209
1210 if (err & (1 << chan_id)) {
1211 idmac_write_ipureg(&ipu_data, 1 << chan_id, IPU_INT_STAT_4);
1212 spin_unlock_irqrestore(&ipu_data.lock, flags);
1213 /*
1214 * Doing this
1215 * ichan->sg[0] = ichan->sg[1] = NULL;
1216 * you can force channel re-enable on the next tx_submit(), but
1217 * this is dirty - think about descriptors with multiple
1218 * sg elements.
1219 */
1220 dev_warn(dev, "NFB4EOF on channel %d, ready %x, %x, cur %x\n",
1221 chan_id, ready0, ready1, curbuf);
1222 return IRQ_HANDLED;
1223 }
1224 spin_unlock_irqrestore(&ipu_data.lock, flags);
1225
1226 /* Other interrupts do not interfere with this channel */
1227 spin_lock(&ichan->lock);
1228 if (unlikely((ichan->active_buffer && (ready1 >> chan_id) & 1) ||
1229 (!ichan->active_buffer && (ready0 >> chan_id) & 1)
1230 )) {
1231 spin_unlock(&ichan->lock);
1232 dev_dbg(dev,
1233 "IRQ with active buffer still ready on channel %x, "
1234 "active %d, ready %x, %x!\n", chan_id,
1235 ichan->active_buffer, ready0, ready1);
1236 return IRQ_NONE;
1237 }
1238
1239 if (unlikely(list_empty(&ichan->queue))) {
1240 ichan->sg[ichan->active_buffer] = NULL;
1241 spin_unlock(&ichan->lock);
1242 dev_err(dev,
1243 "IRQ without queued buffers on channel %x, active %d, "
1244 "ready %x, %x!\n", chan_id,
1245 ichan->active_buffer, ready0, ready1);
1246 return IRQ_NONE;
1247 }
1248
1249 /*
1250 * active_buffer is a software flag, it shows which buffer we are
1251 * currently expecting back from the hardware, IDMAC should be
1252 * processing the other buffer already
1253 */
1254 sg = &ichan->sg[ichan->active_buffer];
1255 sgnext = ichan->sg[!ichan->active_buffer];
1256
1257 if (!*sg) {
1258 spin_unlock(&ichan->lock);
1259 return IRQ_HANDLED;
1260 }
1261
1262 desc = list_entry(ichan->queue.next, struct idmac_tx_desc, list);
1263 descnew = desc;
1264
1265 dev_dbg(dev, "IDMAC irq %d, dma 0x%08x, next dma 0x%08x, current %d, curbuf 0x%08x\n",
1266 irq, sg_dma_address(*sg), sgnext ? sg_dma_address(sgnext) : 0, ichan->active_buffer, curbuf);
1267
1268 /* Find the descriptor of sgnext */
1269 sgnew = idmac_sg_next(ichan, &descnew, *sg);
1270 if (sgnext != sgnew)
1271 dev_err(dev, "Submitted buffer %p, next buffer %p\n", sgnext, sgnew);
1272
1273 /*
1274 * if sgnext == NULL sg must be the last element in a scatterlist and
1275 * queue must be empty
1276 */
1277 if (unlikely(!sgnext)) {
1278 if (!WARN_ON(sg_next(*sg)))
1279 dev_dbg(dev, "Underrun on channel %x\n", chan_id);
1280 ichan->sg[!ichan->active_buffer] = sgnew;
1281
1282 if (unlikely(sgnew)) {
1283 ipu_submit_buffer(ichan, descnew, sgnew, !ichan->active_buffer);
1284 } else {
1285 spin_lock_irqsave(&ipu_data.lock, flags);
1286 ipu_ic_disable_task(&ipu_data, chan_id);
1287 spin_unlock_irqrestore(&ipu_data.lock, flags);
1288 ichan->status = IPU_CHANNEL_READY;
1289 /* Continue to check for complete descriptor */
1290 }
1291 }
1292
1293 /* Calculate and submit the next sg element */
1294 sgnew = idmac_sg_next(ichan, &descnew, sgnew);
1295
1296 if (unlikely(!sg_next(*sg)) || !sgnext) {
1297 /*
1298 * Last element in scatterlist done, remove from the queue,
1299 * _init for debugging
1300 */
1301 list_del_init(&desc->list);
1302 done = true;
1303 }
1304
1305 *sg = sgnew;
1306
1307 if (likely(sgnew) &&
1308 ipu_submit_buffer(ichan, descnew, sgnew, ichan->active_buffer) < 0) {
1309 callback = descnew->txd.callback;
1310 callback_param = descnew->txd.callback_param;
1311 spin_unlock(&ichan->lock);
1312 if (callback)
1313 callback(callback_param);
1314 spin_lock(&ichan->lock);
1315 }
1316
1317 /* Flip the active buffer - even if update above failed */
1318 ichan->active_buffer = !ichan->active_buffer;
1319 if (done)
1320 ichan->completed = desc->txd.cookie;
1321
1322 callback = desc->txd.callback;
1323 callback_param = desc->txd.callback_param;
1324
1325 spin_unlock(&ichan->lock);
1326
1327 if (done && (desc->txd.flags & DMA_PREP_INTERRUPT) && callback)
1328 callback(callback_param);
1329
1330 return IRQ_HANDLED;
1331 }
1332
1333 static void ipu_gc_tasklet(unsigned long arg)
1334 {
1335 struct ipu *ipu = (struct ipu *)arg;
1336 int i;
1337
1338 for (i = 0; i < IPU_CHANNELS_NUM; i++) {
1339 struct idmac_channel *ichan = ipu->channel + i;
1340 struct idmac_tx_desc *desc;
1341 unsigned long flags;
1342 struct scatterlist *sg;
1343 int j, k;
1344
1345 for (j = 0; j < ichan->n_tx_desc; j++) {
1346 desc = ichan->desc + j;
1347 spin_lock_irqsave(&ichan->lock, flags);
1348 if (async_tx_test_ack(&desc->txd)) {
1349 list_move(&desc->list, &ichan->free_list);
1350 for_each_sg(desc->sg, sg, desc->sg_len, k) {
1351 if (ichan->sg[0] == sg)
1352 ichan->sg[0] = NULL;
1353 else if (ichan->sg[1] == sg)
1354 ichan->sg[1] = NULL;
1355 }
1356 async_tx_clear_ack(&desc->txd);
1357 }
1358 spin_unlock_irqrestore(&ichan->lock, flags);
1359 }
1360 }
1361 }
1362
1363 /* Allocate and initialise a transfer descriptor. */
1364 static struct dma_async_tx_descriptor *idmac_prep_slave_sg(struct dma_chan *chan,
1365 struct scatterlist *sgl, unsigned int sg_len,
1366 enum dma_data_direction direction, unsigned long tx_flags)
1367 {
1368 struct idmac_channel *ichan = to_idmac_chan(chan);
1369 struct idmac_tx_desc *desc = NULL;
1370 struct dma_async_tx_descriptor *txd = NULL;
1371 unsigned long flags;
1372
1373 /* We only can handle these three channels so far */
1374 if (chan->chan_id != IDMAC_SDC_0 && chan->chan_id != IDMAC_SDC_1 &&
1375 chan->chan_id != IDMAC_IC_7)
1376 return NULL;
1377
1378 if (direction != DMA_FROM_DEVICE && direction != DMA_TO_DEVICE) {
1379 dev_err(chan->device->dev, "Invalid DMA direction %d!\n", direction);
1380 return NULL;
1381 }
1382
1383 mutex_lock(&ichan->chan_mutex);
1384
1385 spin_lock_irqsave(&ichan->lock, flags);
1386 if (!list_empty(&ichan->free_list)) {
1387 desc = list_entry(ichan->free_list.next,
1388 struct idmac_tx_desc, list);
1389
1390 list_del_init(&desc->list);
1391
1392 desc->sg_len = sg_len;
1393 desc->sg = sgl;
1394 txd = &desc->txd;
1395 txd->flags = tx_flags;
1396 }
1397 spin_unlock_irqrestore(&ichan->lock, flags);
1398
1399 mutex_unlock(&ichan->chan_mutex);
1400
1401 tasklet_schedule(&to_ipu(to_idmac(chan->device))->tasklet);
1402
1403 return txd;
1404 }
1405
1406 /* Re-select the current buffer and re-activate the channel */
1407 static void idmac_issue_pending(struct dma_chan *chan)
1408 {
1409 struct idmac_channel *ichan = to_idmac_chan(chan);
1410 struct idmac *idmac = to_idmac(chan->device);
1411 struct ipu *ipu = to_ipu(idmac);
1412 unsigned long flags;
1413
1414 /* This is not always needed, but doesn't hurt either */
1415 spin_lock_irqsave(&ipu->lock, flags);
1416 ipu_select_buffer(chan->chan_id, ichan->active_buffer);
1417 spin_unlock_irqrestore(&ipu->lock, flags);
1418
1419 /*
1420 * Might need to perform some parts of initialisation from
1421 * ipu_enable_channel(), but not all, we do not want to reset to buffer
1422 * 0, don't need to set priority again either, but re-enabling the task
1423 * and the channel might be a good idea.
1424 */
1425 }
1426
1427 static int __idmac_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1428 unsigned long arg)
1429 {
1430 struct idmac_channel *ichan = to_idmac_chan(chan);
1431 struct idmac *idmac = to_idmac(chan->device);
1432 unsigned long flags;
1433 int i;
1434
1435 /* Only supports DMA_TERMINATE_ALL */
1436 if (cmd != DMA_TERMINATE_ALL)
1437 return -ENXIO;
1438
1439 ipu_disable_channel(idmac, ichan,
1440 ichan->status >= IPU_CHANNEL_ENABLED);
1441
1442 tasklet_disable(&to_ipu(idmac)->tasklet);
1443
1444 /* ichan->queue is modified in ISR, have to spinlock */
1445 spin_lock_irqsave(&ichan->lock, flags);
1446 list_splice_init(&ichan->queue, &ichan->free_list);
1447
1448 if (ichan->desc)
1449 for (i = 0; i < ichan->n_tx_desc; i++) {
1450 struct idmac_tx_desc *desc = ichan->desc + i;
1451 if (list_empty(&desc->list))
1452 /* Descriptor was prepared, but not submitted */
1453 list_add(&desc->list, &ichan->free_list);
1454
1455 async_tx_clear_ack(&desc->txd);
1456 }
1457
1458 ichan->sg[0] = NULL;
1459 ichan->sg[1] = NULL;
1460 spin_unlock_irqrestore(&ichan->lock, flags);
1461
1462 tasklet_enable(&to_ipu(idmac)->tasklet);
1463
1464 ichan->status = IPU_CHANNEL_INITIALIZED;
1465
1466 return 0;
1467 }
1468
1469 static int idmac_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1470 unsigned long arg)
1471 {
1472 struct idmac_channel *ichan = to_idmac_chan(chan);
1473 int ret;
1474
1475 mutex_lock(&ichan->chan_mutex);
1476
1477 ret = __idmac_control(chan, cmd, arg);
1478
1479 mutex_unlock(&ichan->chan_mutex);
1480
1481 return ret;
1482 }
1483
1484 #ifdef DEBUG
1485 static irqreturn_t ic_sof_irq(int irq, void *dev_id)
1486 {
1487 struct idmac_channel *ichan = dev_id;
1488 printk(KERN_DEBUG "Got SOF IRQ %d on Channel %d\n",
1489 irq, ichan->dma_chan.chan_id);
1490 disable_irq_nosync(irq);
1491 return IRQ_HANDLED;
1492 }
1493
1494 static irqreturn_t ic_eof_irq(int irq, void *dev_id)
1495 {
1496 struct idmac_channel *ichan = dev_id;
1497 printk(KERN_DEBUG "Got EOF IRQ %d on Channel %d\n",
1498 irq, ichan->dma_chan.chan_id);
1499 disable_irq_nosync(irq);
1500 return IRQ_HANDLED;
1501 }
1502
1503 static int ic_sof = -EINVAL, ic_eof = -EINVAL;
1504 #endif
1505
1506 static int idmac_alloc_chan_resources(struct dma_chan *chan)
1507 {
1508 struct idmac_channel *ichan = to_idmac_chan(chan);
1509 struct idmac *idmac = to_idmac(chan->device);
1510 int ret;
1511
1512 /* dmaengine.c now guarantees to only offer free channels */
1513 BUG_ON(chan->client_count > 1);
1514 WARN_ON(ichan->status != IPU_CHANNEL_FREE);
1515
1516 chan->cookie = 1;
1517 ichan->completed = -ENXIO;
1518
1519 ret = ipu_irq_map(chan->chan_id);
1520 if (ret < 0)
1521 goto eimap;
1522
1523 ichan->eof_irq = ret;
1524
1525 /*
1526 * Important to first disable the channel, because maybe someone
1527 * used it before us, e.g., the bootloader
1528 */
1529 ipu_disable_channel(idmac, ichan, true);
1530
1531 ret = ipu_init_channel(idmac, ichan);
1532 if (ret < 0)
1533 goto eichan;
1534
1535 ret = request_irq(ichan->eof_irq, idmac_interrupt, 0,
1536 ichan->eof_name, ichan);
1537 if (ret < 0)
1538 goto erirq;
1539
1540 #ifdef DEBUG
1541 if (chan->chan_id == IDMAC_IC_7) {
1542 ic_sof = ipu_irq_map(69);
1543 if (ic_sof > 0)
1544 request_irq(ic_sof, ic_sof_irq, 0, "IC SOF", ichan);
1545 ic_eof = ipu_irq_map(70);
1546 if (ic_eof > 0)
1547 request_irq(ic_eof, ic_eof_irq, 0, "IC EOF", ichan);
1548 }
1549 #endif
1550
1551 ichan->status = IPU_CHANNEL_INITIALIZED;
1552
1553 dev_dbg(&chan->dev->device, "Found channel 0x%x, irq %d\n",
1554 chan->chan_id, ichan->eof_irq);
1555
1556 return ret;
1557
1558 erirq:
1559 ipu_uninit_channel(idmac, ichan);
1560 eichan:
1561 ipu_irq_unmap(chan->chan_id);
1562 eimap:
1563 return ret;
1564 }
1565
1566 static void idmac_free_chan_resources(struct dma_chan *chan)
1567 {
1568 struct idmac_channel *ichan = to_idmac_chan(chan);
1569 struct idmac *idmac = to_idmac(chan->device);
1570
1571 mutex_lock(&ichan->chan_mutex);
1572
1573 __idmac_control(chan, DMA_TERMINATE_ALL, 0);
1574
1575 if (ichan->status > IPU_CHANNEL_FREE) {
1576 #ifdef DEBUG
1577 if (chan->chan_id == IDMAC_IC_7) {
1578 if (ic_sof > 0) {
1579 free_irq(ic_sof, ichan);
1580 ipu_irq_unmap(69);
1581 ic_sof = -EINVAL;
1582 }
1583 if (ic_eof > 0) {
1584 free_irq(ic_eof, ichan);
1585 ipu_irq_unmap(70);
1586 ic_eof = -EINVAL;
1587 }
1588 }
1589 #endif
1590 free_irq(ichan->eof_irq, ichan);
1591 ipu_irq_unmap(chan->chan_id);
1592 }
1593
1594 ichan->status = IPU_CHANNEL_FREE;
1595
1596 ipu_uninit_channel(idmac, ichan);
1597
1598 mutex_unlock(&ichan->chan_mutex);
1599
1600 tasklet_schedule(&to_ipu(idmac)->tasklet);
1601 }
1602
1603 static enum dma_status idmac_tx_status(struct dma_chan *chan,
1604 dma_cookie_t cookie, struct dma_tx_state *txstate)
1605 {
1606 struct idmac_channel *ichan = to_idmac_chan(chan);
1607
1608 dma_set_tx_state(txstate, ichan->completed, chan->cookie, 0);
1609 if (cookie != chan->cookie)
1610 return DMA_ERROR;
1611 return DMA_SUCCESS;
1612 }
1613
1614 static int __init ipu_idmac_init(struct ipu *ipu)
1615 {
1616 struct idmac *idmac = &ipu->idmac;
1617 struct dma_device *dma = &idmac->dma;
1618 int i;
1619
1620 dma_cap_set(DMA_SLAVE, dma->cap_mask);
1621 dma_cap_set(DMA_PRIVATE, dma->cap_mask);
1622
1623 /* Compulsory common fields */
1624 dma->dev = ipu->dev;
1625 dma->device_alloc_chan_resources = idmac_alloc_chan_resources;
1626 dma->device_free_chan_resources = idmac_free_chan_resources;
1627 dma->device_tx_status = idmac_tx_status;
1628 dma->device_issue_pending = idmac_issue_pending;
1629
1630 /* Compulsory for DMA_SLAVE fields */
1631 dma->device_prep_slave_sg = idmac_prep_slave_sg;
1632 dma->device_control = idmac_control;
1633
1634 INIT_LIST_HEAD(&dma->channels);
1635 for (i = 0; i < IPU_CHANNELS_NUM; i++) {
1636 struct idmac_channel *ichan = ipu->channel + i;
1637 struct dma_chan *dma_chan = &ichan->dma_chan;
1638
1639 spin_lock_init(&ichan->lock);
1640 mutex_init(&ichan->chan_mutex);
1641
1642 ichan->status = IPU_CHANNEL_FREE;
1643 ichan->sec_chan_en = false;
1644 ichan->completed = -ENXIO;
1645 snprintf(ichan->eof_name, sizeof(ichan->eof_name), "IDMAC EOF %d", i);
1646
1647 dma_chan->device = &idmac->dma;
1648 dma_chan->cookie = 1;
1649 dma_chan->chan_id = i;
1650 list_add_tail(&dma_chan->device_node, &dma->channels);
1651 }
1652
1653 idmac_write_icreg(ipu, 0x00000070, IDMAC_CONF);
1654
1655 return dma_async_device_register(&idmac->dma);
1656 }
1657
1658 static void __exit ipu_idmac_exit(struct ipu *ipu)
1659 {
1660 int i;
1661 struct idmac *idmac = &ipu->idmac;
1662
1663 for (i = 0; i < IPU_CHANNELS_NUM; i++) {
1664 struct idmac_channel *ichan = ipu->channel + i;
1665
1666 idmac_control(&ichan->dma_chan, DMA_TERMINATE_ALL, 0);
1667 idmac_prep_slave_sg(&ichan->dma_chan, NULL, 0, DMA_NONE, 0);
1668 }
1669
1670 dma_async_device_unregister(&idmac->dma);
1671 }
1672
1673 /*****************************************************************************
1674 * IPU common probe / remove
1675 */
1676
1677 static int __init ipu_probe(struct platform_device *pdev)
1678 {
1679 struct ipu_platform_data *pdata = pdev->dev.platform_data;
1680 struct resource *mem_ipu, *mem_ic;
1681 int ret;
1682
1683 spin_lock_init(&ipu_data.lock);
1684
1685 mem_ipu = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1686 mem_ic = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1687 if (!pdata || !mem_ipu || !mem_ic)
1688 return -EINVAL;
1689
1690 ipu_data.dev = &pdev->dev;
1691
1692 platform_set_drvdata(pdev, &ipu_data);
1693
1694 ret = platform_get_irq(pdev, 0);
1695 if (ret < 0)
1696 goto err_noirq;
1697
1698 ipu_data.irq_fn = ret;
1699 ret = platform_get_irq(pdev, 1);
1700 if (ret < 0)
1701 goto err_noirq;
1702
1703 ipu_data.irq_err = ret;
1704 ipu_data.irq_base = pdata->irq_base;
1705
1706 dev_dbg(&pdev->dev, "fn irq %u, err irq %u, irq-base %u\n",
1707 ipu_data.irq_fn, ipu_data.irq_err, ipu_data.irq_base);
1708
1709 /* Remap IPU common registers */
1710 ipu_data.reg_ipu = ioremap(mem_ipu->start, resource_size(mem_ipu));
1711 if (!ipu_data.reg_ipu) {
1712 ret = -ENOMEM;
1713 goto err_ioremap_ipu;
1714 }
1715
1716 /* Remap Image Converter and Image DMA Controller registers */
1717 ipu_data.reg_ic = ioremap(mem_ic->start, resource_size(mem_ic));
1718 if (!ipu_data.reg_ic) {
1719 ret = -ENOMEM;
1720 goto err_ioremap_ic;
1721 }
1722
1723 /* Get IPU clock */
1724 ipu_data.ipu_clk = clk_get(&pdev->dev, NULL);
1725 if (IS_ERR(ipu_data.ipu_clk)) {
1726 ret = PTR_ERR(ipu_data.ipu_clk);
1727 goto err_clk_get;
1728 }
1729
1730 /* Make sure IPU HSP clock is running */
1731 clk_enable(ipu_data.ipu_clk);
1732
1733 /* Disable all interrupts */
1734 idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_1);
1735 idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_2);
1736 idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_3);
1737 idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_4);
1738 idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_5);
1739
1740 dev_dbg(&pdev->dev, "%s @ 0x%08lx, fn irq %u, err irq %u\n", pdev->name,
1741 (unsigned long)mem_ipu->start, ipu_data.irq_fn, ipu_data.irq_err);
1742
1743 ret = ipu_irq_attach_irq(&ipu_data, pdev);
1744 if (ret < 0)
1745 goto err_attach_irq;
1746
1747 /* Initialize DMA engine */
1748 ret = ipu_idmac_init(&ipu_data);
1749 if (ret < 0)
1750 goto err_idmac_init;
1751
1752 tasklet_init(&ipu_data.tasklet, ipu_gc_tasklet, (unsigned long)&ipu_data);
1753
1754 ipu_data.dev = &pdev->dev;
1755
1756 dev_dbg(ipu_data.dev, "IPU initialized\n");
1757
1758 return 0;
1759
1760 err_idmac_init:
1761 err_attach_irq:
1762 ipu_irq_detach_irq(&ipu_data, pdev);
1763 clk_disable(ipu_data.ipu_clk);
1764 clk_put(ipu_data.ipu_clk);
1765 err_clk_get:
1766 iounmap(ipu_data.reg_ic);
1767 err_ioremap_ic:
1768 iounmap(ipu_data.reg_ipu);
1769 err_ioremap_ipu:
1770 err_noirq:
1771 dev_err(&pdev->dev, "Failed to probe IPU: %d\n", ret);
1772 return ret;
1773 }
1774
1775 static int __exit ipu_remove(struct platform_device *pdev)
1776 {
1777 struct ipu *ipu = platform_get_drvdata(pdev);
1778
1779 ipu_idmac_exit(ipu);
1780 ipu_irq_detach_irq(ipu, pdev);
1781 clk_disable(ipu->ipu_clk);
1782 clk_put(ipu->ipu_clk);
1783 iounmap(ipu->reg_ic);
1784 iounmap(ipu->reg_ipu);
1785 tasklet_kill(&ipu->tasklet);
1786 platform_set_drvdata(pdev, NULL);
1787
1788 return 0;
1789 }
1790
1791 /*
1792 * We need two MEM resources - with IPU-common and Image Converter registers,
1793 * including PF_CONF and IDMAC_* registers, and two IRQs - function and error
1794 */
1795 static struct platform_driver ipu_platform_driver = {
1796 .driver = {
1797 .name = "ipu-core",
1798 .owner = THIS_MODULE,
1799 },
1800 .remove = __exit_p(ipu_remove),
1801 };
1802
1803 static int __init ipu_init(void)
1804 {
1805 return platform_driver_probe(&ipu_platform_driver, ipu_probe);
1806 }
1807 subsys_initcall(ipu_init);
1808
1809 MODULE_DESCRIPTION("IPU core driver");
1810 MODULE_LICENSE("GPL v2");
1811 MODULE_AUTHOR("Guennadi Liakhovetski <lg@denx.de>");
1812 MODULE_ALIAS("platform:ipu-core");
linux-next