?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Add linux-next specific files for 20110831
[linux-2.6/next.git] / drivers / gpu / drm / radeon / radeon_encoders.c
blob319d85d7e759b4f0599f2c5df2b9182568bd993d
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include "drmP.h"
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
29 #include "radeon.h"
30 #include "atom.h"
31
32 extern int atom_debug;
33
34 /* evil but including atombios.h is much worse */
35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 struct drm_display_mode *mode);
37
38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
39 {
40 struct drm_device *dev = encoder->dev;
41 struct radeon_device *rdev = dev->dev_private;
42 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
43 struct drm_encoder *clone_encoder;
44 uint32_t index_mask = 0;
45 int count;
46
47 /* DIG routing gets problematic */
48 if (rdev->family >= CHIP_R600)
49 return index_mask;
50 /* LVDS/TV are too wacky */
51 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
52 return index_mask;
53 /* DVO requires 2x ppll clocks depending on tmds chip */
54 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
55 return index_mask;
56
57 count = -1;
58 list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
59 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
60 count++;
61
62 if (clone_encoder == encoder)
63 continue;
64 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
65 continue;
66 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
67 continue;
68 else
69 index_mask |= (1 << count);
70 }
71 return index_mask;
72 }
73
74 void radeon_setup_encoder_clones(struct drm_device *dev)
75 {
76 struct drm_encoder *encoder;
77
78 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
79 encoder->possible_clones = radeon_encoder_clones(encoder);
80 }
81 }
82
83 uint32_t
84 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
85 {
86 struct radeon_device *rdev = dev->dev_private;
87 uint32_t ret = 0;
88
89 switch (supported_device) {
90 case ATOM_DEVICE_CRT1_SUPPORT:
91 case ATOM_DEVICE_TV1_SUPPORT:
92 case ATOM_DEVICE_TV2_SUPPORT:
93 case ATOM_DEVICE_CRT2_SUPPORT:
94 case ATOM_DEVICE_CV_SUPPORT:
95 switch (dac) {
96 case 1: /* dac a */
97 if ((rdev->family == CHIP_RS300) ||
98 (rdev->family == CHIP_RS400) ||
99 (rdev->family == CHIP_RS480))
100 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
101 else if (ASIC_IS_AVIVO(rdev))
102 ret = ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1;
103 else
104 ret = ENCODER_INTERNAL_DAC1_ENUM_ID1;
105 break;
106 case 2: /* dac b */
107 if (ASIC_IS_AVIVO(rdev))
108 ret = ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1;
109 else {
110 /*if (rdev->family == CHIP_R200)
111 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
112 else*/
113 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
114 }
115 break;
116 case 3: /* external dac */
117 if (ASIC_IS_AVIVO(rdev))
118 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
119 else
120 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
121 break;
122 }
123 break;
124 case ATOM_DEVICE_LCD1_SUPPORT:
125 if (ASIC_IS_AVIVO(rdev))
126 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
127 else
128 ret = ENCODER_INTERNAL_LVDS_ENUM_ID1;
129 break;
130 case ATOM_DEVICE_DFP1_SUPPORT:
131 if ((rdev->family == CHIP_RS300) ||
132 (rdev->family == CHIP_RS400) ||
133 (rdev->family == CHIP_RS480))
134 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
135 else if (ASIC_IS_AVIVO(rdev))
136 ret = ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1;
137 else
138 ret = ENCODER_INTERNAL_TMDS1_ENUM_ID1;
139 break;
140 case ATOM_DEVICE_LCD2_SUPPORT:
141 case ATOM_DEVICE_DFP2_SUPPORT:
142 if ((rdev->family == CHIP_RS600) ||
143 (rdev->family == CHIP_RS690) ||
144 (rdev->family == CHIP_RS740))
145 ret = ENCODER_INTERNAL_DDI_ENUM_ID1;
146 else if (ASIC_IS_AVIVO(rdev))
147 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
148 else
149 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
150 break;
151 case ATOM_DEVICE_DFP3_SUPPORT:
152 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
153 break;
154 }
155
156 return ret;
157 }
158
159 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
160 {
161 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
162 switch (radeon_encoder->encoder_id) {
163 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
164 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
165 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
166 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
167 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
168 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
169 case ENCODER_OBJECT_ID_INTERNAL_DDI:
170 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
171 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
172 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
173 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
174 return true;
175 default:
176 return false;
177 }
178 }
179
180 void
181 radeon_link_encoder_connector(struct drm_device *dev)
182 {
183 struct drm_connector *connector;
184 struct radeon_connector *radeon_connector;
185 struct drm_encoder *encoder;
186 struct radeon_encoder *radeon_encoder;
187
188 /* walk the list and link encoders to connectors */
189 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
190 radeon_connector = to_radeon_connector(connector);
191 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
192 radeon_encoder = to_radeon_encoder(encoder);
193 if (radeon_encoder->devices & radeon_connector->devices)
194 drm_mode_connector_attach_encoder(connector, encoder);
195 }
196 }
197 }
198
199 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
200 {
201 struct drm_device *dev = encoder->dev;
202 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
203 struct drm_connector *connector;
204
205 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
206 if (connector->encoder == encoder) {
207 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
208 radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
209 DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
210 radeon_encoder->active_device, radeon_encoder->devices,
211 radeon_connector->devices, encoder->encoder_type);
212 }
213 }
214 }
215
216 struct drm_connector *
217 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
218 {
219 struct drm_device *dev = encoder->dev;
220 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
221 struct drm_connector *connector;
222 struct radeon_connector *radeon_connector;
223
224 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
225 radeon_connector = to_radeon_connector(connector);
226 if (radeon_encoder->active_device & radeon_connector->devices)
227 return connector;
228 }
229 return NULL;
230 }
231
232 static struct drm_connector *
233 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder)
234 {
235 struct drm_device *dev = encoder->dev;
236 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
237 struct drm_connector *connector;
238 struct radeon_connector *radeon_connector;
239
240 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
241 radeon_connector = to_radeon_connector(connector);
242 if (radeon_encoder->devices & radeon_connector->devices)
243 return connector;
244 }
245 return NULL;
246 }
247
248 struct drm_encoder *radeon_atom_get_external_encoder(struct drm_encoder *encoder)
249 {
250 struct drm_device *dev = encoder->dev;
251 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
252 struct drm_encoder *other_encoder;
253 struct radeon_encoder *other_radeon_encoder;
254
255 if (radeon_encoder->is_ext_encoder)
256 return NULL;
257
258 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
259 if (other_encoder == encoder)
260 continue;
261 other_radeon_encoder = to_radeon_encoder(other_encoder);
262 if (other_radeon_encoder->is_ext_encoder &&
263 (radeon_encoder->devices & other_radeon_encoder->devices))
264 return other_encoder;
265 }
266 return NULL;
267 }
268
269 bool radeon_encoder_is_dp_bridge(struct drm_encoder *encoder)
270 {
271 struct drm_encoder *other_encoder = radeon_atom_get_external_encoder(encoder);
272
273 if (other_encoder) {
274 struct radeon_encoder *radeon_encoder = to_radeon_encoder(other_encoder);
275
276 switch (radeon_encoder->encoder_id) {
277 case ENCODER_OBJECT_ID_TRAVIS:
278 case ENCODER_OBJECT_ID_NUTMEG:
279 return true;
280 default:
281 return false;
282 }
283 }
284
285 return false;
286 }
287
288 void radeon_panel_mode_fixup(struct drm_encoder *encoder,
289 struct drm_display_mode *adjusted_mode)
290 {
291 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
292 struct drm_device *dev = encoder->dev;
293 struct radeon_device *rdev = dev->dev_private;
294 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
295 unsigned hblank = native_mode->htotal - native_mode->hdisplay;
296 unsigned vblank = native_mode->vtotal - native_mode->vdisplay;
297 unsigned hover = native_mode->hsync_start - native_mode->hdisplay;
298 unsigned vover = native_mode->vsync_start - native_mode->vdisplay;
299 unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start;
300 unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start;
301
302 adjusted_mode->clock = native_mode->clock;
303 adjusted_mode->flags = native_mode->flags;
304
305 if (ASIC_IS_AVIVO(rdev)) {
306 adjusted_mode->hdisplay = native_mode->hdisplay;
307 adjusted_mode->vdisplay = native_mode->vdisplay;
308 }
309
310 adjusted_mode->htotal = native_mode->hdisplay + hblank;
311 adjusted_mode->hsync_start = native_mode->hdisplay + hover;
312 adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width;
313
314 adjusted_mode->vtotal = native_mode->vdisplay + vblank;
315 adjusted_mode->vsync_start = native_mode->vdisplay + vover;
316 adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width;
317
318 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
319
320 if (ASIC_IS_AVIVO(rdev)) {
321 adjusted_mode->crtc_hdisplay = native_mode->hdisplay;
322 adjusted_mode->crtc_vdisplay = native_mode->vdisplay;
323 }
324
325 adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank;
326 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover;
327 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width;
328
329 adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank;
330 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover;
331 adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width;
332
333 }
334
335 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
336 struct drm_display_mode *mode,
337 struct drm_display_mode *adjusted_mode)
338 {
339 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
340 struct drm_device *dev = encoder->dev;
341 struct radeon_device *rdev = dev->dev_private;
342
343 /* set the active encoder to connector routing */
344 radeon_encoder_set_active_device(encoder);
345 drm_mode_set_crtcinfo(adjusted_mode, 0);
346
347 /* hw bug */
348 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
349 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
350 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
351
352 /* get the native mode for LVDS */
353 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
354 radeon_panel_mode_fixup(encoder, adjusted_mode);
355
356 /* get the native mode for TV */
357 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
358 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
359 if (tv_dac) {
360 if (tv_dac->tv_std == TV_STD_NTSC ||
361 tv_dac->tv_std == TV_STD_NTSC_J ||
362 tv_dac->tv_std == TV_STD_PAL_M)
363 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
364 else
365 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
366 }
367 }
368
369 if (ASIC_IS_DCE3(rdev) &&
370 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
371 radeon_encoder_is_dp_bridge(encoder))) {
372 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
373 radeon_dp_set_link_config(connector, mode);
374 }
375
376 return true;
377 }
378
379 static void
380 atombios_dac_setup(struct drm_encoder *encoder, int action)
381 {
382 struct drm_device *dev = encoder->dev;
383 struct radeon_device *rdev = dev->dev_private;
384 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
385 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
386 int index = 0;
387 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
388
389 memset(&args, 0, sizeof(args));
390
391 switch (radeon_encoder->encoder_id) {
392 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
393 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
394 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
395 break;
396 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
397 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
398 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
399 break;
400 }
401
402 args.ucAction = action;
403
404 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
405 args.ucDacStandard = ATOM_DAC1_PS2;
406 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
407 args.ucDacStandard = ATOM_DAC1_CV;
408 else {
409 switch (dac_info->tv_std) {
410 case TV_STD_PAL:
411 case TV_STD_PAL_M:
412 case TV_STD_SCART_PAL:
413 case TV_STD_SECAM:
414 case TV_STD_PAL_CN:
415 args.ucDacStandard = ATOM_DAC1_PAL;
416 break;
417 case TV_STD_NTSC:
418 case TV_STD_NTSC_J:
419 case TV_STD_PAL_60:
420 default:
421 args.ucDacStandard = ATOM_DAC1_NTSC;
422 break;
423 }
424 }
425 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
426
427 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
428
429 }
430
431 static void
432 atombios_tv_setup(struct drm_encoder *encoder, int action)
433 {
434 struct drm_device *dev = encoder->dev;
435 struct radeon_device *rdev = dev->dev_private;
436 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
437 TV_ENCODER_CONTROL_PS_ALLOCATION args;
438 int index = 0;
439 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
440
441 memset(&args, 0, sizeof(args));
442
443 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
444
445 args.sTVEncoder.ucAction = action;
446
447 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
448 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
449 else {
450 switch (dac_info->tv_std) {
451 case TV_STD_NTSC:
452 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
453 break;
454 case TV_STD_PAL:
455 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
456 break;
457 case TV_STD_PAL_M:
458 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
459 break;
460 case TV_STD_PAL_60:
461 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
462 break;
463 case TV_STD_NTSC_J:
464 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
465 break;
466 case TV_STD_SCART_PAL:
467 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
468 break;
469 case TV_STD_SECAM:
470 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
471 break;
472 case TV_STD_PAL_CN:
473 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
474 break;
475 default:
476 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
477 break;
478 }
479 }
480
481 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
482
483 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
484
485 }
486
487 union dvo_encoder_control {
488 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
489 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
490 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
491 };
492
493 void
494 atombios_dvo_setup(struct drm_encoder *encoder, int action)
495 {
496 struct drm_device *dev = encoder->dev;
497 struct radeon_device *rdev = dev->dev_private;
498 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
499 union dvo_encoder_control args;
500 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
501
502 memset(&args, 0, sizeof(args));
503
504 if (ASIC_IS_DCE3(rdev)) {
505 /* DCE3+ */
506 args.dvo_v3.ucAction = action;
507 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
508 args.dvo_v3.ucDVOConfig = 0; /* XXX */
509 } else if (ASIC_IS_DCE2(rdev)) {
510 /* DCE2 (pre-DCE3 R6xx, RS600/690/740 */
511 args.dvo.sDVOEncoder.ucAction = action;
512 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
513 /* DFP1, CRT1, TV1 depending on the type of port */
514 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
515
516 if (radeon_encoder->pixel_clock > 165000)
517 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
518 } else {
519 /* R4xx, R5xx */
520 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
521
522 if (radeon_encoder->pixel_clock > 165000)
523 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
524
525 /*if (pScrn->rgbBits == 8)*/
526 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
527 }
528
529 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
530 }
531
532 union lvds_encoder_control {
533 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
534 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
535 };
536
537 void
538 atombios_digital_setup(struct drm_encoder *encoder, int action)
539 {
540 struct drm_device *dev = encoder->dev;
541 struct radeon_device *rdev = dev->dev_private;
542 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
543 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
544 union lvds_encoder_control args;
545 int index = 0;
546 int hdmi_detected = 0;
547 uint8_t frev, crev;
548
549 if (!dig)
550 return;
551
552 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
553 hdmi_detected = 1;
554
555 memset(&args, 0, sizeof(args));
556
557 switch (radeon_encoder->encoder_id) {
558 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
559 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
560 break;
561 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
562 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
563 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
564 break;
565 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
566 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
567 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
568 else
569 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
570 break;
571 }
572
573 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
574 return;
575
576 switch (frev) {
577 case 1:
578 case 2:
579 switch (crev) {
580 case 1:
581 args.v1.ucMisc = 0;
582 args.v1.ucAction = action;
583 if (hdmi_detected)
584 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
585 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
586 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
587 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
588 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
589 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
590 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
591 } else {
592 if (dig->linkb)
593 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
594 if (radeon_encoder->pixel_clock > 165000)
595 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
596 /*if (pScrn->rgbBits == 8) */
597 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
598 }
599 break;
600 case 2:
601 case 3:
602 args.v2.ucMisc = 0;
603 args.v2.ucAction = action;
604 if (crev == 3) {
605 if (dig->coherent_mode)
606 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
607 }
608 if (hdmi_detected)
609 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
610 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
611 args.v2.ucTruncate = 0;
612 args.v2.ucSpatial = 0;
613 args.v2.ucTemporal = 0;
614 args.v2.ucFRC = 0;
615 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
616 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
617 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
618 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
619 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
620 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
621 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
622 }
623 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
624 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
625 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
626 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
627 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
628 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
629 }
630 } else {
631 if (dig->linkb)
632 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
633 if (radeon_encoder->pixel_clock > 165000)
634 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
635 }
636 break;
637 default:
638 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
639 break;
640 }
641 break;
642 default:
643 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
644 break;
645 }
646
647 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
648 }
649
650 int
651 atombios_get_encoder_mode(struct drm_encoder *encoder)
652 {
653 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
654 struct drm_device *dev = encoder->dev;
655 struct radeon_device *rdev = dev->dev_private;
656 struct drm_connector *connector;
657 struct radeon_connector *radeon_connector;
658 struct radeon_connector_atom_dig *dig_connector;
659
660 /* dp bridges are always DP */
661 if (radeon_encoder_is_dp_bridge(encoder))
662 return ATOM_ENCODER_MODE_DP;
663
664 /* DVO is always DVO */
665 if (radeon_encoder->encoder_id == ATOM_ENCODER_MODE_DVO)
666 return ATOM_ENCODER_MODE_DVO;
667
668 connector = radeon_get_connector_for_encoder(encoder);
669 /* if we don't have an active device yet, just use one of
670 * the connectors tied to the encoder.
671 */
672 if (!connector)
673 connector = radeon_get_connector_for_encoder_init(encoder);
674 radeon_connector = to_radeon_connector(connector);
675
676 switch (connector->connector_type) {
677 case DRM_MODE_CONNECTOR_DVII:
678 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
679 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
680 /* fix me */
681 if (ASIC_IS_DCE4(rdev))
682 return ATOM_ENCODER_MODE_DVI;
683 else
684 return ATOM_ENCODER_MODE_HDMI;
685 } else if (radeon_connector->use_digital)
686 return ATOM_ENCODER_MODE_DVI;
687 else
688 return ATOM_ENCODER_MODE_CRT;
689 break;
690 case DRM_MODE_CONNECTOR_DVID:
691 case DRM_MODE_CONNECTOR_HDMIA:
692 default:
693 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
694 /* fix me */
695 if (ASIC_IS_DCE4(rdev))
696 return ATOM_ENCODER_MODE_DVI;
697 else
698 return ATOM_ENCODER_MODE_HDMI;
699 } else
700 return ATOM_ENCODER_MODE_DVI;
701 break;
702 case DRM_MODE_CONNECTOR_LVDS:
703 return ATOM_ENCODER_MODE_LVDS;
704 break;
705 case DRM_MODE_CONNECTOR_DisplayPort:
706 dig_connector = radeon_connector->con_priv;
707 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
708 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
709 return ATOM_ENCODER_MODE_DP;
710 else if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
711 /* fix me */
712 if (ASIC_IS_DCE4(rdev))
713 return ATOM_ENCODER_MODE_DVI;
714 else
715 return ATOM_ENCODER_MODE_HDMI;
716 } else
717 return ATOM_ENCODER_MODE_DVI;
718 break;
719 case DRM_MODE_CONNECTOR_eDP:
720 return ATOM_ENCODER_MODE_DP;
721 case DRM_MODE_CONNECTOR_DVIA:
722 case DRM_MODE_CONNECTOR_VGA:
723 return ATOM_ENCODER_MODE_CRT;
724 break;
725 case DRM_MODE_CONNECTOR_Composite:
726 case DRM_MODE_CONNECTOR_SVIDEO:
727 case DRM_MODE_CONNECTOR_9PinDIN:
728 /* fix me */
729 return ATOM_ENCODER_MODE_TV;
730 /*return ATOM_ENCODER_MODE_CV;*/
731 break;
732 }
733 }
734
735 /*
736 * DIG Encoder/Transmitter Setup
737 *
738 * DCE 3.0/3.1
739 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
740 * Supports up to 3 digital outputs
741 * - 2 DIG encoder blocks.
742 * DIG1 can drive UNIPHY link A or link B
743 * DIG2 can drive UNIPHY link B or LVTMA
744 *
745 * DCE 3.2
746 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
747 * Supports up to 5 digital outputs
748 * - 2 DIG encoder blocks.
749 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
750 *
751 * DCE 4.0/5.0
752 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
753 * Supports up to 6 digital outputs
754 * - 6 DIG encoder blocks.
755 * - DIG to PHY mapping is hardcoded
756 * DIG1 drives UNIPHY0 link A, A+B
757 * DIG2 drives UNIPHY0 link B
758 * DIG3 drives UNIPHY1 link A, A+B
759 * DIG4 drives UNIPHY1 link B
760 * DIG5 drives UNIPHY2 link A, A+B
761 * DIG6 drives UNIPHY2 link B
762 *
763 * DCE 4.1
764 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
765 * Supports up to 6 digital outputs
766 * - 2 DIG encoder blocks.
767 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
768 *
769 * Routing
770 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
771 * Examples:
772 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
773 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
774 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
775 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
776 */
777
778 union dig_encoder_control {
779 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
780 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
781 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
782 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
783 };
784
785 void
786 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
787 {
788 struct drm_device *dev = encoder->dev;
789 struct radeon_device *rdev = dev->dev_private;
790 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
791 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
792 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
793 union dig_encoder_control args;
794 int index = 0;
795 uint8_t frev, crev;
796 int dp_clock = 0;
797 int dp_lane_count = 0;
798 int hpd_id = RADEON_HPD_NONE;
799 int bpc = 8;
800
801 if (connector) {
802 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
803 struct radeon_connector_atom_dig *dig_connector =
804 radeon_connector->con_priv;
805
806 dp_clock = dig_connector->dp_clock;
807 dp_lane_count = dig_connector->dp_lane_count;
808 hpd_id = radeon_connector->hpd.hpd;
809 bpc = connector->display_info.bpc;
810 }
811
812 /* no dig encoder assigned */
813 if (dig->dig_encoder == -1)
814 return;
815
816 memset(&args, 0, sizeof(args));
817
818 if (ASIC_IS_DCE4(rdev))
819 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
820 else {
821 if (dig->dig_encoder)
822 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
823 else
824 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
825 }
826
827 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
828 return;
829
830 args.v1.ucAction = action;
831 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
832 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
833 args.v3.ucPanelMode = panel_mode;
834 else
835 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
836
837 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) ||
838 (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST))
839 args.v1.ucLaneNum = dp_lane_count;
840 else if (radeon_encoder->pixel_clock > 165000)
841 args.v1.ucLaneNum = 8;
842 else
843 args.v1.ucLaneNum = 4;
844
845 if (ASIC_IS_DCE5(rdev)) {
846 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) ||
847 (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST)) {
848 if (dp_clock == 270000)
849 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
850 else if (dp_clock == 540000)
851 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
852 }
853 args.v4.acConfig.ucDigSel = dig->dig_encoder;
854 switch (bpc) {
855 case 0:
856 args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE;
857 break;
858 case 6:
859 args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR;
860 break;
861 case 8:
862 default:
863 args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
864 break;
865 case 10:
866 args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR;
867 break;
868 case 12:
869 args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR;
870 break;
871 case 16:
872 args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR;
873 break;
874 }
875 if (hpd_id == RADEON_HPD_NONE)
876 args.v4.ucHPD_ID = 0;
877 else
878 args.v4.ucHPD_ID = hpd_id + 1;
879 } else if (ASIC_IS_DCE4(rdev)) {
880 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000))
881 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
882 args.v3.acConfig.ucDigSel = dig->dig_encoder;
883 switch (bpc) {
884 case 0:
885 args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE;
886 break;
887 case 6:
888 args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR;
889 break;
890 case 8:
891 default:
892 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
893 break;
894 case 10:
895 args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR;
896 break;
897 case 12:
898 args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR;
899 break;
900 case 16:
901 args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR;
902 break;
903 }
904 } else {
905 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000))
906 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
907 switch (radeon_encoder->encoder_id) {
908 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
909 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
910 break;
911 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
912 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
913 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
914 break;
915 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
916 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
917 break;
918 }
919 if (dig->linkb)
920 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
921 else
922 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
923 }
924
925 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
926
927 }
928
929 union dig_transmitter_control {
930 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
931 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
932 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
933 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
934 };
935
936 void
937 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
938 {
939 struct drm_device *dev = encoder->dev;
940 struct radeon_device *rdev = dev->dev_private;
941 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
942 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
943 struct drm_connector *connector;
944 union dig_transmitter_control args;
945 int index = 0;
946 uint8_t frev, crev;
947 bool is_dp = false;
948 int pll_id = 0;
949 int dp_clock = 0;
950 int dp_lane_count = 0;
951 int connector_object_id = 0;
952 int igp_lane_info = 0;
953 int dig_encoder = dig->dig_encoder;
954
955 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
956 connector = radeon_get_connector_for_encoder_init(encoder);
957 /* just needed to avoid bailing in the encoder check. the encoder
958 * isn't used for init
959 */
960 dig_encoder = 0;
961 } else
962 connector = radeon_get_connector_for_encoder(encoder);
963
964 if (connector) {
965 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
966 struct radeon_connector_atom_dig *dig_connector =
967 radeon_connector->con_priv;
968
969 dp_clock = dig_connector->dp_clock;
970 dp_lane_count = dig_connector->dp_lane_count;
971 connector_object_id =
972 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
973 igp_lane_info = dig_connector->igp_lane_info;
974 }
975
976 /* no dig encoder assigned */
977 if (dig_encoder == -1)
978 return;
979
980 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
981 is_dp = true;
982
983 memset(&args, 0, sizeof(args));
984
985 switch (radeon_encoder->encoder_id) {
986 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
987 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
988 break;
989 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
990 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
991 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
992 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
993 break;
994 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
995 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
996 break;
997 }
998
999 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1000 return;
1001
1002 args.v1.ucAction = action;
1003 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1004 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1005 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1006 args.v1.asMode.ucLaneSel = lane_num;
1007 args.v1.asMode.ucLaneSet = lane_set;
1008 } else {
1009 if (is_dp)
1010 args.v1.usPixelClock =
1011 cpu_to_le16(dp_clock / 10);
1012 else if (radeon_encoder->pixel_clock > 165000)
1013 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1014 else
1015 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1016 }
1017 if (ASIC_IS_DCE4(rdev)) {
1018 if (is_dp)
1019 args.v3.ucLaneNum = dp_lane_count;
1020 else if (radeon_encoder->pixel_clock > 165000)
1021 args.v3.ucLaneNum = 8;
1022 else
1023 args.v3.ucLaneNum = 4;
1024
1025 if (dig->linkb)
1026 args.v3.acConfig.ucLinkSel = 1;
1027 if (dig_encoder & 1)
1028 args.v3.acConfig.ucEncoderSel = 1;
1029
1030 /* Select the PLL for the PHY
1031 * DP PHY should be clocked from external src if there is
1032 * one.
1033 */
1034 if (encoder->crtc) {
1035 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1036 pll_id = radeon_crtc->pll_id;
1037 }
1038
1039 if (ASIC_IS_DCE5(rdev)) {
1040 /* On DCE5 DCPLL usually generates the DP ref clock */
1041 if (is_dp) {
1042 if (rdev->clock.dp_extclk)
1043 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1044 else
1045 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1046 } else
1047 args.v4.acConfig.ucRefClkSource = pll_id;
1048 } else {
1049 /* On DCE4, if there is an external clock, it generates the DP ref clock */
1050 if (is_dp && rdev->clock.dp_extclk)
1051 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1052 else
1053 args.v3.acConfig.ucRefClkSource = pll_id;
1054 }
1055
1056 switch (radeon_encoder->encoder_id) {
1057 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1058 args.v3.acConfig.ucTransmitterSel = 0;
1059 break;
1060 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1061 args.v3.acConfig.ucTransmitterSel = 1;
1062 break;
1063 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1064 args.v3.acConfig.ucTransmitterSel = 2;
1065 break;
1066 }
1067
1068 if (is_dp)
1069 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1070 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1071 if (dig->coherent_mode)
1072 args.v3.acConfig.fCoherentMode = 1;
1073 if (radeon_encoder->pixel_clock > 165000)
1074 args.v3.acConfig.fDualLinkConnector = 1;
1075 }
1076 } else if (ASIC_IS_DCE32(rdev)) {
1077 args.v2.acConfig.ucEncoderSel = dig_encoder;
1078 if (dig->linkb)
1079 args.v2.acConfig.ucLinkSel = 1;
1080
1081 switch (radeon_encoder->encoder_id) {
1082 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1083 args.v2.acConfig.ucTransmitterSel = 0;
1084 break;
1085 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1086 args.v2.acConfig.ucTransmitterSel = 1;
1087 break;
1088 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1089 args.v2.acConfig.ucTransmitterSel = 2;
1090 break;
1091 }
1092
1093 if (is_dp) {
1094 args.v2.acConfig.fCoherentMode = 1;
1095 args.v2.acConfig.fDPConnector = 1;
1096 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1097 if (dig->coherent_mode)
1098 args.v2.acConfig.fCoherentMode = 1;
1099 if (radeon_encoder->pixel_clock > 165000)
1100 args.v2.acConfig.fDualLinkConnector = 1;
1101 }
1102 } else {
1103 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1104
1105 if (dig_encoder)
1106 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1107 else
1108 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1109
1110 if ((rdev->flags & RADEON_IS_IGP) &&
1111 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1112 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
1113 if (igp_lane_info & 0x1)
1114 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1115 else if (igp_lane_info & 0x2)
1116 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1117 else if (igp_lane_info & 0x4)
1118 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1119 else if (igp_lane_info & 0x8)
1120 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1121 } else {
1122 if (igp_lane_info & 0x3)
1123 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1124 else if (igp_lane_info & 0xc)
1125 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1126 }
1127 }
1128
1129 if (dig->linkb)
1130 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1131 else
1132 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1133
1134 if (is_dp)
1135 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1136 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1137 if (dig->coherent_mode)
1138 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1139 if (radeon_encoder->pixel_clock > 165000)
1140 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1141 }
1142 }
1143
1144 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1145 }
1146
1147 bool
1148 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1149 {
1150 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1151 struct drm_device *dev = radeon_connector->base.dev;
1152 struct radeon_device *rdev = dev->dev_private;
1153 union dig_transmitter_control args;
1154 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1155 uint8_t frev, crev;
1156
1157 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1158 goto done;
1159
1160 if (!ASIC_IS_DCE4(rdev))
1161 goto done;
1162
1163 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1164 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1165 goto done;
1166
1167 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1168 goto done;
1169
1170 memset(&args, 0, sizeof(args));
1171
1172 args.v1.ucAction = action;
1173
1174 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1175
1176 /* wait for the panel to power up */
1177 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1178 int i;
1179
1180 for (i = 0; i < 300; i++) {
1181 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1182 return true;
1183 mdelay(1);
1184 }
1185 return false;
1186 }
1187 done:
1188 return true;
1189 }
1190
1191 union external_encoder_control {
1192 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1193 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1194 };
1195
1196 static void
1197 atombios_external_encoder_setup(struct drm_encoder *encoder,
1198 struct drm_encoder *ext_encoder,
1199 int action)
1200 {
1201 struct drm_device *dev = encoder->dev;
1202 struct radeon_device *rdev = dev->dev_private;
1203 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1204 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1205 union external_encoder_control args;
1206 struct drm_connector *connector;
1207 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1208 u8 frev, crev;
1209 int dp_clock = 0;
1210 int dp_lane_count = 0;
1211 int connector_object_id = 0;
1212 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1213 int bpc = 8;
1214
1215 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1216 connector = radeon_get_connector_for_encoder_init(encoder);
1217 else
1218 connector = radeon_get_connector_for_encoder(encoder);
1219
1220 if (connector) {
1221 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1222 struct radeon_connector_atom_dig *dig_connector =
1223 radeon_connector->con_priv;
1224
1225 dp_clock = dig_connector->dp_clock;
1226 dp_lane_count = dig_connector->dp_lane_count;
1227 connector_object_id =
1228 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1229 bpc = connector->display_info.bpc;
1230 }
1231
1232 memset(&args, 0, sizeof(args));
1233
1234 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1235 return;
1236
1237 switch (frev) {
1238 case 1:
1239 /* no params on frev 1 */
1240 break;
1241 case 2:
1242 switch (crev) {
1243 case 1:
1244 case 2:
1245 args.v1.sDigEncoder.ucAction = action;
1246 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1247 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1248
1249 if (args.v1.sDigEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
1250 if (dp_clock == 270000)
1251 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1252 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1253 } else if (radeon_encoder->pixel_clock > 165000)
1254 args.v1.sDigEncoder.ucLaneNum = 8;
1255 else
1256 args.v1.sDigEncoder.ucLaneNum = 4;
1257 break;
1258 case 3:
1259 args.v3.sExtEncoder.ucAction = action;
1260 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1261 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1262 else
1263 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1264 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1265
1266 if (args.v3.sExtEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
1267 if (dp_clock == 270000)
1268 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1269 else if (dp_clock == 540000)
1270 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1271 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1272 } else if (radeon_encoder->pixel_clock > 165000)
1273 args.v3.sExtEncoder.ucLaneNum = 8;
1274 else
1275 args.v3.sExtEncoder.ucLaneNum = 4;
1276 switch (ext_enum) {
1277 case GRAPH_OBJECT_ENUM_ID1:
1278 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1279 break;
1280 case GRAPH_OBJECT_ENUM_ID2:
1281 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1282 break;
1283 case GRAPH_OBJECT_ENUM_ID3:
1284 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1285 break;
1286 }
1287 switch (bpc) {
1288 case 0:
1289 args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE;
1290 break;
1291 case 6:
1292 args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR;
1293 break;
1294 case 8:
1295 default:
1296 args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;
1297 break;
1298 case 10:
1299 args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR;
1300 break;
1301 case 12:
1302 args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR;
1303 break;
1304 case 16:
1305 args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR;
1306 break;
1307 }
1308 break;
1309 default:
1310 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1311 return;
1312 }
1313 break;
1314 default:
1315 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1316 return;
1317 }
1318 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1319 }
1320
1321 static void
1322 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1323 {
1324 struct drm_device *dev = encoder->dev;
1325 struct radeon_device *rdev = dev->dev_private;
1326 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1327 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1328 ENABLE_YUV_PS_ALLOCATION args;
1329 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1330 uint32_t temp, reg;
1331
1332 memset(&args, 0, sizeof(args));
1333
1334 if (rdev->family >= CHIP_R600)
1335 reg = R600_BIOS_3_SCRATCH;
1336 else
1337 reg = RADEON_BIOS_3_SCRATCH;
1338
1339 /* XXX: fix up scratch reg handling */
1340 temp = RREG32(reg);
1341 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1342 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1343 (radeon_crtc->crtc_id << 18)));
1344 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1345 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1346 else
1347 WREG32(reg, 0);
1348
1349 if (enable)
1350 args.ucEnable = ATOM_ENABLE;
1351 args.ucCRTC = radeon_crtc->crtc_id;
1352
1353 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1354
1355 WREG32(reg, temp);
1356 }
1357
1358 static void
1359 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1360 {
1361 struct drm_device *dev = encoder->dev;
1362 struct radeon_device *rdev = dev->dev_private;
1363 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1364 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1365 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1366 int index = 0;
1367 bool is_dig = false;
1368 bool is_dce5_dac = false;
1369 bool is_dce5_dvo = false;
1370
1371 memset(&args, 0, sizeof(args));
1372
1373 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1374 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1375 radeon_encoder->active_device);
1376 switch (radeon_encoder->encoder_id) {
1377 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1378 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1379 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1380 break;
1381 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1382 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1383 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1384 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1385 is_dig = true;
1386 break;
1387 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1388 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1389 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1390 break;
1391 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1392 if (ASIC_IS_DCE5(rdev))
1393 is_dce5_dvo = true;
1394 else if (ASIC_IS_DCE3(rdev))
1395 is_dig = true;
1396 else
1397 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1398 break;
1399 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1400 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1401 break;
1402 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1403 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1404 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1405 else
1406 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1407 break;
1408 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1409 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1410 if (ASIC_IS_DCE5(rdev))
1411 is_dce5_dac = true;
1412 else {
1413 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1414 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1415 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1416 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1417 else
1418 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1419 }
1420 break;
1421 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1422 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1423 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1424 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1425 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1426 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1427 else
1428 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1429 break;
1430 }
1431
1432 if (is_dig) {
1433 switch (mode) {
1434 case DRM_MODE_DPMS_ON:
1435 /* some early dce3.2 boards have a bug in their transmitter control table */
1436 if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730))
1437 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1438 else
1439 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1440 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1441 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1442
1443 if (connector &&
1444 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1445 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1446 struct radeon_connector_atom_dig *radeon_dig_connector =
1447 radeon_connector->con_priv;
1448 atombios_set_edp_panel_power(connector,
1449 ATOM_TRANSMITTER_ACTION_POWER_ON);
1450 radeon_dig_connector->edp_on = true;
1451 }
1452 if (ASIC_IS_DCE4(rdev))
1453 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1454 radeon_dp_link_train(encoder, connector);
1455 if (ASIC_IS_DCE4(rdev))
1456 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1457 }
1458 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1459 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1460 break;
1461 case DRM_MODE_DPMS_STANDBY:
1462 case DRM_MODE_DPMS_SUSPEND:
1463 case DRM_MODE_DPMS_OFF:
1464 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1465 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1466 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1467
1468 if (ASIC_IS_DCE4(rdev))
1469 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1470 if (connector &&
1471 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1472 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1473 struct radeon_connector_atom_dig *radeon_dig_connector =
1474 radeon_connector->con_priv;
1475 atombios_set_edp_panel_power(connector,
1476 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1477 radeon_dig_connector->edp_on = false;
1478 }
1479 }
1480 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1481 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1482 break;
1483 }
1484 } else if (is_dce5_dac) {
1485 switch (mode) {
1486 case DRM_MODE_DPMS_ON:
1487 atombios_dac_setup(encoder, ATOM_ENABLE);
1488 break;
1489 case DRM_MODE_DPMS_STANDBY:
1490 case DRM_MODE_DPMS_SUSPEND:
1491 case DRM_MODE_DPMS_OFF:
1492 atombios_dac_setup(encoder, ATOM_DISABLE);
1493 break;
1494 }
1495 } else if (is_dce5_dvo) {
1496 switch (mode) {
1497 case DRM_MODE_DPMS_ON:
1498 atombios_dvo_setup(encoder, ATOM_ENABLE);
1499 break;
1500 case DRM_MODE_DPMS_STANDBY:
1501 case DRM_MODE_DPMS_SUSPEND:
1502 case DRM_MODE_DPMS_OFF:
1503 atombios_dvo_setup(encoder, ATOM_DISABLE);
1504 break;
1505 }
1506 } else {
1507 switch (mode) {
1508 case DRM_MODE_DPMS_ON:
1509 args.ucAction = ATOM_ENABLE;
1510 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1511 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1512 args.ucAction = ATOM_LCD_BLON;
1513 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1514 }
1515 break;
1516 case DRM_MODE_DPMS_STANDBY:
1517 case DRM_MODE_DPMS_SUSPEND:
1518 case DRM_MODE_DPMS_OFF:
1519 args.ucAction = ATOM_DISABLE;
1520 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1521 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1522 args.ucAction = ATOM_LCD_BLOFF;
1523 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1524 }
1525 break;
1526 }
1527 }
1528
1529 if (ext_encoder) {
1530 switch (mode) {
1531 case DRM_MODE_DPMS_ON:
1532 default:
1533 if (ASIC_IS_DCE41(rdev)) {
1534 atombios_external_encoder_setup(encoder, ext_encoder,
1535 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1536 atombios_external_encoder_setup(encoder, ext_encoder,
1537 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1538 } else
1539 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1540 break;
1541 case DRM_MODE_DPMS_STANDBY:
1542 case DRM_MODE_DPMS_SUSPEND:
1543 case DRM_MODE_DPMS_OFF:
1544 if (ASIC_IS_DCE41(rdev)) {
1545 atombios_external_encoder_setup(encoder, ext_encoder,
1546 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1547 atombios_external_encoder_setup(encoder, ext_encoder,
1548 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1549 } else
1550 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1551 break;
1552 }
1553 }
1554
1555 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1556
1557 }
1558
1559 union crtc_source_param {
1560 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1561 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1562 };
1563
1564 static void
1565 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1566 {
1567 struct drm_device *dev = encoder->dev;
1568 struct radeon_device *rdev = dev->dev_private;
1569 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1570 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1571 union crtc_source_param args;
1572 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1573 uint8_t frev, crev;
1574 struct radeon_encoder_atom_dig *dig;
1575
1576 memset(&args, 0, sizeof(args));
1577
1578 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1579 return;
1580
1581 switch (frev) {
1582 case 1:
1583 switch (crev) {
1584 case 1:
1585 default:
1586 if (ASIC_IS_AVIVO(rdev))
1587 args.v1.ucCRTC = radeon_crtc->crtc_id;
1588 else {
1589 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1590 args.v1.ucCRTC = radeon_crtc->crtc_id;
1591 } else {
1592 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1593 }
1594 }
1595 switch (radeon_encoder->encoder_id) {
1596 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1597 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1598 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1599 break;
1600 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1601 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1602 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1603 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1604 else
1605 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1606 break;
1607 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1608 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1609 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1610 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1611 break;
1612 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1613 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1614 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1615 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1616 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1617 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1618 else
1619 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1620 break;
1621 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1622 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1623 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1624 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1625 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1626 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1627 else
1628 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1629 break;
1630 }
1631 break;
1632 case 2:
1633 args.v2.ucCRTC = radeon_crtc->crtc_id;
1634 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1635 switch (radeon_encoder->encoder_id) {
1636 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1637 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1638 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1639 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1640 dig = radeon_encoder->enc_priv;
1641 switch (dig->dig_encoder) {
1642 case 0:
1643 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1644 break;
1645 case 1:
1646 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1647 break;
1648 case 2:
1649 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1650 break;
1651 case 3:
1652 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1653 break;
1654 case 4:
1655 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1656 break;
1657 case 5:
1658 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1659 break;
1660 }
1661 break;
1662 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1663 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1664 break;
1665 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1666 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1667 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1668 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1669 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1670 else
1671 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1672 break;
1673 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1674 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1675 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1676 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1677 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1678 else
1679 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1680 break;
1681 }
1682 break;
1683 }
1684 break;
1685 default:
1686 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1687 return;
1688 }
1689
1690 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1691
1692 /* update scratch regs with new routing */
1693 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1694 }
1695
1696 static void
1697 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1698 struct drm_display_mode *mode)
1699 {
1700 struct drm_device *dev = encoder->dev;
1701 struct radeon_device *rdev = dev->dev_private;
1702 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1703 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1704
1705 /* Funky macbooks */
1706 if ((dev->pdev->device == 0x71C5) &&
1707 (dev->pdev->subsystem_vendor == 0x106b) &&
1708 (dev->pdev->subsystem_device == 0x0080)) {
1709 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1710 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1711
1712 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1713 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1714
1715 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1716 }
1717 }
1718
1719 /* set scaler clears this on some chips */
1720 if (ASIC_IS_AVIVO(rdev) &&
1721 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1722 if (ASIC_IS_DCE4(rdev)) {
1723 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1724 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1725 EVERGREEN_INTERLEAVE_EN);
1726 else
1727 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1728 } else {
1729 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1730 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1731 AVIVO_D1MODE_INTERLEAVE_EN);
1732 else
1733 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1734 }
1735 }
1736 }
1737
1738 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1739 {
1740 struct drm_device *dev = encoder->dev;
1741 struct radeon_device *rdev = dev->dev_private;
1742 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1743 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1744 struct drm_encoder *test_encoder;
1745 struct radeon_encoder_atom_dig *dig;
1746 uint32_t dig_enc_in_use = 0;
1747
1748 /* DCE4/5 */
1749 if (ASIC_IS_DCE4(rdev)) {
1750 dig = radeon_encoder->enc_priv;
1751 if (ASIC_IS_DCE41(rdev))
1752 return radeon_crtc->crtc_id;
1753 else {
1754 switch (radeon_encoder->encoder_id) {
1755 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1756 if (dig->linkb)
1757 return 1;
1758 else
1759 return 0;
1760 break;
1761 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1762 if (dig->linkb)
1763 return 3;
1764 else
1765 return 2;
1766 break;
1767 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1768 if (dig->linkb)
1769 return 5;
1770 else
1771 return 4;
1772 break;
1773 }
1774 }
1775 }
1776
1777 /* on DCE32 and encoder can driver any block so just crtc id */
1778 if (ASIC_IS_DCE32(rdev)) {
1779 return radeon_crtc->crtc_id;
1780 }
1781
1782 /* on DCE3 - LVTMA can only be driven by DIGB */
1783 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1784 struct radeon_encoder *radeon_test_encoder;
1785
1786 if (encoder == test_encoder)
1787 continue;
1788
1789 if (!radeon_encoder_is_digital(test_encoder))
1790 continue;
1791
1792 radeon_test_encoder = to_radeon_encoder(test_encoder);
1793 dig = radeon_test_encoder->enc_priv;
1794
1795 if (dig->dig_encoder >= 0)
1796 dig_enc_in_use |= (1 << dig->dig_encoder);
1797 }
1798
1799 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1800 if (dig_enc_in_use & 0x2)
1801 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1802 return 1;
1803 }
1804 if (!(dig_enc_in_use & 1))
1805 return 0;
1806 return 1;
1807 }
1808
1809 /* This only needs to be called once at startup */
1810 void
1811 radeon_atom_encoder_init(struct radeon_device *rdev)
1812 {
1813 struct drm_device *dev = rdev->ddev;
1814 struct drm_encoder *encoder;
1815
1816 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1817 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1818 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1819
1820 switch (radeon_encoder->encoder_id) {
1821 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1822 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1823 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1824 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1825 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1826 break;
1827 default:
1828 break;
1829 }
1830
1831 if (ext_encoder && ASIC_IS_DCE41(rdev))
1832 atombios_external_encoder_setup(encoder, ext_encoder,
1833 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
1834 }
1835 }
1836
1837 static void
1838 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1839 struct drm_display_mode *mode,
1840 struct drm_display_mode *adjusted_mode)
1841 {
1842 struct drm_device *dev = encoder->dev;
1843 struct radeon_device *rdev = dev->dev_private;
1844 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1845 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1846
1847 radeon_encoder->pixel_clock = adjusted_mode->clock;
1848
1849 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1850 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1851 atombios_yuv_setup(encoder, true);
1852 else
1853 atombios_yuv_setup(encoder, false);
1854 }
1855
1856 switch (radeon_encoder->encoder_id) {
1857 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1858 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1859 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1860 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1861 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1862 break;
1863 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1864 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1865 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1866 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1867 if (ASIC_IS_DCE4(rdev)) {
1868 /* disable the transmitter */
1869 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1870 /* setup and enable the encoder */
1871 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1872
1873 /* enable the transmitter */
1874 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1875 } else {
1876 /* disable the encoder and transmitter */
1877 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1878 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1879
1880 /* setup and enable the encoder and transmitter */
1881 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1882 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1883 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1884 }
1885 break;
1886 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1887 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1888 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1889 atombios_dvo_setup(encoder, ATOM_ENABLE);
1890 break;
1891 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1892 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1893 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1894 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1895 atombios_dac_setup(encoder, ATOM_ENABLE);
1896 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1897 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1898 atombios_tv_setup(encoder, ATOM_ENABLE);
1899 else
1900 atombios_tv_setup(encoder, ATOM_DISABLE);
1901 }
1902 break;
1903 }
1904
1905 if (ext_encoder) {
1906 if (ASIC_IS_DCE41(rdev))
1907 atombios_external_encoder_setup(encoder, ext_encoder,
1908 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1909 else
1910 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1911 }
1912
1913 atombios_apply_encoder_quirks(encoder, adjusted_mode);
1914
1915 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1916 r600_hdmi_enable(encoder);
1917 r600_hdmi_setmode(encoder, adjusted_mode);
1918 }
1919 }
1920
1921 static bool
1922 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1923 {
1924 struct drm_device *dev = encoder->dev;
1925 struct radeon_device *rdev = dev->dev_private;
1926 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1927 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1928
1929 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1930 ATOM_DEVICE_CV_SUPPORT |
1931 ATOM_DEVICE_CRT_SUPPORT)) {
1932 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1933 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1934 uint8_t frev, crev;
1935
1936 memset(&args, 0, sizeof(args));
1937
1938 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1939 return false;
1940
1941 args.sDacload.ucMisc = 0;
1942
1943 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1944 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1945 args.sDacload.ucDacType = ATOM_DAC_A;
1946 else
1947 args.sDacload.ucDacType = ATOM_DAC_B;
1948
1949 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1950 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1951 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1952 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1953 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1954 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1955 if (crev >= 3)
1956 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1957 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1958 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1959 if (crev >= 3)
1960 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1961 }
1962
1963 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1964
1965 return true;
1966 } else
1967 return false;
1968 }
1969
1970 static enum drm_connector_status
1971 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1972 {
1973 struct drm_device *dev = encoder->dev;
1974 struct radeon_device *rdev = dev->dev_private;
1975 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1976 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1977 uint32_t bios_0_scratch;
1978
1979 if (!atombios_dac_load_detect(encoder, connector)) {
1980 DRM_DEBUG_KMS("detect returned false \n");
1981 return connector_status_unknown;
1982 }
1983
1984 if (rdev->family >= CHIP_R600)
1985 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1986 else
1987 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1988
1989 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1990 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1991 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1992 return connector_status_connected;
1993 }
1994 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1995 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1996 return connector_status_connected;
1997 }
1998 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1999 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2000 return connector_status_connected;
2001 }
2002 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2003 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2004 return connector_status_connected; /* CTV */
2005 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2006 return connector_status_connected; /* STV */
2007 }
2008 return connector_status_disconnected;
2009 }
2010
2011 static enum drm_connector_status
2012 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2013 {
2014 struct drm_device *dev = encoder->dev;
2015 struct radeon_device *rdev = dev->dev_private;
2016 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2017 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2018 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
2019 u32 bios_0_scratch;
2020
2021 if (!ASIC_IS_DCE4(rdev))
2022 return connector_status_unknown;
2023
2024 if (!ext_encoder)
2025 return connector_status_unknown;
2026
2027 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2028 return connector_status_unknown;
2029
2030 /* load detect on the dp bridge */
2031 atombios_external_encoder_setup(encoder, ext_encoder,
2032 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2033
2034 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2035
2036 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2037 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2038 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2039 return connector_status_connected;
2040 }
2041 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2042 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2043 return connector_status_connected;
2044 }
2045 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2046 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2047 return connector_status_connected;
2048 }
2049 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2050 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2051 return connector_status_connected; /* CTV */
2052 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2053 return connector_status_connected; /* STV */
2054 }
2055 return connector_status_disconnected;
2056 }
2057
2058 void
2059 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2060 {
2061 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
2062
2063 if (ext_encoder)
2064 /* ddc_setup on the dp bridge */
2065 atombios_external_encoder_setup(encoder, ext_encoder,
2066 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2067
2068 }
2069
2070 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2071 {
2072 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2073 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2074
2075 if ((radeon_encoder->active_device &
2076 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2077 radeon_encoder_is_dp_bridge(encoder)) {
2078 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2079 if (dig)
2080 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
2081 }
2082
2083 radeon_atom_output_lock(encoder, true);
2084 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2085
2086 if (connector) {
2087 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2088
2089 /* select the clock/data port if it uses a router */
2090 if (radeon_connector->router.cd_valid)
2091 radeon_router_select_cd_port(radeon_connector);
2092
2093 /* turn eDP panel on for mode set */
2094 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2095 atombios_set_edp_panel_power(connector,
2096 ATOM_TRANSMITTER_ACTION_POWER_ON);
2097 }
2098
2099 /* this is needed for the pll/ss setup to work correctly in some cases */
2100 atombios_set_encoder_crtc_source(encoder);
2101 }
2102
2103 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2104 {
2105 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2106 radeon_atom_output_lock(encoder, false);
2107 }
2108
2109 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2110 {
2111 struct drm_device *dev = encoder->dev;
2112 struct radeon_device *rdev = dev->dev_private;
2113 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2114 struct radeon_encoder_atom_dig *dig;
2115
2116 /* check for pre-DCE3 cards with shared encoders;
2117 * can't really use the links individually, so don't disable
2118 * the encoder if it's in use by another connector
2119 */
2120 if (!ASIC_IS_DCE3(rdev)) {
2121 struct drm_encoder *other_encoder;
2122 struct radeon_encoder *other_radeon_encoder;
2123
2124 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2125 other_radeon_encoder = to_radeon_encoder(other_encoder);
2126 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2127 drm_helper_encoder_in_use(other_encoder))
2128 goto disable_done;
2129 }
2130 }
2131
2132 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2133
2134 switch (radeon_encoder->encoder_id) {
2135 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2136 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2137 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2138 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2139 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2140 break;
2141 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2142 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2143 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2144 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2145 if (ASIC_IS_DCE4(rdev))
2146 /* disable the transmitter */
2147 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2148 else {
2149 /* disable the encoder and transmitter */
2150 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2151 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
2152 }
2153 break;
2154 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2155 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2156 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2157 atombios_dvo_setup(encoder, ATOM_DISABLE);
2158 break;
2159 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2160 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2161 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2162 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2163 atombios_dac_setup(encoder, ATOM_DISABLE);
2164 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2165 atombios_tv_setup(encoder, ATOM_DISABLE);
2166 break;
2167 }
2168
2169 disable_done:
2170 if (radeon_encoder_is_digital(encoder)) {
2171 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
2172 r600_hdmi_disable(encoder);
2173 dig = radeon_encoder->enc_priv;
2174 dig->dig_encoder = -1;
2175 }
2176 radeon_encoder->active_device = 0;
2177 }
2178
2179 /* these are handled by the primary encoders */
2180 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2181 {
2182
2183 }
2184
2185 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2186 {
2187
2188 }
2189
2190 static void
2191 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2192 struct drm_display_mode *mode,
2193 struct drm_display_mode *adjusted_mode)
2194 {
2195
2196 }
2197
2198 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2199 {
2200
2201 }
2202
2203 static void
2204 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2205 {
2206
2207 }
2208
2209 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2210 struct drm_display_mode *mode,
2211 struct drm_display_mode *adjusted_mode)
2212 {
2213 return true;
2214 }
2215
2216 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2217 .dpms = radeon_atom_ext_dpms,
2218 .mode_fixup = radeon_atom_ext_mode_fixup,
2219 .prepare = radeon_atom_ext_prepare,
2220 .mode_set = radeon_atom_ext_mode_set,
2221 .commit = radeon_atom_ext_commit,
2222 .disable = radeon_atom_ext_disable,
2223 /* no detect for TMDS/LVDS yet */
2224 };
2225
2226 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2227 .dpms = radeon_atom_encoder_dpms,
2228 .mode_fixup = radeon_atom_mode_fixup,
2229 .prepare = radeon_atom_encoder_prepare,
2230 .mode_set = radeon_atom_encoder_mode_set,
2231 .commit = radeon_atom_encoder_commit,
2232 .disable = radeon_atom_encoder_disable,
2233 .detect = radeon_atom_dig_detect,
2234 };
2235
2236 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2237 .dpms = radeon_atom_encoder_dpms,
2238 .mode_fixup = radeon_atom_mode_fixup,
2239 .prepare = radeon_atom_encoder_prepare,
2240 .mode_set = radeon_atom_encoder_mode_set,
2241 .commit = radeon_atom_encoder_commit,
2242 .detect = radeon_atom_dac_detect,
2243 };
2244
2245 void radeon_enc_destroy(struct drm_encoder *encoder)
2246 {
2247 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2248 kfree(radeon_encoder->enc_priv);
2249 drm_encoder_cleanup(encoder);
2250 kfree(radeon_encoder);
2251 }
2252
2253 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2254 .destroy = radeon_enc_destroy,
2255 };
2256
2257 struct radeon_encoder_atom_dac *
2258 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2259 {
2260 struct drm_device *dev = radeon_encoder->base.dev;
2261 struct radeon_device *rdev = dev->dev_private;
2262 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2263
2264 if (!dac)
2265 return NULL;
2266
2267 dac->tv_std = radeon_atombios_get_tv_info(rdev);
2268 return dac;
2269 }
2270
2271 struct radeon_encoder_atom_dig *
2272 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2273 {
2274 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2275 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2276
2277 if (!dig)
2278 return NULL;
2279
2280 /* coherent mode by default */
2281 dig->coherent_mode = true;
2282 dig->dig_encoder = -1;
2283
2284 if (encoder_enum == 2)
2285 dig->linkb = true;
2286 else
2287 dig->linkb = false;
2288
2289 return dig;
2290 }
2291
2292 void
2293 radeon_add_atom_encoder(struct drm_device *dev,
2294 uint32_t encoder_enum,
2295 uint32_t supported_device,
2296 u16 caps)
2297 {
2298 struct radeon_device *rdev = dev->dev_private;
2299 struct drm_encoder *encoder;
2300 struct radeon_encoder *radeon_encoder;
2301
2302 /* see if we already added it */
2303 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2304 radeon_encoder = to_radeon_encoder(encoder);
2305 if (radeon_encoder->encoder_enum == encoder_enum) {
2306 radeon_encoder->devices |= supported_device;
2307 return;
2308 }
2309
2310 }
2311
2312 /* add a new one */
2313 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2314 if (!radeon_encoder)
2315 return;
2316
2317 encoder = &radeon_encoder->base;
2318 switch (rdev->num_crtc) {
2319 case 1:
2320 encoder->possible_crtcs = 0x1;
2321 break;
2322 case 2:
2323 default:
2324 encoder->possible_crtcs = 0x3;
2325 break;
2326 case 4:
2327 encoder->possible_crtcs = 0xf;
2328 break;
2329 case 6:
2330 encoder->possible_crtcs = 0x3f;
2331 break;
2332 }
2333
2334 radeon_encoder->enc_priv = NULL;
2335
2336 radeon_encoder->encoder_enum = encoder_enum;
2337 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2338 radeon_encoder->devices = supported_device;
2339 radeon_encoder->rmx_type = RMX_OFF;
2340 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2341 radeon_encoder->is_ext_encoder = false;
2342 radeon_encoder->caps = caps;
2343
2344 switch (radeon_encoder->encoder_id) {
2345 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2346 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2347 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2348 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2349 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2350 radeon_encoder->rmx_type = RMX_FULL;
2351 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2352 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2353 } else {
2354 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2355 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2356 }
2357 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2358 break;
2359 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2360 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2361 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2362 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2363 break;
2364 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2365 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2366 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2367 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2368 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2369 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2370 break;
2371 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2372 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2373 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2374 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2375 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2376 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2377 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2378 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2379 radeon_encoder->rmx_type = RMX_FULL;
2380 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2381 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2382 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2383 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2384 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2385 } else {
2386 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2387 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2388 }
2389 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2390 break;
2391 case ENCODER_OBJECT_ID_SI170B:
2392 case ENCODER_OBJECT_ID_CH7303:
2393 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2394 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2395 case ENCODER_OBJECT_ID_TITFP513:
2396 case ENCODER_OBJECT_ID_VT1623:
2397 case ENCODER_OBJECT_ID_HDMI_SI1930:
2398 case ENCODER_OBJECT_ID_TRAVIS:
2399 case ENCODER_OBJECT_ID_NUTMEG:
2400 /* these are handled by the primary encoders */
2401 radeon_encoder->is_ext_encoder = true;
2402 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2403 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2404 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2405 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2406 else
2407 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2408 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2409 break;
2410 }
2411 }
linux-next