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Add linux-next specific files for 20110831
[linux-2.6/next.git] / drivers / hwmon / w83627ehf.c
blobeca61b3a58e74d9eab7536ac62f17f994cb2f452
1 /*
2 w83627ehf - Driver for the hardware monitoring functionality of
3 the Winbond W83627EHF Super-I/O chip
4 Copyright (C) 2005 Jean Delvare <khali@linux-fr.org>
5 Copyright (C) 2006 Yuan Mu (Winbond),
6 Rudolf Marek <r.marek@assembler.cz>
7 David Hubbard <david.c.hubbard@gmail.com>
8 Daniel J Blueman <daniel.blueman@gmail.com>
9 Copyright (C) 2010 Sheng-Yuan Huang (Nuvoton) (PS00)
10
11 Shamelessly ripped from the w83627hf driver
12 Copyright (C) 2003 Mark Studebaker
13
14 Thanks to Leon Moonen, Steve Cliffe and Grant Coady for their help
15 in testing and debugging this driver.
16
17 This driver also supports the W83627EHG, which is the lead-free
18 version of the W83627EHF.
19
20 This program is free software; you can redistribute it and/or modify
21 it under the terms of the GNU General Public License as published by
22 the Free Software Foundation; either version 2 of the License, or
23 (at your option) any later version.
24
25 This program is distributed in the hope that it will be useful,
26 but WITHOUT ANY WARRANTY; without even the implied warranty of
27 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 GNU General Public License for more details.
29
30 You should have received a copy of the GNU General Public License
31 along with this program; if not, write to the Free Software
32 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
33
34
35 Supports the following chips:
36
37 Chip #vin #fan #pwm #temp chip IDs man ID
38 w83627ehf 10 5 4 3 0x8850 0x88 0x5ca3
39 0x8860 0xa1
40 w83627dhg 9 5 4 3 0xa020 0xc1 0x5ca3
41 w83627dhg-p 9 5 4 3 0xb070 0xc1 0x5ca3
42 w83667hg 9 5 3 3 0xa510 0xc1 0x5ca3
43 w83667hg-b 9 5 3 4 0xb350 0xc1 0x5ca3
44 nct6775f 9 4 3 9 0xb470 0xc1 0x5ca3
45 nct6776f 9 5 3 9 0xC330 0xc1 0x5ca3
46 */
47
48 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
49
50 #include <linux/module.h>
51 #include <linux/init.h>
52 #include <linux/slab.h>
53 #include <linux/jiffies.h>
54 #include <linux/platform_device.h>
55 #include <linux/hwmon.h>
56 #include <linux/hwmon-sysfs.h>
57 #include <linux/hwmon-vid.h>
58 #include <linux/err.h>
59 #include <linux/mutex.h>
60 #include <linux/acpi.h>
61 #include <linux/io.h>
62 #include "lm75.h"
63
64 enum kinds { w83627ehf, w83627dhg, w83627dhg_p, w83667hg, w83667hg_b, nct6775,
65 nct6776 };
66
67 /* used to set data->name = w83627ehf_device_names[data->sio_kind] */
68 static const char * const w83627ehf_device_names[] = {
69 "w83627ehf",
70 "w83627dhg",
71 "w83627dhg",
72 "w83667hg",
73 "w83667hg",
74 "nct6775",
75 "nct6776",
76 };
77
78 static unsigned short force_id;
79 module_param(force_id, ushort, 0);
80 MODULE_PARM_DESC(force_id, "Override the detected device ID");
81
82 static unsigned short fan_debounce;
83 module_param(fan_debounce, ushort, 0);
84 MODULE_PARM_DESC(fan_debounce, "Enable debouncing for fan RPM signal");
85
86 #define DRVNAME "w83627ehf"
87
88 /*
89 * Super-I/O constants and functions
90 */
91
92 #define W83627EHF_LD_HWM 0x0b
93 #define W83667HG_LD_VID 0x0d
94
95 #define SIO_REG_LDSEL 0x07 /* Logical device select */
96 #define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
97 #define SIO_REG_EN_VRM10 0x2C /* GPIO3, GPIO4 selection */
98 #define SIO_REG_ENABLE 0x30 /* Logical device enable */
99 #define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
100 #define SIO_REG_VID_CTRL 0xF0 /* VID control */
101 #define SIO_REG_VID_DATA 0xF1 /* VID data */
102
103 #define SIO_W83627EHF_ID 0x8850
104 #define SIO_W83627EHG_ID 0x8860
105 #define SIO_W83627DHG_ID 0xa020
106 #define SIO_W83627DHG_P_ID 0xb070
107 #define SIO_W83667HG_ID 0xa510
108 #define SIO_W83667HG_B_ID 0xb350
109 #define SIO_NCT6775_ID 0xb470
110 #define SIO_NCT6776_ID 0xc330
111 #define SIO_ID_MASK 0xFFF0
112
113 static inline void
114 superio_outb(int ioreg, int reg, int val)
115 {
116 outb(reg, ioreg);
117 outb(val, ioreg + 1);
118 }
119
120 static inline int
121 superio_inb(int ioreg, int reg)
122 {
123 outb(reg, ioreg);
124 return inb(ioreg + 1);
125 }
126
127 static inline void
128 superio_select(int ioreg, int ld)
129 {
130 outb(SIO_REG_LDSEL, ioreg);
131 outb(ld, ioreg + 1);
132 }
133
134 static inline void
135 superio_enter(int ioreg)
136 {
137 outb(0x87, ioreg);
138 outb(0x87, ioreg);
139 }
140
141 static inline void
142 superio_exit(int ioreg)
143 {
144 outb(0xaa, ioreg);
145 outb(0x02, ioreg);
146 outb(0x02, ioreg + 1);
147 }
148
149 /*
150 * ISA constants
151 */
152
153 #define IOREGION_ALIGNMENT (~7)
154 #define IOREGION_OFFSET 5
155 #define IOREGION_LENGTH 2
156 #define ADDR_REG_OFFSET 0
157 #define DATA_REG_OFFSET 1
158
159 #define W83627EHF_REG_BANK 0x4E
160 #define W83627EHF_REG_CONFIG 0x40
161
162 /* Not currently used:
163 * REG_MAN_ID has the value 0x5ca3 for all supported chips.
164 * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
165 * REG_MAN_ID is at port 0x4f
166 * REG_CHIP_ID is at port 0x58 */
167
168 static const u16 W83627EHF_REG_FAN[] = { 0x28, 0x29, 0x2a, 0x3f, 0x553 };
169 static const u16 W83627EHF_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d, 0x3e, 0x55c };
170
171 /* The W83627EHF registers for nr=7,8,9 are in bank 5 */
172 #define W83627EHF_REG_IN_MAX(nr) ((nr < 7) ? (0x2b + (nr) * 2) : \
173 (0x554 + (((nr) - 7) * 2)))
174 #define W83627EHF_REG_IN_MIN(nr) ((nr < 7) ? (0x2c + (nr) * 2) : \
175 (0x555 + (((nr) - 7) * 2)))
176 #define W83627EHF_REG_IN(nr) ((nr < 7) ? (0x20 + (nr)) : \
177 (0x550 + (nr) - 7))
178
179 static const u16 W83627EHF_REG_TEMP[] = { 0x27, 0x150, 0x250, 0x7e };
180 static const u16 W83627EHF_REG_TEMP_HYST[] = { 0x3a, 0x153, 0x253, 0 };
181 static const u16 W83627EHF_REG_TEMP_OVER[] = { 0x39, 0x155, 0x255, 0 };
182 static const u16 W83627EHF_REG_TEMP_CONFIG[] = { 0, 0x152, 0x252, 0 };
183
184 /* Fan clock dividers are spread over the following five registers */
185 #define W83627EHF_REG_FANDIV1 0x47
186 #define W83627EHF_REG_FANDIV2 0x4B
187 #define W83627EHF_REG_VBAT 0x5D
188 #define W83627EHF_REG_DIODE 0x59
189 #define W83627EHF_REG_SMI_OVT 0x4C
190
191 /* NCT6775F has its own fan divider registers */
192 #define NCT6775_REG_FANDIV1 0x506
193 #define NCT6775_REG_FANDIV2 0x507
194 #define NCT6775_REG_FAN_DEBOUNCE 0xf0
195
196 #define W83627EHF_REG_ALARM1 0x459
197 #define W83627EHF_REG_ALARM2 0x45A
198 #define W83627EHF_REG_ALARM3 0x45B
199
200 #define W83627EHF_REG_CASEOPEN_DET 0x42 /* SMI STATUS #2 */
201 #define W83627EHF_REG_CASEOPEN_CLR 0x46 /* SMI MASK #3 */
202
203 /* SmartFan registers */
204 #define W83627EHF_REG_FAN_STEPUP_TIME 0x0f
205 #define W83627EHF_REG_FAN_STEPDOWN_TIME 0x0e
206
207 /* DC or PWM output fan configuration */
208 static const u8 W83627EHF_REG_PWM_ENABLE[] = {
209 0x04, /* SYS FAN0 output mode and PWM mode */
210 0x04, /* CPU FAN0 output mode and PWM mode */
211 0x12, /* AUX FAN mode */
212 0x62, /* CPU FAN1 mode */
213 };
214
215 static const u8 W83627EHF_PWM_MODE_SHIFT[] = { 0, 1, 0, 6 };
216 static const u8 W83627EHF_PWM_ENABLE_SHIFT[] = { 2, 4, 1, 4 };
217
218 /* FAN Duty Cycle, be used to control */
219 static const u16 W83627EHF_REG_PWM[] = { 0x01, 0x03, 0x11, 0x61 };
220 static const u16 W83627EHF_REG_TARGET[] = { 0x05, 0x06, 0x13, 0x63 };
221 static const u8 W83627EHF_REG_TOLERANCE[] = { 0x07, 0x07, 0x14, 0x62 };
222
223 /* Advanced Fan control, some values are common for all fans */
224 static const u16 W83627EHF_REG_FAN_START_OUTPUT[] = { 0x0a, 0x0b, 0x16, 0x65 };
225 static const u16 W83627EHF_REG_FAN_STOP_OUTPUT[] = { 0x08, 0x09, 0x15, 0x64 };
226 static const u16 W83627EHF_REG_FAN_STOP_TIME[] = { 0x0c, 0x0d, 0x17, 0x66 };
227
228 static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_COMMON[]
229 = { 0xff, 0x67, 0xff, 0x69 };
230 static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_COMMON[]
231 = { 0xff, 0x68, 0xff, 0x6a };
232
233 static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B[] = { 0x67, 0x69, 0x6b };
234 static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B[]
235 = { 0x68, 0x6a, 0x6c };
236
237 static const u16 NCT6775_REG_TARGET[] = { 0x101, 0x201, 0x301 };
238 static const u16 NCT6775_REG_FAN_MODE[] = { 0x102, 0x202, 0x302 };
239 static const u16 NCT6775_REG_FAN_STOP_OUTPUT[] = { 0x105, 0x205, 0x305 };
240 static const u16 NCT6775_REG_FAN_START_OUTPUT[] = { 0x106, 0x206, 0x306 };
241 static const u16 NCT6775_REG_FAN_STOP_TIME[] = { 0x107, 0x207, 0x307 };
242 static const u16 NCT6775_REG_PWM[] = { 0x109, 0x209, 0x309 };
243 static const u16 NCT6775_REG_FAN_MAX_OUTPUT[] = { 0x10a, 0x20a, 0x30a };
244 static const u16 NCT6775_REG_FAN_STEP_OUTPUT[] = { 0x10b, 0x20b, 0x30b };
245 static const u16 NCT6775_REG_FAN[] = { 0x630, 0x632, 0x634, 0x636, 0x638 };
246 static const u16 NCT6776_REG_FAN_MIN[] = { 0x63a, 0x63c, 0x63e, 0x640, 0x642};
247
248 static const u16 NCT6775_REG_TEMP[]
249 = { 0x27, 0x150, 0x250, 0x73, 0x75, 0x77, 0x62b, 0x62c, 0x62d };
250 static const u16 NCT6775_REG_TEMP_CONFIG[]
251 = { 0, 0x152, 0x252, 0, 0, 0, 0x628, 0x629, 0x62A };
252 static const u16 NCT6775_REG_TEMP_HYST[]
253 = { 0x3a, 0x153, 0x253, 0, 0, 0, 0x673, 0x678, 0x67D };
254 static const u16 NCT6775_REG_TEMP_OVER[]
255 = { 0x39, 0x155, 0x255, 0, 0, 0, 0x672, 0x677, 0x67C };
256 static const u16 NCT6775_REG_TEMP_SOURCE[]
257 = { 0x621, 0x622, 0x623, 0x100, 0x200, 0x300, 0x624, 0x625, 0x626 };
258
259 static const char *const w83667hg_b_temp_label[] = {
260 "SYSTIN",
261 "CPUTIN",
262 "AUXTIN",
263 "AMDTSI",
264 "PECI Agent 1",
265 "PECI Agent 2",
266 "PECI Agent 3",
267 "PECI Agent 4"
268 };
269
270 static const char *const nct6775_temp_label[] = {
271 "",
272 "SYSTIN",
273 "CPUTIN",
274 "AUXTIN",
275 "AMD SB-TSI",
276 "PECI Agent 0",
277 "PECI Agent 1",
278 "PECI Agent 2",
279 "PECI Agent 3",
280 "PECI Agent 4",
281 "PECI Agent 5",
282 "PECI Agent 6",
283 "PECI Agent 7",
284 "PCH_CHIP_CPU_MAX_TEMP",
285 "PCH_CHIP_TEMP",
286 "PCH_CPU_TEMP",
287 "PCH_MCH_TEMP",
288 "PCH_DIM0_TEMP",
289 "PCH_DIM1_TEMP",
290 "PCH_DIM2_TEMP",
291 "PCH_DIM3_TEMP"
292 };
293
294 static const char *const nct6776_temp_label[] = {
295 "",
296 "SYSTIN",
297 "CPUTIN",
298 "AUXTIN",
299 "SMBUSMASTER 0",
300 "SMBUSMASTER 1",
301 "SMBUSMASTER 2",
302 "SMBUSMASTER 3",
303 "SMBUSMASTER 4",
304 "SMBUSMASTER 5",
305 "SMBUSMASTER 6",
306 "SMBUSMASTER 7",
307 "PECI Agent 0",
308 "PECI Agent 1",
309 "PCH_CHIP_CPU_MAX_TEMP",
310 "PCH_CHIP_TEMP",
311 "PCH_CPU_TEMP",
312 "PCH_MCH_TEMP",
313 "PCH_DIM0_TEMP",
314 "PCH_DIM1_TEMP",
315 "PCH_DIM2_TEMP",
316 "PCH_DIM3_TEMP",
317 "BYTE_TEMP"
318 };
319
320 #define NUM_REG_TEMP ARRAY_SIZE(NCT6775_REG_TEMP)
321
322 static inline int is_word_sized(u16 reg)
323 {
324 return ((((reg & 0xff00) == 0x100
325 || (reg & 0xff00) == 0x200)
326 && ((reg & 0x00ff) == 0x50
327 || (reg & 0x00ff) == 0x53
328 || (reg & 0x00ff) == 0x55))
329 || (reg & 0xfff0) == 0x630
330 || reg == 0x640 || reg == 0x642
331 || ((reg & 0xfff0) == 0x650
332 && (reg & 0x000f) >= 0x06)
333 || reg == 0x73 || reg == 0x75 || reg == 0x77
334 );
335 }
336
337 /*
338 * Conversions
339 */
340
341 /* 1 is PWM mode, output in ms */
342 static inline unsigned int step_time_from_reg(u8 reg, u8 mode)
343 {
344 return mode ? 100 * reg : 400 * reg;
345 }
346
347 static inline u8 step_time_to_reg(unsigned int msec, u8 mode)
348 {
349 return SENSORS_LIMIT((mode ? (msec + 50) / 100 :
350 (msec + 200) / 400), 1, 255);
351 }
352
353 static unsigned int fan_from_reg8(u16 reg, unsigned int divreg)
354 {
355 if (reg == 0 || reg == 255)
356 return 0;
357 return 1350000U / (reg << divreg);
358 }
359
360 static unsigned int fan_from_reg13(u16 reg, unsigned int divreg)
361 {
362 if ((reg & 0xff1f) == 0xff1f)
363 return 0;
364
365 reg = (reg & 0x1f) | ((reg & 0xff00) >> 3);
366
367 if (reg == 0)
368 return 0;
369
370 return 1350000U / reg;
371 }
372
373 static unsigned int fan_from_reg16(u16 reg, unsigned int divreg)
374 {
375 if (reg == 0 || reg == 0xffff)
376 return 0;
377
378 /*
379 * Even though the registers are 16 bit wide, the fan divisor
380 * still applies.
381 */
382 return 1350000U / (reg << divreg);
383 }
384
385 static inline unsigned int
386 div_from_reg(u8 reg)
387 {
388 return 1 << reg;
389 }
390
391 static inline int
392 temp_from_reg(u16 reg, s16 regval)
393 {
394 if (is_word_sized(reg))
395 return LM75_TEMP_FROM_REG(regval);
396 return regval * 1000;
397 }
398
399 static inline u16
400 temp_to_reg(u16 reg, long temp)
401 {
402 if (is_word_sized(reg))
403 return LM75_TEMP_TO_REG(temp);
404 return DIV_ROUND_CLOSEST(SENSORS_LIMIT(temp, -127000, 128000), 1000);
405 }
406
407 /* Some of analog inputs have internal scaling (2x), 8mV is ADC LSB */
408
409 static u8 scale_in[10] = { 8, 8, 16, 16, 8, 8, 8, 16, 16, 8 };
410
411 static inline long in_from_reg(u8 reg, u8 nr)
412 {
413 return reg * scale_in[nr];
414 }
415
416 static inline u8 in_to_reg(u32 val, u8 nr)
417 {
418 return SENSORS_LIMIT(((val + (scale_in[nr] / 2)) / scale_in[nr]), 0,
419 255);
420 }
421
422 /*
423 * Data structures and manipulation thereof
424 */
425
426 struct w83627ehf_data {
427 int addr; /* IO base of hw monitor block */
428 const char *name;
429
430 struct device *hwmon_dev;
431 struct mutex lock;
432
433 u16 reg_temp[NUM_REG_TEMP];
434 u16 reg_temp_over[NUM_REG_TEMP];
435 u16 reg_temp_hyst[NUM_REG_TEMP];
436 u16 reg_temp_config[NUM_REG_TEMP];
437 u8 temp_src[NUM_REG_TEMP];
438 const char * const *temp_label;
439
440 const u16 *REG_PWM;
441 const u16 *REG_TARGET;
442 const u16 *REG_FAN;
443 const u16 *REG_FAN_MIN;
444 const u16 *REG_FAN_START_OUTPUT;
445 const u16 *REG_FAN_STOP_OUTPUT;
446 const u16 *REG_FAN_STOP_TIME;
447 const u16 *REG_FAN_MAX_OUTPUT;
448 const u16 *REG_FAN_STEP_OUTPUT;
449
450 unsigned int (*fan_from_reg)(u16 reg, unsigned int divreg);
451 unsigned int (*fan_from_reg_min)(u16 reg, unsigned int divreg);
452
453 struct mutex update_lock;
454 char valid; /* !=0 if following fields are valid */
455 unsigned long last_updated; /* In jiffies */
456
457 /* Register values */
458 u8 bank; /* current register bank */
459 u8 in_num; /* number of in inputs we have */
460 u8 in[10]; /* Register value */
461 u8 in_max[10]; /* Register value */
462 u8 in_min[10]; /* Register value */
463 unsigned int rpm[5];
464 u16 fan_min[5];
465 u8 fan_div[5];
466 u8 has_fan; /* some fan inputs can be disabled */
467 u8 has_fan_min; /* some fans don't have min register */
468 bool has_fan_div;
469 u8 temp_type[3];
470 s16 temp[9];
471 s16 temp_max[9];
472 s16 temp_max_hyst[9];
473 u32 alarms;
474 u8 caseopen;
475
476 u8 pwm_mode[4]; /* 0->DC variable voltage, 1->PWM variable duty cycle */
477 u8 pwm_enable[4]; /* 1->manual
478 2->thermal cruise mode (also called SmartFan I)
479 3->fan speed cruise mode
480 4->variable thermal cruise (also called
481 SmartFan III)
482 5->enhanced variable thermal cruise (also called
483 SmartFan IV) */
484 u8 pwm_enable_orig[4]; /* original value of pwm_enable */
485 u8 pwm_num; /* number of pwm */
486 u8 pwm[4];
487 u8 target_temp[4];
488 u8 tolerance[4];
489
490 u8 fan_start_output[4]; /* minimum fan speed when spinning up */
491 u8 fan_stop_output[4]; /* minimum fan speed when spinning down */
492 u8 fan_stop_time[4]; /* time at minimum before disabling fan */
493 u8 fan_max_output[4]; /* maximum fan speed */
494 u8 fan_step_output[4]; /* rate of change output value */
495
496 u8 vid;
497 u8 vrm;
498
499 u16 have_temp;
500 u8 in6_skip;
501 };
502
503 struct w83627ehf_sio_data {
504 int sioreg;
505 enum kinds kind;
506 };
507
508 /*
509 * On older chips, only registers 0x50-0x5f are banked.
510 * On more recent chips, all registers are banked.
511 * Assume that is the case and set the bank number for each access.
512 * Cache the bank number so it only needs to be set if it changes.
513 */
514 static inline void w83627ehf_set_bank(struct w83627ehf_data *data, u16 reg)
515 {
516 u8 bank = reg >> 8;
517 if (data->bank != bank) {
518 outb_p(W83627EHF_REG_BANK, data->addr + ADDR_REG_OFFSET);
519 outb_p(bank, data->addr + DATA_REG_OFFSET);
520 data->bank = bank;
521 }
522 }
523
524 static u16 w83627ehf_read_value(struct w83627ehf_data *data, u16 reg)
525 {
526 int res, word_sized = is_word_sized(reg);
527
528 mutex_lock(&data->lock);
529
530 w83627ehf_set_bank(data, reg);
531 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
532 res = inb_p(data->addr + DATA_REG_OFFSET);
533 if (word_sized) {
534 outb_p((reg & 0xff) + 1,
535 data->addr + ADDR_REG_OFFSET);
536 res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET);
537 }
538
539 mutex_unlock(&data->lock);
540 return res;
541 }
542
543 static int w83627ehf_write_value(struct w83627ehf_data *data, u16 reg,
544 u16 value)
545 {
546 int word_sized = is_word_sized(reg);
547
548 mutex_lock(&data->lock);
549
550 w83627ehf_set_bank(data, reg);
551 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
552 if (word_sized) {
553 outb_p(value >> 8, data->addr + DATA_REG_OFFSET);
554 outb_p((reg & 0xff) + 1,
555 data->addr + ADDR_REG_OFFSET);
556 }
557 outb_p(value & 0xff, data->addr + DATA_REG_OFFSET);
558
559 mutex_unlock(&data->lock);
560 return 0;
561 }
562
563 /* This function assumes that the caller holds data->update_lock */
564 static void nct6775_write_fan_div(struct w83627ehf_data *data, int nr)
565 {
566 u8 reg;
567
568 switch (nr) {
569 case 0:
570 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV1) & 0x70)
571 | (data->fan_div[0] & 0x7);
572 w83627ehf_write_value(data, NCT6775_REG_FANDIV1, reg);
573 break;
574 case 1:
575 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV1) & 0x7)
576 | ((data->fan_div[1] << 4) & 0x70);
577 w83627ehf_write_value(data, NCT6775_REG_FANDIV1, reg);
578 case 2:
579 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV2) & 0x70)
580 | (data->fan_div[2] & 0x7);
581 w83627ehf_write_value(data, NCT6775_REG_FANDIV2, reg);
582 break;
583 case 3:
584 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV2) & 0x7)
585 | ((data->fan_div[3] << 4) & 0x70);
586 w83627ehf_write_value(data, NCT6775_REG_FANDIV2, reg);
587 break;
588 }
589 }
590
591 /* This function assumes that the caller holds data->update_lock */
592 static void w83627ehf_write_fan_div(struct w83627ehf_data *data, int nr)
593 {
594 u8 reg;
595
596 switch (nr) {
597 case 0:
598 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0xcf)
599 | ((data->fan_div[0] & 0x03) << 4);
600 /* fan5 input control bit is write only, compute the value */
601 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
602 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
603 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xdf)
604 | ((data->fan_div[0] & 0x04) << 3);
605 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
606 break;
607 case 1:
608 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0x3f)
609 | ((data->fan_div[1] & 0x03) << 6);
610 /* fan5 input control bit is write only, compute the value */
611 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
612 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
613 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xbf)
614 | ((data->fan_div[1] & 0x04) << 4);
615 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
616 break;
617 case 2:
618 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV2) & 0x3f)
619 | ((data->fan_div[2] & 0x03) << 6);
620 w83627ehf_write_value(data, W83627EHF_REG_FANDIV2, reg);
621 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0x7f)
622 | ((data->fan_div[2] & 0x04) << 5);
623 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
624 break;
625 case 3:
626 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0xfc)
627 | (data->fan_div[3] & 0x03);
628 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
629 reg = (w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT) & 0x7f)
630 | ((data->fan_div[3] & 0x04) << 5);
631 w83627ehf_write_value(data, W83627EHF_REG_SMI_OVT, reg);
632 break;
633 case 4:
634 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0x73)
635 | ((data->fan_div[4] & 0x03) << 2)
636 | ((data->fan_div[4] & 0x04) << 5);
637 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
638 break;
639 }
640 }
641
642 static void w83627ehf_write_fan_div_common(struct device *dev,
643 struct w83627ehf_data *data, int nr)
644 {
645 struct w83627ehf_sio_data *sio_data = dev->platform_data;
646
647 if (sio_data->kind == nct6776)
648 ; /* no dividers, do nothing */
649 else if (sio_data->kind == nct6775)
650 nct6775_write_fan_div(data, nr);
651 else
652 w83627ehf_write_fan_div(data, nr);
653 }
654
655 static void nct6775_update_fan_div(struct w83627ehf_data *data)
656 {
657 u8 i;
658
659 i = w83627ehf_read_value(data, NCT6775_REG_FANDIV1);
660 data->fan_div[0] = i & 0x7;
661 data->fan_div[1] = (i & 0x70) >> 4;
662 i = w83627ehf_read_value(data, NCT6775_REG_FANDIV2);
663 data->fan_div[2] = i & 0x7;
664 if (data->has_fan & (1<<3))
665 data->fan_div[3] = (i & 0x70) >> 4;
666 }
667
668 static void w83627ehf_update_fan_div(struct w83627ehf_data *data)
669 {
670 int i;
671
672 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
673 data->fan_div[0] = (i >> 4) & 0x03;
674 data->fan_div[1] = (i >> 6) & 0x03;
675 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV2);
676 data->fan_div[2] = (i >> 6) & 0x03;
677 i = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
678 data->fan_div[0] |= (i >> 3) & 0x04;
679 data->fan_div[1] |= (i >> 4) & 0x04;
680 data->fan_div[2] |= (i >> 5) & 0x04;
681 if (data->has_fan & ((1 << 3) | (1 << 4))) {
682 i = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
683 data->fan_div[3] = i & 0x03;
684 data->fan_div[4] = ((i >> 2) & 0x03)
685 | ((i >> 5) & 0x04);
686 }
687 if (data->has_fan & (1 << 3)) {
688 i = w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT);
689 data->fan_div[3] |= (i >> 5) & 0x04;
690 }
691 }
692
693 static void w83627ehf_update_fan_div_common(struct device *dev,
694 struct w83627ehf_data *data)
695 {
696 struct w83627ehf_sio_data *sio_data = dev->platform_data;
697
698 if (sio_data->kind == nct6776)
699 ; /* no dividers, do nothing */
700 else if (sio_data->kind == nct6775)
701 nct6775_update_fan_div(data);
702 else
703 w83627ehf_update_fan_div(data);
704 }
705
706 static void nct6775_update_pwm(struct w83627ehf_data *data)
707 {
708 int i;
709 int pwmcfg, fanmodecfg;
710
711 for (i = 0; i < data->pwm_num; i++) {
712 pwmcfg = w83627ehf_read_value(data,
713 W83627EHF_REG_PWM_ENABLE[i]);
714 fanmodecfg = w83627ehf_read_value(data,
715 NCT6775_REG_FAN_MODE[i]);
716 data->pwm_mode[i] =
717 ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1) ? 0 : 1;
718 data->pwm_enable[i] = ((fanmodecfg >> 4) & 7) + 1;
719 data->tolerance[i] = fanmodecfg & 0x0f;
720 data->pwm[i] = w83627ehf_read_value(data, data->REG_PWM[i]);
721 }
722 }
723
724 static void w83627ehf_update_pwm(struct w83627ehf_data *data)
725 {
726 int i;
727 int pwmcfg = 0, tolerance = 0; /* shut up the compiler */
728
729 for (i = 0; i < data->pwm_num; i++) {
730 if (!(data->has_fan & (1 << i)))
731 continue;
732
733 /* pwmcfg, tolerance mapped for i=0, i=1 to same reg */
734 if (i != 1) {
735 pwmcfg = w83627ehf_read_value(data,
736 W83627EHF_REG_PWM_ENABLE[i]);
737 tolerance = w83627ehf_read_value(data,
738 W83627EHF_REG_TOLERANCE[i]);
739 }
740 data->pwm_mode[i] =
741 ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1) ? 0 : 1;
742 data->pwm_enable[i] = ((pwmcfg >> W83627EHF_PWM_ENABLE_SHIFT[i])
743 & 3) + 1;
744 data->pwm[i] = w83627ehf_read_value(data, data->REG_PWM[i]);
745
746 data->tolerance[i] = (tolerance >> (i == 1 ? 4 : 0)) & 0x0f;
747 }
748 }
749
750 static void w83627ehf_update_pwm_common(struct device *dev,
751 struct w83627ehf_data *data)
752 {
753 struct w83627ehf_sio_data *sio_data = dev->platform_data;
754
755 if (sio_data->kind == nct6775 || sio_data->kind == nct6776)
756 nct6775_update_pwm(data);
757 else
758 w83627ehf_update_pwm(data);
759 }
760
761 static struct w83627ehf_data *w83627ehf_update_device(struct device *dev)
762 {
763 struct w83627ehf_data *data = dev_get_drvdata(dev);
764 struct w83627ehf_sio_data *sio_data = dev->platform_data;
765
766 int i;
767
768 mutex_lock(&data->update_lock);
769
770 if (time_after(jiffies, data->last_updated + HZ + HZ/2)
771 || !data->valid) {
772 /* Fan clock dividers */
773 w83627ehf_update_fan_div_common(dev, data);
774
775 /* Measured voltages and limits */
776 for (i = 0; i < data->in_num; i++) {
777 data->in[i] = w83627ehf_read_value(data,
778 W83627EHF_REG_IN(i));
779 data->in_min[i] = w83627ehf_read_value(data,
780 W83627EHF_REG_IN_MIN(i));
781 data->in_max[i] = w83627ehf_read_value(data,
782 W83627EHF_REG_IN_MAX(i));
783 }
784
785 /* Measured fan speeds and limits */
786 for (i = 0; i < 5; i++) {
787 u16 reg;
788
789 if (!(data->has_fan & (1 << i)))
790 continue;
791
792 reg = w83627ehf_read_value(data, data->REG_FAN[i]);
793 data->rpm[i] = data->fan_from_reg(reg,
794 data->fan_div[i]);
795
796 if (data->has_fan_min & (1 << i))
797 data->fan_min[i] = w83627ehf_read_value(data,
798 data->REG_FAN_MIN[i]);
799
800 /* If we failed to measure the fan speed and clock
801 divider can be increased, let's try that for next
802 time */
803 if (data->has_fan_div
804 && (reg >= 0xff || (sio_data->kind == nct6775
805 && reg == 0x00))
806 && data->fan_div[i] < 0x07) {
807 dev_dbg(dev, "Increasing fan%d "
808 "clock divider from %u to %u\n",
809 i + 1, div_from_reg(data->fan_div[i]),
810 div_from_reg(data->fan_div[i] + 1));
811 data->fan_div[i]++;
812 w83627ehf_write_fan_div_common(dev, data, i);
813 /* Preserve min limit if possible */
814 if ((data->has_fan_min & (1 << i))
815 && data->fan_min[i] >= 2
816 && data->fan_min[i] != 255)
817 w83627ehf_write_value(data,
818 data->REG_FAN_MIN[i],
819 (data->fan_min[i] /= 2));
820 }
821 }
822
823 w83627ehf_update_pwm_common(dev, data);
824
825 for (i = 0; i < data->pwm_num; i++) {
826 if (!(data->has_fan & (1 << i)))
827 continue;
828
829 data->fan_start_output[i] =
830 w83627ehf_read_value(data,
831 data->REG_FAN_START_OUTPUT[i]);
832 data->fan_stop_output[i] =
833 w83627ehf_read_value(data,
834 data->REG_FAN_STOP_OUTPUT[i]);
835 data->fan_stop_time[i] =
836 w83627ehf_read_value(data,
837 data->REG_FAN_STOP_TIME[i]);
838
839 if (data->REG_FAN_MAX_OUTPUT &&
840 data->REG_FAN_MAX_OUTPUT[i] != 0xff)
841 data->fan_max_output[i] =
842 w83627ehf_read_value(data,
843 data->REG_FAN_MAX_OUTPUT[i]);
844
845 if (data->REG_FAN_STEP_OUTPUT &&
846 data->REG_FAN_STEP_OUTPUT[i] != 0xff)
847 data->fan_step_output[i] =
848 w83627ehf_read_value(data,
849 data->REG_FAN_STEP_OUTPUT[i]);
850
851 data->target_temp[i] =
852 w83627ehf_read_value(data,
853 data->REG_TARGET[i]) &
854 (data->pwm_mode[i] == 1 ? 0x7f : 0xff);
855 }
856
857 /* Measured temperatures and limits */
858 for (i = 0; i < NUM_REG_TEMP; i++) {
859 if (!(data->have_temp & (1 << i)))
860 continue;
861 data->temp[i] = w83627ehf_read_value(data,
862 data->reg_temp[i]);
863 if (data->reg_temp_over[i])
864 data->temp_max[i]
865 = w83627ehf_read_value(data,
866 data->reg_temp_over[i]);
867 if (data->reg_temp_hyst[i])
868 data->temp_max_hyst[i]
869 = w83627ehf_read_value(data,
870 data->reg_temp_hyst[i]);
871 }
872
873 data->alarms = w83627ehf_read_value(data,
874 W83627EHF_REG_ALARM1) |
875 (w83627ehf_read_value(data,
876 W83627EHF_REG_ALARM2) << 8) |
877 (w83627ehf_read_value(data,
878 W83627EHF_REG_ALARM3) << 16);
879
880 data->caseopen = w83627ehf_read_value(data,
881 W83627EHF_REG_CASEOPEN_DET);
882
883 data->last_updated = jiffies;
884 data->valid = 1;
885 }
886
887 mutex_unlock(&data->update_lock);
888 return data;
889 }
890
891 /*
892 * Sysfs callback functions
893 */
894 #define show_in_reg(reg) \
895 static ssize_t \
896 show_##reg(struct device *dev, struct device_attribute *attr, \
897 char *buf) \
898 { \
899 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
900 struct sensor_device_attribute *sensor_attr = \
901 to_sensor_dev_attr(attr); \
902 int nr = sensor_attr->index; \
903 return sprintf(buf, "%ld\n", in_from_reg(data->reg[nr], nr)); \
904 }
905 show_in_reg(in)
906 show_in_reg(in_min)
907 show_in_reg(in_max)
908
909 #define store_in_reg(REG, reg) \
910 static ssize_t \
911 store_in_##reg(struct device *dev, struct device_attribute *attr, \
912 const char *buf, size_t count) \
913 { \
914 struct w83627ehf_data *data = dev_get_drvdata(dev); \
915 struct sensor_device_attribute *sensor_attr = \
916 to_sensor_dev_attr(attr); \
917 int nr = sensor_attr->index; \
918 unsigned long val; \
919 int err; \
920 err = strict_strtoul(buf, 10, &val); \
921 if (err < 0) \
922 return err; \
923 mutex_lock(&data->update_lock); \
924 data->in_##reg[nr] = in_to_reg(val, nr); \
925 w83627ehf_write_value(data, W83627EHF_REG_IN_##REG(nr), \
926 data->in_##reg[nr]); \
927 mutex_unlock(&data->update_lock); \
928 return count; \
929 }
930
931 store_in_reg(MIN, min)
932 store_in_reg(MAX, max)
933
934 static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
935 char *buf)
936 {
937 struct w83627ehf_data *data = w83627ehf_update_device(dev);
938 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
939 int nr = sensor_attr->index;
940 return sprintf(buf, "%u\n", (data->alarms >> nr) & 0x01);
941 }
942
943 static struct sensor_device_attribute sda_in_input[] = {
944 SENSOR_ATTR(in0_input, S_IRUGO, show_in, NULL, 0),
945 SENSOR_ATTR(in1_input, S_IRUGO, show_in, NULL, 1),
946 SENSOR_ATTR(in2_input, S_IRUGO, show_in, NULL, 2),
947 SENSOR_ATTR(in3_input, S_IRUGO, show_in, NULL, 3),
948 SENSOR_ATTR(in4_input, S_IRUGO, show_in, NULL, 4),
949 SENSOR_ATTR(in5_input, S_IRUGO, show_in, NULL, 5),
950 SENSOR_ATTR(in6_input, S_IRUGO, show_in, NULL, 6),
951 SENSOR_ATTR(in7_input, S_IRUGO, show_in, NULL, 7),
952 SENSOR_ATTR(in8_input, S_IRUGO, show_in, NULL, 8),
953 SENSOR_ATTR(in9_input, S_IRUGO, show_in, NULL, 9),
954 };
955
956 static struct sensor_device_attribute sda_in_alarm[] = {
957 SENSOR_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 0),
958 SENSOR_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 1),
959 SENSOR_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 2),
960 SENSOR_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 3),
961 SENSOR_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 8),
962 SENSOR_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 21),
963 SENSOR_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 20),
964 SENSOR_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 16),
965 SENSOR_ATTR(in8_alarm, S_IRUGO, show_alarm, NULL, 17),
966 SENSOR_ATTR(in9_alarm, S_IRUGO, show_alarm, NULL, 19),
967 };
968
969 static struct sensor_device_attribute sda_in_min[] = {
970 SENSOR_ATTR(in0_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 0),
971 SENSOR_ATTR(in1_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 1),
972 SENSOR_ATTR(in2_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 2),
973 SENSOR_ATTR(in3_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 3),
974 SENSOR_ATTR(in4_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 4),
975 SENSOR_ATTR(in5_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 5),
976 SENSOR_ATTR(in6_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 6),
977 SENSOR_ATTR(in7_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 7),
978 SENSOR_ATTR(in8_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 8),
979 SENSOR_ATTR(in9_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 9),
980 };
981
982 static struct sensor_device_attribute sda_in_max[] = {
983 SENSOR_ATTR(in0_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 0),
984 SENSOR_ATTR(in1_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 1),
985 SENSOR_ATTR(in2_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 2),
986 SENSOR_ATTR(in3_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 3),
987 SENSOR_ATTR(in4_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 4),
988 SENSOR_ATTR(in5_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 5),
989 SENSOR_ATTR(in6_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 6),
990 SENSOR_ATTR(in7_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 7),
991 SENSOR_ATTR(in8_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 8),
992 SENSOR_ATTR(in9_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 9),
993 };
994
995 static ssize_t
996 show_fan(struct device *dev, struct device_attribute *attr, char *buf)
997 {
998 struct w83627ehf_data *data = w83627ehf_update_device(dev);
999 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1000 int nr = sensor_attr->index;
1001 return sprintf(buf, "%d\n", data->rpm[nr]);
1002 }
1003
1004 static ssize_t
1005 show_fan_min(struct device *dev, struct device_attribute *attr, char *buf)
1006 {
1007 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1008 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1009 int nr = sensor_attr->index;
1010 return sprintf(buf, "%d\n",
1011 data->fan_from_reg_min(data->fan_min[nr],
1012 data->fan_div[nr]));
1013 }
1014
1015 static ssize_t
1016 show_fan_div(struct device *dev, struct device_attribute *attr,
1017 char *buf)
1018 {
1019 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1020 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1021 int nr = sensor_attr->index;
1022 return sprintf(buf, "%u\n", div_from_reg(data->fan_div[nr]));
1023 }
1024
1025 static ssize_t
1026 store_fan_min(struct device *dev, struct device_attribute *attr,
1027 const char *buf, size_t count)
1028 {
1029 struct w83627ehf_data *data = dev_get_drvdata(dev);
1030 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1031 int nr = sensor_attr->index;
1032 unsigned long val;
1033 int err;
1034 unsigned int reg;
1035 u8 new_div;
1036
1037 err = strict_strtoul(buf, 10, &val);
1038 if (err < 0)
1039 return err;
1040
1041 mutex_lock(&data->update_lock);
1042 if (!data->has_fan_div) {
1043 /*
1044 * Only NCT6776F for now, so we know that this is a 13 bit
1045 * register
1046 */
1047 if (!val) {
1048 val = 0xff1f;
1049 } else {
1050 if (val > 1350000U)
1051 val = 135000U;
1052 val = 1350000U / val;
1053 val = (val & 0x1f) | ((val << 3) & 0xff00);
1054 }
1055 data->fan_min[nr] = val;
1056 goto done; /* Leave fan divider alone */
1057 }
1058 if (!val) {
1059 /* No min limit, alarm disabled */
1060 data->fan_min[nr] = 255;
1061 new_div = data->fan_div[nr]; /* No change */
1062 dev_info(dev, "fan%u low limit and alarm disabled\n", nr + 1);
1063 } else if ((reg = 1350000U / val) >= 128 * 255) {
1064 /* Speed below this value cannot possibly be represented,
1065 even with the highest divider (128) */
1066 data->fan_min[nr] = 254;
1067 new_div = 7; /* 128 == (1 << 7) */
1068 dev_warn(dev, "fan%u low limit %lu below minimum %u, set to "
1069 "minimum\n", nr + 1, val,
1070 data->fan_from_reg_min(254, 7));
1071 } else if (!reg) {
1072 /* Speed above this value cannot possibly be represented,
1073 even with the lowest divider (1) */
1074 data->fan_min[nr] = 1;
1075 new_div = 0; /* 1 == (1 << 0) */
1076 dev_warn(dev, "fan%u low limit %lu above maximum %u, set to "
1077 "maximum\n", nr + 1, val,
1078 data->fan_from_reg_min(1, 0));
1079 } else {
1080 /* Automatically pick the best divider, i.e. the one such
1081 that the min limit will correspond to a register value
1082 in the 96..192 range */
1083 new_div = 0;
1084 while (reg > 192 && new_div < 7) {
1085 reg >>= 1;
1086 new_div++;
1087 }
1088 data->fan_min[nr] = reg;
1089 }
1090
1091 /* Write both the fan clock divider (if it changed) and the new
1092 fan min (unconditionally) */
1093 if (new_div != data->fan_div[nr]) {
1094 dev_dbg(dev, "fan%u clock divider changed from %u to %u\n",
1095 nr + 1, div_from_reg(data->fan_div[nr]),
1096 div_from_reg(new_div));
1097 data->fan_div[nr] = new_div;
1098 w83627ehf_write_fan_div_common(dev, data, nr);
1099 /* Give the chip time to sample a new speed value */
1100 data->last_updated = jiffies;
1101 }
1102 done:
1103 w83627ehf_write_value(data, data->REG_FAN_MIN[nr],
1104 data->fan_min[nr]);
1105 mutex_unlock(&data->update_lock);
1106
1107 return count;
1108 }
1109
1110 static struct sensor_device_attribute sda_fan_input[] = {
1111 SENSOR_ATTR(fan1_input, S_IRUGO, show_fan, NULL, 0),
1112 SENSOR_ATTR(fan2_input, S_IRUGO, show_fan, NULL, 1),
1113 SENSOR_ATTR(fan3_input, S_IRUGO, show_fan, NULL, 2),
1114 SENSOR_ATTR(fan4_input, S_IRUGO, show_fan, NULL, 3),
1115 SENSOR_ATTR(fan5_input, S_IRUGO, show_fan, NULL, 4),
1116 };
1117
1118 static struct sensor_device_attribute sda_fan_alarm[] = {
1119 SENSOR_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 6),
1120 SENSOR_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 7),
1121 SENSOR_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 11),
1122 SENSOR_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 10),
1123 SENSOR_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 23),
1124 };
1125
1126 static struct sensor_device_attribute sda_fan_min[] = {
1127 SENSOR_ATTR(fan1_min, S_IWUSR | S_IRUGO, show_fan_min,
1128 store_fan_min, 0),
1129 SENSOR_ATTR(fan2_min, S_IWUSR | S_IRUGO, show_fan_min,
1130 store_fan_min, 1),
1131 SENSOR_ATTR(fan3_min, S_IWUSR | S_IRUGO, show_fan_min,
1132 store_fan_min, 2),
1133 SENSOR_ATTR(fan4_min, S_IWUSR | S_IRUGO, show_fan_min,
1134 store_fan_min, 3),
1135 SENSOR_ATTR(fan5_min, S_IWUSR | S_IRUGO, show_fan_min,
1136 store_fan_min, 4),
1137 };
1138
1139 static struct sensor_device_attribute sda_fan_div[] = {
1140 SENSOR_ATTR(fan1_div, S_IRUGO, show_fan_div, NULL, 0),
1141 SENSOR_ATTR(fan2_div, S_IRUGO, show_fan_div, NULL, 1),
1142 SENSOR_ATTR(fan3_div, S_IRUGO, show_fan_div, NULL, 2),
1143 SENSOR_ATTR(fan4_div, S_IRUGO, show_fan_div, NULL, 3),
1144 SENSOR_ATTR(fan5_div, S_IRUGO, show_fan_div, NULL, 4),
1145 };
1146
1147 static ssize_t
1148 show_temp_label(struct device *dev, struct device_attribute *attr, char *buf)
1149 {
1150 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1151 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1152 int nr = sensor_attr->index;
1153 return sprintf(buf, "%s\n", data->temp_label[data->temp_src[nr]]);
1154 }
1155
1156 #define show_temp_reg(addr, reg) \
1157 static ssize_t \
1158 show_##reg(struct device *dev, struct device_attribute *attr, \
1159 char *buf) \
1160 { \
1161 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
1162 struct sensor_device_attribute *sensor_attr = \
1163 to_sensor_dev_attr(attr); \
1164 int nr = sensor_attr->index; \
1165 return sprintf(buf, "%d\n", \
1166 temp_from_reg(data->addr[nr], data->reg[nr])); \
1167 }
1168 show_temp_reg(reg_temp, temp);
1169 show_temp_reg(reg_temp_over, temp_max);
1170 show_temp_reg(reg_temp_hyst, temp_max_hyst);
1171
1172 #define store_temp_reg(addr, reg) \
1173 static ssize_t \
1174 store_##reg(struct device *dev, struct device_attribute *attr, \
1175 const char *buf, size_t count) \
1176 { \
1177 struct w83627ehf_data *data = dev_get_drvdata(dev); \
1178 struct sensor_device_attribute *sensor_attr = \
1179 to_sensor_dev_attr(attr); \
1180 int nr = sensor_attr->index; \
1181 int err; \
1182 long val; \
1183 err = strict_strtol(buf, 10, &val); \
1184 if (err < 0) \
1185 return err; \
1186 mutex_lock(&data->update_lock); \
1187 data->reg[nr] = temp_to_reg(data->addr[nr], val); \
1188 w83627ehf_write_value(data, data->addr[nr], \
1189 data->reg[nr]); \
1190 mutex_unlock(&data->update_lock); \
1191 return count; \
1192 }
1193 store_temp_reg(reg_temp_over, temp_max);
1194 store_temp_reg(reg_temp_hyst, temp_max_hyst);
1195
1196 static ssize_t
1197 show_temp_type(struct device *dev, struct device_attribute *attr, char *buf)
1198 {
1199 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1200 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1201 int nr = sensor_attr->index;
1202 return sprintf(buf, "%d\n", (int)data->temp_type[nr]);
1203 }
1204
1205 static struct sensor_device_attribute sda_temp_input[] = {
1206 SENSOR_ATTR(temp1_input, S_IRUGO, show_temp, NULL, 0),
1207 SENSOR_ATTR(temp2_input, S_IRUGO, show_temp, NULL, 1),
1208 SENSOR_ATTR(temp3_input, S_IRUGO, show_temp, NULL, 2),
1209 SENSOR_ATTR(temp4_input, S_IRUGO, show_temp, NULL, 3),
1210 SENSOR_ATTR(temp5_input, S_IRUGO, show_temp, NULL, 4),
1211 SENSOR_ATTR(temp6_input, S_IRUGO, show_temp, NULL, 5),
1212 SENSOR_ATTR(temp7_input, S_IRUGO, show_temp, NULL, 6),
1213 SENSOR_ATTR(temp8_input, S_IRUGO, show_temp, NULL, 7),
1214 SENSOR_ATTR(temp9_input, S_IRUGO, show_temp, NULL, 8),
1215 };
1216
1217 static struct sensor_device_attribute sda_temp_label[] = {
1218 SENSOR_ATTR(temp1_label, S_IRUGO, show_temp_label, NULL, 0),
1219 SENSOR_ATTR(temp2_label, S_IRUGO, show_temp_label, NULL, 1),
1220 SENSOR_ATTR(temp3_label, S_IRUGO, show_temp_label, NULL, 2),
1221 SENSOR_ATTR(temp4_label, S_IRUGO, show_temp_label, NULL, 3),
1222 SENSOR_ATTR(temp5_label, S_IRUGO, show_temp_label, NULL, 4),
1223 SENSOR_ATTR(temp6_label, S_IRUGO, show_temp_label, NULL, 5),
1224 SENSOR_ATTR(temp7_label, S_IRUGO, show_temp_label, NULL, 6),
1225 SENSOR_ATTR(temp8_label, S_IRUGO, show_temp_label, NULL, 7),
1226 SENSOR_ATTR(temp9_label, S_IRUGO, show_temp_label, NULL, 8),
1227 };
1228
1229 static struct sensor_device_attribute sda_temp_max[] = {
1230 SENSOR_ATTR(temp1_max, S_IRUGO | S_IWUSR, show_temp_max,
1231 store_temp_max, 0),
1232 SENSOR_ATTR(temp2_max, S_IRUGO | S_IWUSR, show_temp_max,
1233 store_temp_max, 1),
1234 SENSOR_ATTR(temp3_max, S_IRUGO | S_IWUSR, show_temp_max,
1235 store_temp_max, 2),
1236 SENSOR_ATTR(temp4_max, S_IRUGO | S_IWUSR, show_temp_max,
1237 store_temp_max, 3),
1238 SENSOR_ATTR(temp5_max, S_IRUGO | S_IWUSR, show_temp_max,
1239 store_temp_max, 4),
1240 SENSOR_ATTR(temp6_max, S_IRUGO | S_IWUSR, show_temp_max,
1241 store_temp_max, 5),
1242 SENSOR_ATTR(temp7_max, S_IRUGO | S_IWUSR, show_temp_max,
1243 store_temp_max, 6),
1244 SENSOR_ATTR(temp8_max, S_IRUGO | S_IWUSR, show_temp_max,
1245 store_temp_max, 7),
1246 SENSOR_ATTR(temp9_max, S_IRUGO | S_IWUSR, show_temp_max,
1247 store_temp_max, 8),
1248 };
1249
1250 static struct sensor_device_attribute sda_temp_max_hyst[] = {
1251 SENSOR_ATTR(temp1_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1252 store_temp_max_hyst, 0),
1253 SENSOR_ATTR(temp2_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1254 store_temp_max_hyst, 1),
1255 SENSOR_ATTR(temp3_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1256 store_temp_max_hyst, 2),
1257 SENSOR_ATTR(temp4_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1258 store_temp_max_hyst, 3),
1259 SENSOR_ATTR(temp5_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1260 store_temp_max_hyst, 4),
1261 SENSOR_ATTR(temp6_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1262 store_temp_max_hyst, 5),
1263 SENSOR_ATTR(temp7_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1264 store_temp_max_hyst, 6),
1265 SENSOR_ATTR(temp8_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1266 store_temp_max_hyst, 7),
1267 SENSOR_ATTR(temp9_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1268 store_temp_max_hyst, 8),
1269 };
1270
1271 static struct sensor_device_attribute sda_temp_alarm[] = {
1272 SENSOR_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 4),
1273 SENSOR_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 5),
1274 SENSOR_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 13),
1275 };
1276
1277 static struct sensor_device_attribute sda_temp_type[] = {
1278 SENSOR_ATTR(temp1_type, S_IRUGO, show_temp_type, NULL, 0),
1279 SENSOR_ATTR(temp2_type, S_IRUGO, show_temp_type, NULL, 1),
1280 SENSOR_ATTR(temp3_type, S_IRUGO, show_temp_type, NULL, 2),
1281 };
1282
1283 #define show_pwm_reg(reg) \
1284 static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1285 char *buf) \
1286 { \
1287 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
1288 struct sensor_device_attribute *sensor_attr = \
1289 to_sensor_dev_attr(attr); \
1290 int nr = sensor_attr->index; \
1291 return sprintf(buf, "%d\n", data->reg[nr]); \
1292 }
1293
1294 show_pwm_reg(pwm_mode)
1295 show_pwm_reg(pwm_enable)
1296 show_pwm_reg(pwm)
1297
1298 static ssize_t
1299 store_pwm_mode(struct device *dev, struct device_attribute *attr,
1300 const char *buf, size_t count)
1301 {
1302 struct w83627ehf_data *data = dev_get_drvdata(dev);
1303 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1304 int nr = sensor_attr->index;
1305 unsigned long val;
1306 int err;
1307 u16 reg;
1308
1309 err = strict_strtoul(buf, 10, &val);
1310 if (err < 0)
1311 return err;
1312
1313 if (val > 1)
1314 return -EINVAL;
1315 mutex_lock(&data->update_lock);
1316 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
1317 data->pwm_mode[nr] = val;
1318 reg &= ~(1 << W83627EHF_PWM_MODE_SHIFT[nr]);
1319 if (!val)
1320 reg |= 1 << W83627EHF_PWM_MODE_SHIFT[nr];
1321 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
1322 mutex_unlock(&data->update_lock);
1323 return count;
1324 }
1325
1326 static ssize_t
1327 store_pwm(struct device *dev, struct device_attribute *attr,
1328 const char *buf, size_t count)
1329 {
1330 struct w83627ehf_data *data = dev_get_drvdata(dev);
1331 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1332 int nr = sensor_attr->index;
1333 unsigned long val;
1334 int err;
1335
1336 err = strict_strtoul(buf, 10, &val);
1337 if (err < 0)
1338 return err;
1339
1340 val = SENSORS_LIMIT(val, 0, 255);
1341
1342 mutex_lock(&data->update_lock);
1343 data->pwm[nr] = val;
1344 w83627ehf_write_value(data, data->REG_PWM[nr], val);
1345 mutex_unlock(&data->update_lock);
1346 return count;
1347 }
1348
1349 static ssize_t
1350 store_pwm_enable(struct device *dev, struct device_attribute *attr,
1351 const char *buf, size_t count)
1352 {
1353 struct w83627ehf_data *data = dev_get_drvdata(dev);
1354 struct w83627ehf_sio_data *sio_data = dev->platform_data;
1355 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1356 int nr = sensor_attr->index;
1357 unsigned long val;
1358 int err;
1359 u16 reg;
1360
1361 err = strict_strtoul(buf, 10, &val);
1362 if (err < 0)
1363 return err;
1364
1365 if (!val || (val > 4 && val != data->pwm_enable_orig[nr]))
1366 return -EINVAL;
1367 /* SmartFan III mode is not supported on NCT6776F */
1368 if (sio_data->kind == nct6776 && val == 4)
1369 return -EINVAL;
1370
1371 mutex_lock(&data->update_lock);
1372 data->pwm_enable[nr] = val;
1373 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
1374 reg = w83627ehf_read_value(data,
1375 NCT6775_REG_FAN_MODE[nr]);
1376 reg &= 0x0f;
1377 reg |= (val - 1) << 4;
1378 w83627ehf_write_value(data,
1379 NCT6775_REG_FAN_MODE[nr], reg);
1380 } else {
1381 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
1382 reg &= ~(0x03 << W83627EHF_PWM_ENABLE_SHIFT[nr]);
1383 reg |= (val - 1) << W83627EHF_PWM_ENABLE_SHIFT[nr];
1384 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
1385 }
1386 mutex_unlock(&data->update_lock);
1387 return count;
1388 }
1389
1390
1391 #define show_tol_temp(reg) \
1392 static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1393 char *buf) \
1394 { \
1395 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
1396 struct sensor_device_attribute *sensor_attr = \
1397 to_sensor_dev_attr(attr); \
1398 int nr = sensor_attr->index; \
1399 return sprintf(buf, "%d\n", data->reg[nr] * 1000); \
1400 }
1401
1402 show_tol_temp(tolerance)
1403 show_tol_temp(target_temp)
1404
1405 static ssize_t
1406 store_target_temp(struct device *dev, struct device_attribute *attr,
1407 const char *buf, size_t count)
1408 {
1409 struct w83627ehf_data *data = dev_get_drvdata(dev);
1410 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1411 int nr = sensor_attr->index;
1412 long val;
1413 int err;
1414
1415 err = strict_strtol(buf, 10, &val);
1416 if (err < 0)
1417 return err;
1418
1419 val = SENSORS_LIMIT(DIV_ROUND_CLOSEST(val, 1000), 0, 127);
1420
1421 mutex_lock(&data->update_lock);
1422 data->target_temp[nr] = val;
1423 w83627ehf_write_value(data, data->REG_TARGET[nr], val);
1424 mutex_unlock(&data->update_lock);
1425 return count;
1426 }
1427
1428 static ssize_t
1429 store_tolerance(struct device *dev, struct device_attribute *attr,
1430 const char *buf, size_t count)
1431 {
1432 struct w83627ehf_data *data = dev_get_drvdata(dev);
1433 struct w83627ehf_sio_data *sio_data = dev->platform_data;
1434 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1435 int nr = sensor_attr->index;
1436 u16 reg;
1437 long val;
1438 int err;
1439
1440 err = strict_strtol(buf, 10, &val);
1441 if (err < 0)
1442 return err;
1443
1444 /* Limit the temp to 0C - 15C */
1445 val = SENSORS_LIMIT(DIV_ROUND_CLOSEST(val, 1000), 0, 15);
1446
1447 mutex_lock(&data->update_lock);
1448 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
1449 /* Limit tolerance further for NCT6776F */
1450 if (sio_data->kind == nct6776 && val > 7)
1451 val = 7;
1452 reg = w83627ehf_read_value(data, NCT6775_REG_FAN_MODE[nr]);
1453 reg = (reg & 0xf0) | val;
1454 w83627ehf_write_value(data, NCT6775_REG_FAN_MODE[nr], reg);
1455 } else {
1456 reg = w83627ehf_read_value(data, W83627EHF_REG_TOLERANCE[nr]);
1457 if (nr == 1)
1458 reg = (reg & 0x0f) | (val << 4);
1459 else
1460 reg = (reg & 0xf0) | val;
1461 w83627ehf_write_value(data, W83627EHF_REG_TOLERANCE[nr], reg);
1462 }
1463 data->tolerance[nr] = val;
1464 mutex_unlock(&data->update_lock);
1465 return count;
1466 }
1467
1468 static struct sensor_device_attribute sda_pwm[] = {
1469 SENSOR_ATTR(pwm1, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0),
1470 SENSOR_ATTR(pwm2, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 1),
1471 SENSOR_ATTR(pwm3, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 2),
1472 SENSOR_ATTR(pwm4, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 3),
1473 };
1474
1475 static struct sensor_device_attribute sda_pwm_mode[] = {
1476 SENSOR_ATTR(pwm1_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1477 store_pwm_mode, 0),
1478 SENSOR_ATTR(pwm2_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1479 store_pwm_mode, 1),
1480 SENSOR_ATTR(pwm3_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1481 store_pwm_mode, 2),
1482 SENSOR_ATTR(pwm4_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1483 store_pwm_mode, 3),
1484 };
1485
1486 static struct sensor_device_attribute sda_pwm_enable[] = {
1487 SENSOR_ATTR(pwm1_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1488 store_pwm_enable, 0),
1489 SENSOR_ATTR(pwm2_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1490 store_pwm_enable, 1),
1491 SENSOR_ATTR(pwm3_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1492 store_pwm_enable, 2),
1493 SENSOR_ATTR(pwm4_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1494 store_pwm_enable, 3),
1495 };
1496
1497 static struct sensor_device_attribute sda_target_temp[] = {
1498 SENSOR_ATTR(pwm1_target, S_IWUSR | S_IRUGO, show_target_temp,
1499 store_target_temp, 0),
1500 SENSOR_ATTR(pwm2_target, S_IWUSR | S_IRUGO, show_target_temp,
1501 store_target_temp, 1),
1502 SENSOR_ATTR(pwm3_target, S_IWUSR | S_IRUGO, show_target_temp,
1503 store_target_temp, 2),
1504 SENSOR_ATTR(pwm4_target, S_IWUSR | S_IRUGO, show_target_temp,
1505 store_target_temp, 3),
1506 };
1507
1508 static struct sensor_device_attribute sda_tolerance[] = {
1509 SENSOR_ATTR(pwm1_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1510 store_tolerance, 0),
1511 SENSOR_ATTR(pwm2_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1512 store_tolerance, 1),
1513 SENSOR_ATTR(pwm3_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1514 store_tolerance, 2),
1515 SENSOR_ATTR(pwm4_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1516 store_tolerance, 3),
1517 };
1518
1519 /* Smart Fan registers */
1520
1521 #define fan_functions(reg, REG) \
1522 static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1523 char *buf) \
1524 { \
1525 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
1526 struct sensor_device_attribute *sensor_attr = \
1527 to_sensor_dev_attr(attr); \
1528 int nr = sensor_attr->index; \
1529 return sprintf(buf, "%d\n", data->reg[nr]); \
1530 } \
1531 static ssize_t \
1532 store_##reg(struct device *dev, struct device_attribute *attr, \
1533 const char *buf, size_t count) \
1534 { \
1535 struct w83627ehf_data *data = dev_get_drvdata(dev); \
1536 struct sensor_device_attribute *sensor_attr = \
1537 to_sensor_dev_attr(attr); \
1538 int nr = sensor_attr->index; \
1539 unsigned long val; \
1540 int err; \
1541 err = strict_strtoul(buf, 10, &val); \
1542 if (err < 0) \
1543 return err; \
1544 val = SENSORS_LIMIT(val, 1, 255); \
1545 mutex_lock(&data->update_lock); \
1546 data->reg[nr] = val; \
1547 w83627ehf_write_value(data, data->REG_##REG[nr], val); \
1548 mutex_unlock(&data->update_lock); \
1549 return count; \
1550 }
1551
1552 fan_functions(fan_start_output, FAN_START_OUTPUT)
1553 fan_functions(fan_stop_output, FAN_STOP_OUTPUT)
1554 fan_functions(fan_max_output, FAN_MAX_OUTPUT)
1555 fan_functions(fan_step_output, FAN_STEP_OUTPUT)
1556
1557 #define fan_time_functions(reg, REG) \
1558 static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1559 char *buf) \
1560 { \
1561 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
1562 struct sensor_device_attribute *sensor_attr = \
1563 to_sensor_dev_attr(attr); \
1564 int nr = sensor_attr->index; \
1565 return sprintf(buf, "%d\n", \
1566 step_time_from_reg(data->reg[nr], \
1567 data->pwm_mode[nr])); \
1568 } \
1569 \
1570 static ssize_t \
1571 store_##reg(struct device *dev, struct device_attribute *attr, \
1572 const char *buf, size_t count) \
1573 { \
1574 struct w83627ehf_data *data = dev_get_drvdata(dev); \
1575 struct sensor_device_attribute *sensor_attr = \
1576 to_sensor_dev_attr(attr); \
1577 int nr = sensor_attr->index; \
1578 unsigned long val; \
1579 int err; \
1580 err = strict_strtoul(buf, 10, &val); \
1581 if (err < 0) \
1582 return err; \
1583 val = step_time_to_reg(val, data->pwm_mode[nr]); \
1584 mutex_lock(&data->update_lock); \
1585 data->reg[nr] = val; \
1586 w83627ehf_write_value(data, W83627EHF_REG_##REG[nr], val); \
1587 mutex_unlock(&data->update_lock); \
1588 return count; \
1589 } \
1590
1591 fan_time_functions(fan_stop_time, FAN_STOP_TIME)
1592
1593 static ssize_t show_name(struct device *dev, struct device_attribute *attr,
1594 char *buf)
1595 {
1596 struct w83627ehf_data *data = dev_get_drvdata(dev);
1597
1598 return sprintf(buf, "%s\n", data->name);
1599 }
1600 static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
1601
1602 static struct sensor_device_attribute sda_sf3_arrays_fan4[] = {
1603 SENSOR_ATTR(pwm4_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1604 store_fan_stop_time, 3),
1605 SENSOR_ATTR(pwm4_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1606 store_fan_start_output, 3),
1607 SENSOR_ATTR(pwm4_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1608 store_fan_stop_output, 3),
1609 SENSOR_ATTR(pwm4_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1610 store_fan_max_output, 3),
1611 SENSOR_ATTR(pwm4_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1612 store_fan_step_output, 3),
1613 };
1614
1615 static struct sensor_device_attribute sda_sf3_arrays[] = {
1616 SENSOR_ATTR(pwm1_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1617 store_fan_stop_time, 0),
1618 SENSOR_ATTR(pwm2_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1619 store_fan_stop_time, 1),
1620 SENSOR_ATTR(pwm3_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1621 store_fan_stop_time, 2),
1622 SENSOR_ATTR(pwm1_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1623 store_fan_start_output, 0),
1624 SENSOR_ATTR(pwm2_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1625 store_fan_start_output, 1),
1626 SENSOR_ATTR(pwm3_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1627 store_fan_start_output, 2),
1628 SENSOR_ATTR(pwm1_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1629 store_fan_stop_output, 0),
1630 SENSOR_ATTR(pwm2_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1631 store_fan_stop_output, 1),
1632 SENSOR_ATTR(pwm3_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1633 store_fan_stop_output, 2),
1634 };
1635
1636
1637 /*
1638 * pwm1 and pwm3 don't support max and step settings on all chips.
1639 * Need to check support while generating/removing attribute files.
1640 */
1641 static struct sensor_device_attribute sda_sf3_max_step_arrays[] = {
1642 SENSOR_ATTR(pwm1_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1643 store_fan_max_output, 0),
1644 SENSOR_ATTR(pwm1_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1645 store_fan_step_output, 0),
1646 SENSOR_ATTR(pwm2_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1647 store_fan_max_output, 1),
1648 SENSOR_ATTR(pwm2_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1649 store_fan_step_output, 1),
1650 SENSOR_ATTR(pwm3_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1651 store_fan_max_output, 2),
1652 SENSOR_ATTR(pwm3_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1653 store_fan_step_output, 2),
1654 };
1655
1656 static ssize_t
1657 show_vid(struct device *dev, struct device_attribute *attr, char *buf)
1658 {
1659 struct w83627ehf_data *data = dev_get_drvdata(dev);
1660 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
1661 }
1662 static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid, NULL);
1663
1664
1665 /* Case open detection */
1666
1667 static ssize_t
1668 show_caseopen(struct device *dev, struct device_attribute *attr, char *buf)
1669 {
1670 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1671
1672 return sprintf(buf, "%d\n",
1673 !!(data->caseopen & to_sensor_dev_attr_2(attr)->index));
1674 }
1675
1676 static ssize_t
1677 clear_caseopen(struct device *dev, struct device_attribute *attr,
1678 const char *buf, size_t count)
1679 {
1680 struct w83627ehf_data *data = dev_get_drvdata(dev);
1681 unsigned long val;
1682 u16 reg, mask;
1683
1684 if (strict_strtoul(buf, 10, &val) || val != 0)
1685 return -EINVAL;
1686
1687 mask = to_sensor_dev_attr_2(attr)->nr;
1688
1689 mutex_lock(&data->update_lock);
1690 reg = w83627ehf_read_value(data, W83627EHF_REG_CASEOPEN_CLR);
1691 w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg | mask);
1692 w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg & ~mask);
1693 data->valid = 0; /* Force cache refresh */
1694 mutex_unlock(&data->update_lock);
1695
1696 return count;
1697 }
1698
1699 static struct sensor_device_attribute_2 sda_caseopen[] = {
1700 SENSOR_ATTR_2(intrusion0_alarm, S_IWUSR | S_IRUGO, show_caseopen,
1701 clear_caseopen, 0x80, 0x10),
1702 SENSOR_ATTR_2(intrusion1_alarm, S_IWUSR | S_IRUGO, show_caseopen,
1703 clear_caseopen, 0x40, 0x40),
1704 };
1705
1706 /*
1707 * Driver and device management
1708 */
1709
1710 static void w83627ehf_device_remove_files(struct device *dev)
1711 {
1712 /* some entries in the following arrays may not have been used in
1713 * device_create_file(), but device_remove_file() will ignore them */
1714 int i;
1715 struct w83627ehf_data *data = dev_get_drvdata(dev);
1716
1717 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++)
1718 device_remove_file(dev, &sda_sf3_arrays[i].dev_attr);
1719 for (i = 0; i < ARRAY_SIZE(sda_sf3_max_step_arrays); i++) {
1720 struct sensor_device_attribute *attr =
1721 &sda_sf3_max_step_arrays[i];
1722 if (data->REG_FAN_STEP_OUTPUT &&
1723 data->REG_FAN_STEP_OUTPUT[attr->index] != 0xff)
1724 device_remove_file(dev, &attr->dev_attr);
1725 }
1726 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++)
1727 device_remove_file(dev, &sda_sf3_arrays_fan4[i].dev_attr);
1728 for (i = 0; i < data->in_num; i++) {
1729 if ((i == 6) && data->in6_skip)
1730 continue;
1731 device_remove_file(dev, &sda_in_input[i].dev_attr);
1732 device_remove_file(dev, &sda_in_alarm[i].dev_attr);
1733 device_remove_file(dev, &sda_in_min[i].dev_attr);
1734 device_remove_file(dev, &sda_in_max[i].dev_attr);
1735 }
1736 for (i = 0; i < 5; i++) {
1737 device_remove_file(dev, &sda_fan_input[i].dev_attr);
1738 device_remove_file(dev, &sda_fan_alarm[i].dev_attr);
1739 device_remove_file(dev, &sda_fan_div[i].dev_attr);
1740 device_remove_file(dev, &sda_fan_min[i].dev_attr);
1741 }
1742 for (i = 0; i < data->pwm_num; i++) {
1743 device_remove_file(dev, &sda_pwm[i].dev_attr);
1744 device_remove_file(dev, &sda_pwm_mode[i].dev_attr);
1745 device_remove_file(dev, &sda_pwm_enable[i].dev_attr);
1746 device_remove_file(dev, &sda_target_temp[i].dev_attr);
1747 device_remove_file(dev, &sda_tolerance[i].dev_attr);
1748 }
1749 for (i = 0; i < NUM_REG_TEMP; i++) {
1750 if (!(data->have_temp & (1 << i)))
1751 continue;
1752 device_remove_file(dev, &sda_temp_input[i].dev_attr);
1753 device_remove_file(dev, &sda_temp_label[i].dev_attr);
1754 device_remove_file(dev, &sda_temp_max[i].dev_attr);
1755 device_remove_file(dev, &sda_temp_max_hyst[i].dev_attr);
1756 if (i > 2)
1757 continue;
1758 device_remove_file(dev, &sda_temp_alarm[i].dev_attr);
1759 device_remove_file(dev, &sda_temp_type[i].dev_attr);
1760 }
1761
1762 device_remove_file(dev, &sda_caseopen[0].dev_attr);
1763 device_remove_file(dev, &sda_caseopen[1].dev_attr);
1764
1765 device_remove_file(dev, &dev_attr_name);
1766 device_remove_file(dev, &dev_attr_cpu0_vid);
1767 }
1768
1769 /* Get the monitoring functions started */
1770 static inline void __devinit w83627ehf_init_device(struct w83627ehf_data *data)
1771 {
1772 int i;
1773 u8 tmp, diode;
1774
1775 /* Start monitoring is needed */
1776 tmp = w83627ehf_read_value(data, W83627EHF_REG_CONFIG);
1777 if (!(tmp & 0x01))
1778 w83627ehf_write_value(data, W83627EHF_REG_CONFIG,
1779 tmp | 0x01);
1780
1781 /* Enable temperature sensors if needed */
1782 for (i = 0; i < NUM_REG_TEMP; i++) {
1783 if (!(data->have_temp & (1 << i)))
1784 continue;
1785 if (!data->reg_temp_config[i])
1786 continue;
1787 tmp = w83627ehf_read_value(data,
1788 data->reg_temp_config[i]);
1789 if (tmp & 0x01)
1790 w83627ehf_write_value(data,
1791 data->reg_temp_config[i],
1792 tmp & 0xfe);
1793 }
1794
1795 /* Enable VBAT monitoring if needed */
1796 tmp = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
1797 if (!(tmp & 0x01))
1798 w83627ehf_write_value(data, W83627EHF_REG_VBAT, tmp | 0x01);
1799
1800 /* Get thermal sensor types */
1801 diode = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
1802 for (i = 0; i < 3; i++) {
1803 if ((tmp & (0x02 << i)))
1804 data->temp_type[i] = (diode & (0x10 << i)) ? 1 : 2;
1805 else
1806 data->temp_type[i] = 4; /* thermistor */
1807 }
1808 }
1809
1810 static void w82627ehf_swap_tempreg(struct w83627ehf_data *data,
1811 int r1, int r2)
1812 {
1813 u16 tmp;
1814
1815 tmp = data->temp_src[r1];
1816 data->temp_src[r1] = data->temp_src[r2];
1817 data->temp_src[r2] = tmp;
1818
1819 tmp = data->reg_temp[r1];
1820 data->reg_temp[r1] = data->reg_temp[r2];
1821 data->reg_temp[r2] = tmp;
1822
1823 tmp = data->reg_temp_over[r1];
1824 data->reg_temp_over[r1] = data->reg_temp_over[r2];
1825 data->reg_temp_over[r2] = tmp;
1826
1827 tmp = data->reg_temp_hyst[r1];
1828 data->reg_temp_hyst[r1] = data->reg_temp_hyst[r2];
1829 data->reg_temp_hyst[r2] = tmp;
1830
1831 tmp = data->reg_temp_config[r1];
1832 data->reg_temp_config[r1] = data->reg_temp_config[r2];
1833 data->reg_temp_config[r2] = tmp;
1834 }
1835
1836 static int __devinit w83627ehf_probe(struct platform_device *pdev)
1837 {
1838 struct device *dev = &pdev->dev;
1839 struct w83627ehf_sio_data *sio_data = dev->platform_data;
1840 struct w83627ehf_data *data;
1841 struct resource *res;
1842 u8 fan3pin, fan4pin, fan4min, fan5pin, en_vrm10;
1843 int i, err = 0;
1844
1845 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
1846 if (!request_region(res->start, IOREGION_LENGTH, DRVNAME)) {
1847 err = -EBUSY;
1848 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
1849 (unsigned long)res->start,
1850 (unsigned long)res->start + IOREGION_LENGTH - 1);
1851 goto exit;
1852 }
1853
1854 data = kzalloc(sizeof(struct w83627ehf_data), GFP_KERNEL);
1855 if (!data) {
1856 err = -ENOMEM;
1857 goto exit_release;
1858 }
1859
1860 data->addr = res->start;
1861 mutex_init(&data->lock);
1862 mutex_init(&data->update_lock);
1863 data->name = w83627ehf_device_names[sio_data->kind];
1864 platform_set_drvdata(pdev, data);
1865
1866 /* 627EHG and 627EHF have 10 voltage inputs; 627DHG and 667HG have 9 */
1867 data->in_num = (sio_data->kind == w83627ehf) ? 10 : 9;
1868 /* 667HG, NCT6775F, and NCT6776F have 3 pwms */
1869 data->pwm_num = (sio_data->kind == w83667hg
1870 || sio_data->kind == w83667hg_b
1871 || sio_data->kind == nct6775
1872 || sio_data->kind == nct6776) ? 3 : 4;
1873
1874 data->have_temp = 0x07;
1875 /* Check temp3 configuration bit for 667HG */
1876 if (sio_data->kind == w83667hg) {
1877 u8 reg;
1878
1879 reg = w83627ehf_read_value(data, W83627EHF_REG_TEMP_CONFIG[2]);
1880 if (reg & 0x01)
1881 data->have_temp &= ~(1 << 2);
1882 else
1883 data->in6_skip = 1; /* either temp3 or in6 */
1884 }
1885
1886 /* Deal with temperature register setup first. */
1887 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
1888 int mask = 0;
1889
1890 /*
1891 * Display temperature sensor output only if it monitors
1892 * a source other than one already reported. Always display
1893 * first three temperature registers, though.
1894 */
1895 for (i = 0; i < NUM_REG_TEMP; i++) {
1896 u8 src;
1897
1898 data->reg_temp[i] = NCT6775_REG_TEMP[i];
1899 data->reg_temp_over[i] = NCT6775_REG_TEMP_OVER[i];
1900 data->reg_temp_hyst[i] = NCT6775_REG_TEMP_HYST[i];
1901 data->reg_temp_config[i] = NCT6775_REG_TEMP_CONFIG[i];
1902
1903 src = w83627ehf_read_value(data,
1904 NCT6775_REG_TEMP_SOURCE[i]);
1905 src &= 0x1f;
1906 if (src && !(mask & (1 << src))) {
1907 data->have_temp |= 1 << i;
1908 mask |= 1 << src;
1909 }
1910
1911 data->temp_src[i] = src;
1912
1913 /*
1914 * Now do some register swapping if index 0..2 don't
1915 * point to SYSTIN(1), CPUIN(2), and AUXIN(3).
1916 * Idea is to have the first three attributes
1917 * report SYSTIN, CPUIN, and AUXIN if possible
1918 * without overriding the basic system configuration.
1919 */
1920 if (i > 0 && data->temp_src[0] != 1
1921 && data->temp_src[i] == 1)
1922 w82627ehf_swap_tempreg(data, 0, i);
1923 if (i > 1 && data->temp_src[1] != 2
1924 && data->temp_src[i] == 2)
1925 w82627ehf_swap_tempreg(data, 1, i);
1926 if (i > 2 && data->temp_src[2] != 3
1927 && data->temp_src[i] == 3)
1928 w82627ehf_swap_tempreg(data, 2, i);
1929 }
1930 if (sio_data->kind == nct6776) {
1931 /*
1932 * On NCT6776, AUXTIN and VIN3 pins are shared.
1933 * Only way to detect it is to check if AUXTIN is used
1934 * as a temperature source, and if that source is
1935 * enabled.
1936 *
1937 * If that is the case, disable in6, which reports VIN3.
1938 * Otherwise disable temp3.
1939 */
1940 if (data->temp_src[2] == 3) {
1941 u8 reg;
1942
1943 if (data->reg_temp_config[2])
1944 reg = w83627ehf_read_value(data,
1945 data->reg_temp_config[2]);
1946 else
1947 reg = 0; /* Assume AUXTIN is used */
1948
1949 if (reg & 0x01)
1950 data->have_temp &= ~(1 << 2);
1951 else
1952 data->in6_skip = 1;
1953 }
1954 data->temp_label = nct6776_temp_label;
1955 } else {
1956 data->temp_label = nct6775_temp_label;
1957 }
1958 } else if (sio_data->kind == w83667hg_b) {
1959 u8 reg;
1960
1961 /*
1962 * Temperature sources are selected with bank 0, registers 0x49
1963 * and 0x4a.
1964 */
1965 for (i = 0; i < ARRAY_SIZE(W83627EHF_REG_TEMP); i++) {
1966 data->reg_temp[i] = W83627EHF_REG_TEMP[i];
1967 data->reg_temp_over[i] = W83627EHF_REG_TEMP_OVER[i];
1968 data->reg_temp_hyst[i] = W83627EHF_REG_TEMP_HYST[i];
1969 data->reg_temp_config[i] = W83627EHF_REG_TEMP_CONFIG[i];
1970 }
1971 reg = w83627ehf_read_value(data, 0x4a);
1972 data->temp_src[0] = reg >> 5;
1973 reg = w83627ehf_read_value(data, 0x49);
1974 data->temp_src[1] = reg & 0x07;
1975 data->temp_src[2] = (reg >> 4) & 0x07;
1976
1977 /*
1978 * W83667HG-B has another temperature register at 0x7e.
1979 * The temperature source is selected with register 0x7d.
1980 * Support it if the source differs from already reported
1981 * sources.
1982 */
1983 reg = w83627ehf_read_value(data, 0x7d);
1984 reg &= 0x07;
1985 if (reg != data->temp_src[0] && reg != data->temp_src[1]
1986 && reg != data->temp_src[2]) {
1987 data->temp_src[3] = reg;
1988 data->have_temp |= 1 << 3;
1989 }
1990
1991 /*
1992 * Chip supports either AUXTIN or VIN3. Try to find out which
1993 * one.
1994 */
1995 reg = w83627ehf_read_value(data, W83627EHF_REG_TEMP_CONFIG[2]);
1996 if (data->temp_src[2] == 2 && (reg & 0x01))
1997 data->have_temp &= ~(1 << 2);
1998
1999 if ((data->temp_src[2] == 2 && (data->have_temp & (1 << 2)))
2000 || (data->temp_src[3] == 2 && (data->have_temp & (1 << 3))))
2001 data->in6_skip = 1;
2002
2003 data->temp_label = w83667hg_b_temp_label;
2004 } else {
2005 /* Temperature sources are fixed */
2006 for (i = 0; i < 3; i++) {
2007 data->reg_temp[i] = W83627EHF_REG_TEMP[i];
2008 data->reg_temp_over[i] = W83627EHF_REG_TEMP_OVER[i];
2009 data->reg_temp_hyst[i] = W83627EHF_REG_TEMP_HYST[i];
2010 data->reg_temp_config[i] = W83627EHF_REG_TEMP_CONFIG[i];
2011 }
2012 }
2013
2014 if (sio_data->kind == nct6775) {
2015 data->has_fan_div = true;
2016 data->fan_from_reg = fan_from_reg16;
2017 data->fan_from_reg_min = fan_from_reg8;
2018 data->REG_PWM = NCT6775_REG_PWM;
2019 data->REG_TARGET = NCT6775_REG_TARGET;
2020 data->REG_FAN = NCT6775_REG_FAN;
2021 data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN;
2022 data->REG_FAN_START_OUTPUT = NCT6775_REG_FAN_START_OUTPUT;
2023 data->REG_FAN_STOP_OUTPUT = NCT6775_REG_FAN_STOP_OUTPUT;
2024 data->REG_FAN_STOP_TIME = NCT6775_REG_FAN_STOP_TIME;
2025 data->REG_FAN_MAX_OUTPUT = NCT6775_REG_FAN_MAX_OUTPUT;
2026 data->REG_FAN_STEP_OUTPUT = NCT6775_REG_FAN_STEP_OUTPUT;
2027 } else if (sio_data->kind == nct6776) {
2028 data->has_fan_div = false;
2029 data->fan_from_reg = fan_from_reg13;
2030 data->fan_from_reg_min = fan_from_reg13;
2031 data->REG_PWM = NCT6775_REG_PWM;
2032 data->REG_TARGET = NCT6775_REG_TARGET;
2033 data->REG_FAN = NCT6775_REG_FAN;
2034 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
2035 data->REG_FAN_START_OUTPUT = NCT6775_REG_FAN_START_OUTPUT;
2036 data->REG_FAN_STOP_OUTPUT = NCT6775_REG_FAN_STOP_OUTPUT;
2037 data->REG_FAN_STOP_TIME = NCT6775_REG_FAN_STOP_TIME;
2038 } else if (sio_data->kind == w83667hg_b) {
2039 data->has_fan_div = true;
2040 data->fan_from_reg = fan_from_reg8;
2041 data->fan_from_reg_min = fan_from_reg8;
2042 data->REG_PWM = W83627EHF_REG_PWM;
2043 data->REG_TARGET = W83627EHF_REG_TARGET;
2044 data->REG_FAN = W83627EHF_REG_FAN;
2045 data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN;
2046 data->REG_FAN_START_OUTPUT = W83627EHF_REG_FAN_START_OUTPUT;
2047 data->REG_FAN_STOP_OUTPUT = W83627EHF_REG_FAN_STOP_OUTPUT;
2048 data->REG_FAN_STOP_TIME = W83627EHF_REG_FAN_STOP_TIME;
2049 data->REG_FAN_MAX_OUTPUT =
2050 W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B;
2051 data->REG_FAN_STEP_OUTPUT =
2052 W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B;
2053 } else {
2054 data->has_fan_div = true;
2055 data->fan_from_reg = fan_from_reg8;
2056 data->fan_from_reg_min = fan_from_reg8;
2057 data->REG_PWM = W83627EHF_REG_PWM;
2058 data->REG_TARGET = W83627EHF_REG_TARGET;
2059 data->REG_FAN = W83627EHF_REG_FAN;
2060 data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN;
2061 data->REG_FAN_START_OUTPUT = W83627EHF_REG_FAN_START_OUTPUT;
2062 data->REG_FAN_STOP_OUTPUT = W83627EHF_REG_FAN_STOP_OUTPUT;
2063 data->REG_FAN_STOP_TIME = W83627EHF_REG_FAN_STOP_TIME;
2064 data->REG_FAN_MAX_OUTPUT =
2065 W83627EHF_REG_FAN_MAX_OUTPUT_COMMON;
2066 data->REG_FAN_STEP_OUTPUT =
2067 W83627EHF_REG_FAN_STEP_OUTPUT_COMMON;
2068 }
2069
2070 /* Initialize the chip */
2071 w83627ehf_init_device(data);
2072
2073 data->vrm = vid_which_vrm();
2074 superio_enter(sio_data->sioreg);
2075 /* Read VID value */
2076 if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b ||
2077 sio_data->kind == nct6775 || sio_data->kind == nct6776) {
2078 /* W83667HG has different pins for VID input and output, so
2079 we can get the VID input values directly at logical device D
2080 0xe3. */
2081 superio_select(sio_data->sioreg, W83667HG_LD_VID);
2082 data->vid = superio_inb(sio_data->sioreg, 0xe3);
2083 err = device_create_file(dev, &dev_attr_cpu0_vid);
2084 if (err)
2085 goto exit_release;
2086 } else {
2087 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
2088 if (superio_inb(sio_data->sioreg, SIO_REG_VID_CTRL) & 0x80) {
2089 /* Set VID input sensibility if needed. In theory the
2090 BIOS should have set it, but in practice it's not
2091 always the case. We only do it for the W83627EHF/EHG
2092 because the W83627DHG is more complex in this
2093 respect. */
2094 if (sio_data->kind == w83627ehf) {
2095 en_vrm10 = superio_inb(sio_data->sioreg,
2096 SIO_REG_EN_VRM10);
2097 if ((en_vrm10 & 0x08) && data->vrm == 90) {
2098 dev_warn(dev, "Setting VID input "
2099 "voltage to TTL\n");
2100 superio_outb(sio_data->sioreg,
2101 SIO_REG_EN_VRM10,
2102 en_vrm10 & ~0x08);
2103 } else if (!(en_vrm10 & 0x08)
2104 && data->vrm == 100) {
2105 dev_warn(dev, "Setting VID input "
2106 "voltage to VRM10\n");
2107 superio_outb(sio_data->sioreg,
2108 SIO_REG_EN_VRM10,
2109 en_vrm10 | 0x08);
2110 }
2111 }
2112
2113 data->vid = superio_inb(sio_data->sioreg,
2114 SIO_REG_VID_DATA);
2115 if (sio_data->kind == w83627ehf) /* 6 VID pins only */
2116 data->vid &= 0x3f;
2117
2118 err = device_create_file(dev, &dev_attr_cpu0_vid);
2119 if (err)
2120 goto exit_release;
2121 } else {
2122 dev_info(dev, "VID pins in output mode, CPU VID not "
2123 "available\n");
2124 }
2125 }
2126
2127 /* fan4 and fan5 share some pins with the GPIO and serial flash */
2128 if (sio_data->kind == nct6775) {
2129 /* On NCT6775, fan4 shares pins with the fdc interface */
2130 fan3pin = 1;
2131 fan4pin = !(superio_inb(sio_data->sioreg, 0x2A) & 0x80);
2132 fan4min = 0;
2133 fan5pin = 0;
2134 } else if (sio_data->kind == nct6776) {
2135 fan3pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x40);
2136 fan4pin = !!(superio_inb(sio_data->sioreg, 0x1C) & 0x01);
2137 fan5pin = !!(superio_inb(sio_data->sioreg, 0x1C) & 0x02);
2138 fan4min = fan4pin;
2139 } else if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b) {
2140 fan3pin = 1;
2141 fan4pin = superio_inb(sio_data->sioreg, 0x27) & 0x40;
2142 fan5pin = superio_inb(sio_data->sioreg, 0x27) & 0x20;
2143 fan4min = fan4pin;
2144 } else {
2145 fan3pin = 1;
2146 fan4pin = !(superio_inb(sio_data->sioreg, 0x29) & 0x06);
2147 fan5pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x02);
2148 fan4min = fan4pin;
2149 }
2150
2151 if (fan_debounce &&
2152 (sio_data->kind == nct6775 || sio_data->kind == nct6776)) {
2153 u8 tmp;
2154
2155 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
2156 tmp = superio_inb(sio_data->sioreg, NCT6775_REG_FAN_DEBOUNCE);
2157 if (sio_data->kind == nct6776)
2158 superio_outb(sio_data->sioreg, NCT6775_REG_FAN_DEBOUNCE,
2159 0x3e | tmp);
2160 else
2161 superio_outb(sio_data->sioreg, NCT6775_REG_FAN_DEBOUNCE,
2162 0x1e | tmp);
2163 pr_info("Enabled fan debounce for chip %s\n", data->name);
2164 }
2165
2166 superio_exit(sio_data->sioreg);
2167
2168 /* It looks like fan4 and fan5 pins can be alternatively used
2169 as fan on/off switches, but fan5 control is write only :/
2170 We assume that if the serial interface is disabled, designers
2171 connected fan5 as input unless they are emitting log 1, which
2172 is not the default. */
2173
2174 data->has_fan = data->has_fan_min = 0x03; /* fan1 and fan2 */
2175
2176 data->has_fan |= (fan3pin << 2);
2177 data->has_fan_min |= (fan3pin << 2);
2178
2179 /*
2180 * NCT6775F and NCT6776F don't have the W83627EHF_REG_FANDIV1 register
2181 */
2182 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
2183 data->has_fan |= (fan4pin << 3) | (fan5pin << 4);
2184 data->has_fan_min |= (fan4min << 3) | (fan5pin << 4);
2185 } else {
2186 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
2187 if ((i & (1 << 2)) && fan4pin) {
2188 data->has_fan |= (1 << 3);
2189 data->has_fan_min |= (1 << 3);
2190 }
2191 if (!(i & (1 << 1)) && fan5pin) {
2192 data->has_fan |= (1 << 4);
2193 data->has_fan_min |= (1 << 4);
2194 }
2195 }
2196
2197 /* Read fan clock dividers immediately */
2198 w83627ehf_update_fan_div_common(dev, data);
2199
2200 /* Read pwm data to save original values */
2201 w83627ehf_update_pwm_common(dev, data);
2202 for (i = 0; i < data->pwm_num; i++)
2203 data->pwm_enable_orig[i] = data->pwm_enable[i];
2204
2205 /* Read pwm data to save original values */
2206 w83627ehf_update_pwm_common(dev, data);
2207 for (i = 0; i < data->pwm_num; i++)
2208 data->pwm_enable_orig[i] = data->pwm_enable[i];
2209
2210 /* Register sysfs hooks */
2211 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++) {
2212 err = device_create_file(dev, &sda_sf3_arrays[i].dev_attr);
2213 if (err)
2214 goto exit_remove;
2215 }
2216
2217 for (i = 0; i < ARRAY_SIZE(sda_sf3_max_step_arrays); i++) {
2218 struct sensor_device_attribute *attr =
2219 &sda_sf3_max_step_arrays[i];
2220 if (data->REG_FAN_STEP_OUTPUT &&
2221 data->REG_FAN_STEP_OUTPUT[attr->index] != 0xff) {
2222 err = device_create_file(dev, &attr->dev_attr);
2223 if (err)
2224 goto exit_remove;
2225 }
2226 }
2227 /* if fan4 is enabled create the sf3 files for it */
2228 if ((data->has_fan & (1 << 3)) && data->pwm_num >= 4)
2229 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++) {
2230 err = device_create_file(dev,
2231 &sda_sf3_arrays_fan4[i].dev_attr);
2232 if (err)
2233 goto exit_remove;
2234 }
2235
2236 for (i = 0; i < data->in_num; i++) {
2237 if ((i == 6) && data->in6_skip)
2238 continue;
2239 if ((err = device_create_file(dev, &sda_in_input[i].dev_attr))
2240 || (err = device_create_file(dev,
2241 &sda_in_alarm[i].dev_attr))
2242 || (err = device_create_file(dev,
2243 &sda_in_min[i].dev_attr))
2244 || (err = device_create_file(dev,
2245 &sda_in_max[i].dev_attr)))
2246 goto exit_remove;
2247 }
2248
2249 for (i = 0; i < 5; i++) {
2250 if (data->has_fan & (1 << i)) {
2251 if ((err = device_create_file(dev,
2252 &sda_fan_input[i].dev_attr))
2253 || (err = device_create_file(dev,
2254 &sda_fan_alarm[i].dev_attr)))
2255 goto exit_remove;
2256 if (sio_data->kind != nct6776) {
2257 err = device_create_file(dev,
2258 &sda_fan_div[i].dev_attr);
2259 if (err)
2260 goto exit_remove;
2261 }
2262 if (data->has_fan_min & (1 << i)) {
2263 err = device_create_file(dev,
2264 &sda_fan_min[i].dev_attr);
2265 if (err)
2266 goto exit_remove;
2267 }
2268 if (i < data->pwm_num &&
2269 ((err = device_create_file(dev,
2270 &sda_pwm[i].dev_attr))
2271 || (err = device_create_file(dev,
2272 &sda_pwm_mode[i].dev_attr))
2273 || (err = device_create_file(dev,
2274 &sda_pwm_enable[i].dev_attr))
2275 || (err = device_create_file(dev,
2276 &sda_target_temp[i].dev_attr))
2277 || (err = device_create_file(dev,
2278 &sda_tolerance[i].dev_attr))))
2279 goto exit_remove;
2280 }
2281 }
2282
2283 for (i = 0; i < NUM_REG_TEMP; i++) {
2284 if (!(data->have_temp & (1 << i)))
2285 continue;
2286 err = device_create_file(dev, &sda_temp_input[i].dev_attr);
2287 if (err)
2288 goto exit_remove;
2289 if (data->temp_label) {
2290 err = device_create_file(dev,
2291 &sda_temp_label[i].dev_attr);
2292 if (err)
2293 goto exit_remove;
2294 }
2295 if (data->reg_temp_over[i]) {
2296 err = device_create_file(dev,
2297 &sda_temp_max[i].dev_attr);
2298 if (err)
2299 goto exit_remove;
2300 }
2301 if (data->reg_temp_hyst[i]) {
2302 err = device_create_file(dev,
2303 &sda_temp_max_hyst[i].dev_attr);
2304 if (err)
2305 goto exit_remove;
2306 }
2307 if (i > 2)
2308 continue;
2309 if ((err = device_create_file(dev,
2310 &sda_temp_alarm[i].dev_attr))
2311 || (err = device_create_file(dev,
2312 &sda_temp_type[i].dev_attr)))
2313 goto exit_remove;
2314 }
2315
2316 err = device_create_file(dev, &sda_caseopen[0].dev_attr);
2317 if (err)
2318 goto exit_remove;
2319
2320 if (sio_data->kind == nct6776) {
2321 err = device_create_file(dev, &sda_caseopen[1].dev_attr);
2322 if (err)
2323 goto exit_remove;
2324 }
2325
2326 err = device_create_file(dev, &dev_attr_name);
2327 if (err)
2328 goto exit_remove;
2329
2330 data->hwmon_dev = hwmon_device_register(dev);
2331 if (IS_ERR(data->hwmon_dev)) {
2332 err = PTR_ERR(data->hwmon_dev);
2333 goto exit_remove;
2334 }
2335
2336 return 0;
2337
2338 exit_remove:
2339 w83627ehf_device_remove_files(dev);
2340 kfree(data);
2341 platform_set_drvdata(pdev, NULL);
2342 exit_release:
2343 release_region(res->start, IOREGION_LENGTH);
2344 exit:
2345 return err;
2346 }
2347
2348 static int __devexit w83627ehf_remove(struct platform_device *pdev)
2349 {
2350 struct w83627ehf_data *data = platform_get_drvdata(pdev);
2351
2352 hwmon_device_unregister(data->hwmon_dev);
2353 w83627ehf_device_remove_files(&pdev->dev);
2354 release_region(data->addr, IOREGION_LENGTH);
2355 platform_set_drvdata(pdev, NULL);
2356 kfree(data);
2357
2358 return 0;
2359 }
2360
2361 static struct platform_driver w83627ehf_driver = {
2362 .driver = {
2363 .owner = THIS_MODULE,
2364 .name = DRVNAME,
2365 },
2366 .probe = w83627ehf_probe,
2367 .remove = __devexit_p(w83627ehf_remove),
2368 };
2369
2370 /* w83627ehf_find() looks for a '627 in the Super-I/O config space */
2371 static int __init w83627ehf_find(int sioaddr, unsigned short *addr,
2372 struct w83627ehf_sio_data *sio_data)
2373 {
2374 static const char __initdata sio_name_W83627EHF[] = "W83627EHF";
2375 static const char __initdata sio_name_W83627EHG[] = "W83627EHG";
2376 static const char __initdata sio_name_W83627DHG[] = "W83627DHG";
2377 static const char __initdata sio_name_W83627DHG_P[] = "W83627DHG-P";
2378 static const char __initdata sio_name_W83667HG[] = "W83667HG";
2379 static const char __initdata sio_name_W83667HG_B[] = "W83667HG-B";
2380 static const char __initdata sio_name_NCT6775[] = "NCT6775F";
2381 static const char __initdata sio_name_NCT6776[] = "NCT6776F";
2382
2383 u16 val;
2384 const char *sio_name;
2385
2386 superio_enter(sioaddr);
2387
2388 if (force_id)
2389 val = force_id;
2390 else
2391 val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8)
2392 | superio_inb(sioaddr, SIO_REG_DEVID + 1);
2393 switch (val & SIO_ID_MASK) {
2394 case SIO_W83627EHF_ID:
2395 sio_data->kind = w83627ehf;
2396 sio_name = sio_name_W83627EHF;
2397 break;
2398 case SIO_W83627EHG_ID:
2399 sio_data->kind = w83627ehf;
2400 sio_name = sio_name_W83627EHG;
2401 break;
2402 case SIO_W83627DHG_ID:
2403 sio_data->kind = w83627dhg;
2404 sio_name = sio_name_W83627DHG;
2405 break;
2406 case SIO_W83627DHG_P_ID:
2407 sio_data->kind = w83627dhg_p;
2408 sio_name = sio_name_W83627DHG_P;
2409 break;
2410 case SIO_W83667HG_ID:
2411 sio_data->kind = w83667hg;
2412 sio_name = sio_name_W83667HG;
2413 break;
2414 case SIO_W83667HG_B_ID:
2415 sio_data->kind = w83667hg_b;
2416 sio_name = sio_name_W83667HG_B;
2417 break;
2418 case SIO_NCT6775_ID:
2419 sio_data->kind = nct6775;
2420 sio_name = sio_name_NCT6775;
2421 break;
2422 case SIO_NCT6776_ID:
2423 sio_data->kind = nct6776;
2424 sio_name = sio_name_NCT6776;
2425 break;
2426 default:
2427 if (val != 0xffff)
2428 pr_debug("unsupported chip ID: 0x%04x\n", val);
2429 superio_exit(sioaddr);
2430 return -ENODEV;
2431 }
2432
2433 /* We have a known chip, find the HWM I/O address */
2434 superio_select(sioaddr, W83627EHF_LD_HWM);
2435 val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8)
2436 | superio_inb(sioaddr, SIO_REG_ADDR + 1);
2437 *addr = val & IOREGION_ALIGNMENT;
2438 if (*addr == 0) {
2439 pr_err("Refusing to enable a Super-I/O device with a base I/O port 0\n");
2440 superio_exit(sioaddr);
2441 return -ENODEV;
2442 }
2443
2444 /* Activate logical device if needed */
2445 val = superio_inb(sioaddr, SIO_REG_ENABLE);
2446 if (!(val & 0x01)) {
2447 pr_warn("Forcibly enabling Super-I/O. "
2448 "Sensor is probably unusable.\n");
2449 superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01);
2450 }
2451
2452 superio_exit(sioaddr);
2453 pr_info("Found %s chip at %#x\n", sio_name, *addr);
2454 sio_data->sioreg = sioaddr;
2455
2456 return 0;
2457 }
2458
2459 /* when Super-I/O functions move to a separate file, the Super-I/O
2460 * bus will manage the lifetime of the device and this module will only keep
2461 * track of the w83627ehf driver. But since we platform_device_alloc(), we
2462 * must keep track of the device */
2463 static struct platform_device *pdev;
2464
2465 static int __init sensors_w83627ehf_init(void)
2466 {
2467 int err;
2468 unsigned short address;
2469 struct resource res;
2470 struct w83627ehf_sio_data sio_data;
2471
2472 /* initialize sio_data->kind and sio_data->sioreg.
2473 *
2474 * when Super-I/O functions move to a separate file, the Super-I/O
2475 * driver will probe 0x2e and 0x4e and auto-detect the presence of a
2476 * w83627ehf hardware monitor, and call probe() */
2477 if (w83627ehf_find(0x2e, &address, &sio_data) &&
2478 w83627ehf_find(0x4e, &address, &sio_data))
2479 return -ENODEV;
2480
2481 err = platform_driver_register(&w83627ehf_driver);
2482 if (err)
2483 goto exit;
2484
2485 pdev = platform_device_alloc(DRVNAME, address);
2486 if (!pdev) {
2487 err = -ENOMEM;
2488 pr_err("Device allocation failed\n");
2489 goto exit_unregister;
2490 }
2491
2492 err = platform_device_add_data(pdev, &sio_data,
2493 sizeof(struct w83627ehf_sio_data));
2494 if (err) {
2495 pr_err("Platform data allocation failed\n");
2496 goto exit_device_put;
2497 }
2498
2499 memset(&res, 0, sizeof(res));
2500 res.name = DRVNAME;
2501 res.start = address + IOREGION_OFFSET;
2502 res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1;
2503 res.flags = IORESOURCE_IO;
2504
2505 err = acpi_check_resource_conflict(&res);
2506 if (err)
2507 goto exit_device_put;
2508
2509 err = platform_device_add_resources(pdev, &res, 1);
2510 if (err) {
2511 pr_err("Device resource addition failed (%d)\n", err);
2512 goto exit_device_put;
2513 }
2514
2515 /* platform_device_add calls probe() */
2516 err = platform_device_add(pdev);
2517 if (err) {
2518 pr_err("Device addition failed (%d)\n", err);
2519 goto exit_device_put;
2520 }
2521
2522 return 0;
2523
2524 exit_device_put:
2525 platform_device_put(pdev);
2526 exit_unregister:
2527 platform_driver_unregister(&w83627ehf_driver);
2528 exit:
2529 return err;
2530 }
2531
2532 static void __exit sensors_w83627ehf_exit(void)
2533 {
2534 platform_device_unregister(pdev);
2535 platform_driver_unregister(&w83627ehf_driver);
2536 }
2537
2538 MODULE_AUTHOR("Jean Delvare <khali@linux-fr.org>");
2539 MODULE_DESCRIPTION("W83627EHF driver");
2540 MODULE_LICENSE("GPL");
2541
2542 module_init(sensors_w83627ehf_init);
2543 module_exit(sensors_w83627ehf_exit);
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