drivers/idle/intel_idle.c

   1 /*
   2  * intel_idle.c - native hardware idle loop for modern Intel processors
   3  *
   4  * Copyright (c) 2010, Intel Corporation.
   5  * Len Brown <len.brown@intel.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19  */
  20
  21 /*
  22  * intel_idle is a cpuidle driver that loads on specific Intel processors
  23  * in lieu of the legacy ACPI processor_idle driver.  The intent is to
  24  * make Linux more efficient on these processors, as intel_idle knows
  25  * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
  26  */
  27
  28 /*
  29  * Design Assumptions
  30  *
  31  * All CPUs have same idle states as boot CPU
  32  *
  33  * Chipset BM_STS (bus master status) bit is a NOP
  34  *      for preventing entry into deep C-stats
  35  */
  36
  37 /*
  38  * Known limitations
  39  *
  40  * The driver currently initializes for_each_online_cpu() upon modprobe.
  41  * It it unaware of subsequent processors hot-added to the system.
  42  * This means that if you boot with maxcpus=n and later online
  43  * processors above n, those processors will use C1 only.
  44  *
  45  * ACPI has a .suspend hack to turn off deep c-statees during suspend
  46  * to avoid complications with the lapic timer workaround.
  47  * Have not seen issues with suspend, but may need same workaround here.
  48  *
  49  * There is currently no kernel-based automatic probing/loading mechanism
  50  * if the driver is built as a module.
  51  */
  52
  53 /* un-comment DEBUG to enable pr_debug() statements */
  54 #define DEBUG
  55
  56 #include <linux/kernel.h>
  57 #include <linux/cpuidle.h>
  58 #include <linux/clockchips.h>
  59 #include <linux/hrtimer.h>      /* ktime_get_real() */
  60 #include <trace/events/power.h>
  61 #include <linux/sched.h>
  62 #include <linux/notifier.h>
  63 #include <linux/cpu.h>
  64 #include <linux/module.h>
  65 #include <asm/mwait.h>
  66 #include <asm/msr.h>
  67
  68 #define INTEL_IDLE_VERSION "0.4"
  69 #define PREFIX "intel_idle: "
  70
  71 static struct cpuidle_driver intel_idle_driver = {
  72         .name = "intel_idle",
  73         .owner = THIS_MODULE,
  74 };
  75 /* intel_idle.max_cstate=0 disables driver */
  76 static int max_cstate = MWAIT_MAX_NUM_CSTATES - 1;
  77
  78 static unsigned int mwait_substates;
  79
  80 #define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF
  81 /* Reliable LAPIC Timer States, bit 1 for C1 etc.  */
  82 static unsigned int lapic_timer_reliable_states = (1 << 1);      /* Default to only C1 */
  83
  84 static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
  85 static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state);
  86
  87 static struct cpuidle_state *cpuidle_state_table;
  88
  89 /*
  90  * Hardware C-state auto-demotion may not always be optimal.
  91  * Indicate which enable bits to clear here.
  92  */
  93 static unsigned long long auto_demotion_disable_flags;
  94
  95 /*
  96  * Set this flag for states where the HW flushes the TLB for us
  97  * and so we don't need cross-calls to keep it consistent.
  98  * If this flag is set, SW flushes the TLB, so even if the
  99  * HW doesn't do the flushing, this flag is safe to use.
 100  */
 101 #define CPUIDLE_FLAG_TLB_FLUSHED        0x10000
 102
 103 /*
 104  * States are indexed by the cstate number,
 105  * which is also the index into the MWAIT hint array.
 106  * Thus C0 is a dummy.
 107  */
 108 static struct cpuidle_state nehalem_cstates[MWAIT_MAX_NUM_CSTATES] = {
 109         { /* MWAIT C0 */ },
 110         { /* MWAIT C1 */
 111                 .name = "C1-NHM",
 112                 .desc = "MWAIT 0x00",
 113                 .driver_data = (void *) 0x00,
 114                 .flags = CPUIDLE_FLAG_TIME_VALID,
 115                 .exit_latency = 3,
 116                 .target_residency = 6,
 117                 .enter = &intel_idle },
 118         { /* MWAIT C2 */
 119                 .name = "C3-NHM",
 120                 .desc = "MWAIT 0x10",
 121                 .driver_data = (void *) 0x10,
 122                 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 123                 .exit_latency = 20,
 124                 .target_residency = 80,
 125                 .enter = &intel_idle },
 126         { /* MWAIT C3 */
 127                 .name = "C6-NHM",
 128                 .desc = "MWAIT 0x20",
 129                 .driver_data = (void *) 0x20,
 130                 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 131                 .exit_latency = 200,
 132                 .target_residency = 800,
 133                 .enter = &intel_idle },
 134 };
 135
 136 static struct cpuidle_state snb_cstates[MWAIT_MAX_NUM_CSTATES] = {
 137         { /* MWAIT C0 */ },
 138         { /* MWAIT C1 */
 139                 .name = "C1-SNB",
 140                 .desc = "MWAIT 0x00",
 141                 .driver_data = (void *) 0x00,
 142                 .flags = CPUIDLE_FLAG_TIME_VALID,
 143                 .exit_latency = 1,
 144                 .target_residency = 1,
 145                 .enter = &intel_idle },
 146         { /* MWAIT C2 */
 147                 .name = "C3-SNB",
 148                 .desc = "MWAIT 0x10",
 149                 .driver_data = (void *) 0x10,
 150                 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 151                 .exit_latency = 80,
 152                 .target_residency = 211,
 153                 .enter = &intel_idle },
 154         { /* MWAIT C3 */
 155                 .name = "C6-SNB",
 156                 .desc = "MWAIT 0x20",
 157                 .driver_data = (void *) 0x20,
 158                 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 159                 .exit_latency = 104,
 160                 .target_residency = 345,
 161                 .enter = &intel_idle },
 162         { /* MWAIT C4 */
 163                 .name = "C7-SNB",
 164                 .desc = "MWAIT 0x30",
 165                 .driver_data = (void *) 0x30,
 166                 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 167                 .exit_latency = 109,
 168                 .target_residency = 345,
 169                 .enter = &intel_idle },
 170 };
 171
 172 static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
 173         { /* MWAIT C0 */ },
 174         { /* MWAIT C1 */
 175                 .name = "C1-ATM",
 176                 .desc = "MWAIT 0x00",
 177                 .driver_data = (void *) 0x00,
 178                 .flags = CPUIDLE_FLAG_TIME_VALID,
 179                 .exit_latency = 1,
 180                 .target_residency = 4,
 181                 .enter = &intel_idle },
 182         { /* MWAIT C2 */
 183                 .name = "C2-ATM",
 184                 .desc = "MWAIT 0x10",
 185                 .driver_data = (void *) 0x10,
 186                 .flags = CPUIDLE_FLAG_TIME_VALID,
 187                 .exit_latency = 20,
 188                 .target_residency = 80,
 189                 .enter = &intel_idle },
 190         { /* MWAIT C3 */ },
 191         { /* MWAIT C4 */
 192                 .name = "C4-ATM",
 193                 .desc = "MWAIT 0x30",
 194                 .driver_data = (void *) 0x30,
 195                 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 196                 .exit_latency = 100,
 197                 .target_residency = 400,
 198                 .enter = &intel_idle },
 199         { /* MWAIT C5 */ },
 200         { /* MWAIT C6 */
 201                 .name = "C6-ATM",
 202                 .desc = "MWAIT 0x52",
 203                 .driver_data = (void *) 0x52,
 204                 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 205                 .exit_latency = 140,
 206                 .target_residency = 560,
 207                 .enter = &intel_idle },
 208 };
 209
 210 /**
 211  * intel_idle
 212  * @dev: cpuidle_device
 213  * @state: cpuidle state
 214  *
 215  */
 216 static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state)
 217 {
 218         unsigned long ecx = 1; /* break on interrupt flag */
 219         unsigned long eax = (unsigned long)cpuidle_get_statedata(state);
 220         unsigned int cstate;
 221         ktime_t kt_before, kt_after;
 222         s64 usec_delta;
 223         int cpu = smp_processor_id();
 224
 225         cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;
 226
 227         local_irq_disable();
 228
 229         /*
 230          * leave_mm() to avoid costly and often unnecessary wakeups
 231          * for flushing the user TLB's associated with the active mm.
 232          */
 233         if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
 234                 leave_mm(cpu);
 235
 236         if (!(lapic_timer_reliable_states & (1 << (cstate))))
 237                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
 238
 239         kt_before = ktime_get_real();
 240
 241         stop_critical_timings();
 242         if (!need_resched()) {
 243
 244                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 245                 smp_mb();
 246                 if (!need_resched())
 247                         __mwait(eax, ecx);
 248         }
 249
 250         start_critical_timings();
 251
 252         kt_after = ktime_get_real();
 253         usec_delta = ktime_to_us(ktime_sub(kt_after, kt_before));
 254
 255         local_irq_enable();
 256
 257         if (!(lapic_timer_reliable_states & (1 << (cstate))))
 258                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
 259
 260         return usec_delta;
 261 }
 262
 263 static void __setup_broadcast_timer(void *arg)
 264 {
 265         unsigned long reason = (unsigned long)arg;
 266         int cpu = smp_processor_id();
 267
 268         reason = reason ?
 269                 CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF;
 270
 271         clockevents_notify(reason, &cpu);
 272 }
 273
 274 static void auto_demotion_disable(void *dummy)
 275 {
 276         unsigned long long msr_bits;
 277
 278         rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
 279         msr_bits &= ~auto_demotion_disable_flags;
 280         wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
 281 }
 282
 283 static void __intel_idle_notify_handler(void *arg)
 284 {
 285         if (auto_demotion_disable_flags)
 286                 auto_demotion_disable(NULL);
 287
 288         if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
 289                 __setup_broadcast_timer((void *)true);
 290 }
 291
 292 static int setup_intelidle_cpuhp_notify(struct notifier_block *n,
 293                 unsigned long action, void *hcpu)
 294 {
 295         int hotcpu = (unsigned long)hcpu;
 296
 297         switch (action & 0xf) {
 298         case CPU_ONLINE:
 299                 smp_call_function_single(hotcpu, __intel_idle_notify_handler,
 300                         NULL, 1);
 301                 break;
 302         }
 303         return NOTIFY_OK;
 304 }
 305
 306 static struct notifier_block setup_intelidle_notifier = {
 307         .notifier_call = setup_intelidle_cpuhp_notify,
 308 };
 309
 310 /*
 311  * intel_idle_probe()
 312  */
 313 static int intel_idle_probe(void)
 314 {
 315         unsigned int eax, ebx, ecx;
 316
 317         if (max_cstate == 0) {
 318                 pr_debug(PREFIX "disabled\n");
 319                 return -EPERM;
 320         }
 321
 322         if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
 323                 return -ENODEV;
 324
 325         if (!boot_cpu_has(X86_FEATURE_MWAIT))
 326                 return -ENODEV;
 327
 328         if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
 329                 return -ENODEV;
 330
 331         cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
 332
 333         if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
 334                 !(ecx & CPUID5_ECX_INTERRUPT_BREAK))
 335                         return -ENODEV;
 336
 337         pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates);
 338
 339
 340         if (boot_cpu_data.x86 != 6)     /* family 6 */
 341                 return -ENODEV;
 342
 343         switch (boot_cpu_data.x86_model) {
 344
 345         case 0x1A:      /* Core i7, Xeon 5500 series */
 346         case 0x1E:      /* Core i7 and i5 Processor - Lynnfield Jasper Forest */
 347         case 0x1F:      /* Core i7 and i5 Processor - Nehalem */
 348         case 0x2E:      /* Nehalem-EX Xeon */
 349         case 0x2F:      /* Westmere-EX Xeon */
 350         case 0x25:      /* Westmere */
 351         case 0x2C:      /* Westmere */
 352                 cpuidle_state_table = nehalem_cstates;
 353                 auto_demotion_disable_flags =
 354                         (NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE);
 355                 break;
 356
 357         case 0x1C:      /* 28 - Atom Processor */
 358                 cpuidle_state_table = atom_cstates;
 359                 break;
 360
 361         case 0x26:      /* 38 - Lincroft Atom Processor */
 362                 cpuidle_state_table = atom_cstates;
 363                 auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE;
 364                 break;
 365
 366         case 0x2A:      /* SNB */
 367         case 0x2D:      /* SNB Xeon */
 368                 cpuidle_state_table = snb_cstates;
 369                 break;
 370
 371         default:
 372                 pr_debug(PREFIX "does not run on family %d model %d\n",
 373                         boot_cpu_data.x86, boot_cpu_data.x86_model);
 374                 return -ENODEV;
 375         }
 376
 377         if (boot_cpu_has(X86_FEATURE_ARAT))     /* Always Reliable APIC Timer */
 378                 lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
 379         else
 380                 on_each_cpu(__setup_broadcast_timer, (void *)true, 1);
 381
 382         pr_debug(PREFIX "v" INTEL_IDLE_VERSION
 383                 " model 0x%X\n", boot_cpu_data.x86_model);
 384
 385         pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n",
 386                 lapic_timer_reliable_states);
 387         return 0;
 388 }
 389
 390 /*
 391  * intel_idle_cpuidle_devices_uninit()
 392  * unregister, free cpuidle_devices
 393  */
 394 static void intel_idle_cpuidle_devices_uninit(void)
 395 {
 396         int i;
 397         struct cpuidle_device *dev;
 398
 399         for_each_online_cpu(i) {
 400                 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
 401                 cpuidle_unregister_device(dev);
 402         }
 403
 404         free_percpu(intel_idle_cpuidle_devices);
 405         return;
 406 }
 407 /*
 408  * intel_idle_cpuidle_devices_init()
 409  * allocate, initialize, register cpuidle_devices
 410  */
 411 static int intel_idle_cpuidle_devices_init(void)
 412 {
 413         int i, cstate;
 414         struct cpuidle_device *dev;
 415
 416         intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
 417         if (intel_idle_cpuidle_devices == NULL)
 418                 return -ENOMEM;
 419
 420         for_each_online_cpu(i) {
 421                 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
 422
 423                 dev->state_count = 1;
 424
 425                 for (cstate = 1; cstate < MWAIT_MAX_NUM_CSTATES; ++cstate) {
 426                         int num_substates;
 427
 428                         if (cstate > max_cstate) {
 429                                 printk(PREFIX "max_cstate %d reached\n",
 430                                         max_cstate);
 431                                 break;
 432                         }
 433
 434                         /* does the state exist in CPUID.MWAIT? */
 435                         num_substates = (mwait_substates >> ((cstate) * 4))
 436                                                 & MWAIT_SUBSTATE_MASK;
 437                         if (num_substates == 0)
 438                                 continue;
 439                         /* is the state not enabled? */
 440                         if (cpuidle_state_table[cstate].enter == NULL) {
 441                                 /* does the driver not know about the state? */
 442                                 if (*cpuidle_state_table[cstate].name == '\0')
 443                                         pr_debug(PREFIX "unaware of model 0x%x"
 444                                                 " MWAIT %d please"
 445                                                 " contact lenb@kernel.org",
 446                                         boot_cpu_data.x86_model, cstate);
 447                                 continue;
 448                         }
 449
 450                         if ((cstate > 2) &&
 451                                 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
 452                                 mark_tsc_unstable("TSC halts in idle"
 453                                         " states deeper than C2");
 454
 455                         dev->states[dev->state_count] = /* structure copy */
 456                                 cpuidle_state_table[cstate];
 457
 458                         dev->state_count += 1;
 459                 }
 460
 461                 dev->cpu = i;
 462                 if (cpuidle_register_device(dev)) {
 463                         pr_debug(PREFIX "cpuidle_register_device %d failed!\n",
 464                                  i);
 465                         intel_idle_cpuidle_devices_uninit();
 466                         return -EIO;
 467                 }
 468         }
 469         if (auto_demotion_disable_flags)
 470                 on_each_cpu(auto_demotion_disable, NULL, 1);
 471
 472         return 0;
 473 }
 474
 475
 476 static int __init intel_idle_init(void)
 477 {
 478         int retval;
 479
 480         /* Do not load intel_idle at all for now if idle= is passed */
 481         if (boot_option_idle_override != IDLE_NO_OVERRIDE)
 482                 return -ENODEV;
 483
 484         retval = intel_idle_probe();
 485         if (retval)
 486                 return retval;
 487
 488         retval = cpuidle_register_driver(&intel_idle_driver);
 489         if (retval) {
 490                 printk(KERN_DEBUG PREFIX "intel_idle yielding to %s",
 491                         cpuidle_get_driver()->name);
 492                 return retval;
 493         }
 494
 495         retval = intel_idle_cpuidle_devices_init();
 496         if (retval) {
 497                 cpuidle_unregister_driver(&intel_idle_driver);
 498                 return retval;
 499         }
 500
 501         if (auto_demotion_disable_flags || lapic_timer_reliable_states !=
 502             LAPIC_TIMER_ALWAYS_RELIABLE)
 503                 register_cpu_notifier(&setup_intelidle_notifier);
 504
 505         return 0;
 506 }
 507
 508 static void __exit intel_idle_exit(void)
 509 {
 510         intel_idle_cpuidle_devices_uninit();
 511         cpuidle_unregister_driver(&intel_idle_driver);
 512
 513         if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
 514                 on_each_cpu(__setup_broadcast_timer, (void *)false, 1);
 515
 516         if (auto_demotion_disable_flags || lapic_timer_reliable_states !=
 517             LAPIC_TIMER_ALWAYS_RELIABLE)
 518                 unregister_cpu_notifier(&setup_intelidle_notifier);
 519
 520         return;
 521 }
 522
 523 module_init(intel_idle_init);
 524 module_exit(intel_idle_exit);
 525
 526 module_param(max_cstate, int, 0444);
 527
 528 MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
 529 MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION);
 530 MODULE_LICENSE("GPL");