Add linux-next specific files for 20110831
[linux-2.6/next.git] / drivers / media / rc / ene_ir.h
blob017c209cdf8a2ac51ae7365908102e8dc4e8a10d
1 /*
2 * driver for ENE KB3926 B/C/D/E/F CIR (also known as ENE0XXX)
4 * Copyright (C) 2010 Maxim Levitsky <maximlevitsky@gmail.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of the
9 * License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
19 * USA
21 #include <linux/spinlock.h>
24 /* hardware address */
25 #define ENE_STATUS 0 /* hardware status - unused */
26 #define ENE_ADDR_HI 1 /* hi byte of register address */
27 #define ENE_ADDR_LO 2 /* low byte of register address */
28 #define ENE_IO 3 /* read/write window */
29 #define ENE_IO_SIZE 4
31 /* 8 bytes of samples, divided in 2 packets*/
32 #define ENE_FW_SAMPLE_BUFFER 0xF8F0 /* sample buffer */
33 #define ENE_FW_SAMPLE_SPACE 0x80 /* sample is space */
34 #define ENE_FW_PACKET_SIZE 4
36 /* first firmware flag register */
37 #define ENE_FW1 0xF8F8 /* flagr */
38 #define ENE_FW1_ENABLE 0x01 /* enable fw processing */
39 #define ENE_FW1_TXIRQ 0x02 /* TX interrupt pending */
40 #define ENE_FW1_HAS_EXTRA_BUF 0x04 /* fw uses extra buffer*/
41 #define ENE_FW1_EXTRA_BUF_HND 0x08 /* extra buffer handshake bit*/
42 #define ENE_FW1_LED_ON 0x10 /* turn on a led */
44 #define ENE_FW1_WPATTERN 0x20 /* enable wake pattern */
45 #define ENE_FW1_WAKE 0x40 /* enable wake from S3 */
46 #define ENE_FW1_IRQ 0x80 /* enable interrupt */
48 /* second firmware flag register */
49 #define ENE_FW2 0xF8F9 /* flagw */
50 #define ENE_FW2_BUF_WPTR 0x01 /* which half of the buffer to read */
51 #define ENE_FW2_RXIRQ 0x04 /* RX IRQ pending*/
52 #define ENE_FW2_GP0A 0x08 /* Use GPIO0A for demodulated input */
53 #define ENE_FW2_EMMITER1_CONN 0x10 /* TX emmiter 1 connected */
54 #define ENE_FW2_EMMITER2_CONN 0x20 /* TX emmiter 2 connected */
56 #define ENE_FW2_FAN_INPUT 0x40 /* fan input used for demodulated data*/
57 #define ENE_FW2_LEARNING 0x80 /* hardware supports learning and TX */
59 /* firmware RX pointer for new style buffer */
60 #define ENE_FW_RX_POINTER 0xF8FA
62 /* high parts of samples for fan input (8 samples)*/
63 #define ENE_FW_SMPL_BUF_FAN 0xF8FB
64 #define ENE_FW_SMPL_BUF_FAN_PLS 0x8000 /* combined sample is pulse */
65 #define ENE_FW_SMPL_BUF_FAN_MSK 0x0FFF /* combined sample maximum value */
66 #define ENE_FW_SAMPLE_PERIOD_FAN 61 /* fan input has fixed sample period */
68 /* transmitter ports */
69 #define ENE_GPIOFS1 0xFC01
70 #define ENE_GPIOFS1_GPIO0D 0x20 /* enable tx output on GPIO0D */
71 #define ENE_GPIOFS8 0xFC08
72 #define ENE_GPIOFS8_GPIO41 0x02 /* enable tx output on GPIO40 */
74 /* IRQ registers block (for revision B) */
75 #define ENEB_IRQ 0xFD09 /* IRQ number */
76 #define ENEB_IRQ_UNK1 0xFD17 /* unknown setting = 1 */
77 #define ENEB_IRQ_STATUS 0xFD80 /* irq status */
78 #define ENEB_IRQ_STATUS_IR 0x20 /* IR irq */
80 /* fan as input settings */
81 #define ENE_FAN_AS_IN1 0xFE30 /* fan init reg 1 */
82 #define ENE_FAN_AS_IN1_EN 0xCD
83 #define ENE_FAN_AS_IN2 0xFE31 /* fan init reg 2 */
84 #define ENE_FAN_AS_IN2_EN 0x03
86 /* IRQ registers block (for revision C,D) */
87 #define ENE_IRQ 0xFE9B /* new irq settings register */
88 #define ENE_IRQ_MASK 0x0F /* irq number mask */
89 #define ENE_IRQ_UNK_EN 0x10 /* always enabled */
90 #define ENE_IRQ_STATUS 0x20 /* irq status and ACK */
92 /* CIR Config register #1 */
93 #define ENE_CIRCFG 0xFEC0
94 #define ENE_CIRCFG_RX_EN 0x01 /* RX enable */
95 #define ENE_CIRCFG_RX_IRQ 0x02 /* Enable hardware interrupt */
96 #define ENE_CIRCFG_REV_POL 0x04 /* Input polarity reversed */
97 #define ENE_CIRCFG_CARR_DEMOD 0x08 /* Enable carrier demodulator */
99 #define ENE_CIRCFG_TX_EN 0x10 /* TX enable */
100 #define ENE_CIRCFG_TX_IRQ 0x20 /* Send interrupt on TX done */
101 #define ENE_CIRCFG_TX_POL_REV 0x40 /* TX polarity reversed */
102 #define ENE_CIRCFG_TX_CARR 0x80 /* send TX carrier or not */
104 /* CIR config register #2 */
105 #define ENE_CIRCFG2 0xFEC1
106 #define ENE_CIRCFG2_RLC 0x00
107 #define ENE_CIRCFG2_RC5 0x01
108 #define ENE_CIRCFG2_RC6 0x02
109 #define ENE_CIRCFG2_NEC 0x03
110 #define ENE_CIRCFG2_CARR_DETECT 0x10 /* Enable carrier detection */
111 #define ENE_CIRCFG2_GPIO0A 0x20 /* Use GPIO0A instead of GPIO40 for input */
112 #define ENE_CIRCFG2_FAST_SAMPL1 0x40 /* Fast leading pulse detection for RC6 */
113 #define ENE_CIRCFG2_FAST_SAMPL2 0x80 /* Fast data detection for RC6 */
115 /* Knobs for protocol decoding - will document when/if will use them */
116 #define ENE_CIRPF 0xFEC2
117 #define ENE_CIRHIGH 0xFEC3
118 #define ENE_CIRBIT 0xFEC4
119 #define ENE_CIRSTART 0xFEC5
120 #define ENE_CIRSTART2 0xFEC6
122 /* Actual register which contains RLC RX data - read by firmware */
123 #define ENE_CIRDAT_IN 0xFEC7
126 /* RLC configuration - sample period (1us resulution) + idle mode */
127 #define ENE_CIRRLC_CFG 0xFEC8
128 #define ENE_CIRRLC_CFG_OVERFLOW 0x80 /* interrupt on overflows if set */
129 #define ENE_DEFAULT_SAMPLE_PERIOD 50
131 /* Two byte RLC TX buffer */
132 #define ENE_CIRRLC_OUT0 0xFEC9
133 #define ENE_CIRRLC_OUT1 0xFECA
134 #define ENE_CIRRLC_OUT_PULSE 0x80 /* Transmitted sample is pulse */
135 #define ENE_CIRRLC_OUT_MASK 0x7F
138 /* Carrier detect setting
139 * Low nibble - number of carrier pulses to average
140 * High nibble - number of initial carrier pulses to discard
142 #define ENE_CIRCAR_PULS 0xFECB
144 /* detected RX carrier period (resolution: 500 ns) */
145 #define ENE_CIRCAR_PRD 0xFECC
146 #define ENE_CIRCAR_PRD_VALID 0x80 /* data valid content valid */
148 /* detected RX carrier pulse width (resolution: 500 ns) */
149 #define ENE_CIRCAR_HPRD 0xFECD
151 /* TX period (resolution: 500 ns, minimum 2)*/
152 #define ENE_CIRMOD_PRD 0xFECE
153 #define ENE_CIRMOD_PRD_POL 0x80 /* TX carrier polarity*/
155 #define ENE_CIRMOD_PRD_MAX 0x7F /* 15.87 kHz */
156 #define ENE_CIRMOD_PRD_MIN 0x02 /* 1 Mhz */
158 /* TX pulse width (resolution: 500 ns)*/
159 #define ENE_CIRMOD_HPRD 0xFECF
161 /* Hardware versions */
162 #define ENE_ECHV 0xFF00 /* hardware revision */
163 #define ENE_PLLFRH 0xFF16
164 #define ENE_PLLFRL 0xFF17
165 #define ENE_DEFAULT_PLL_FREQ 1000
167 #define ENE_ECSTS 0xFF1D
168 #define ENE_ECSTS_RSRVD 0x04
170 #define ENE_ECVER_MAJOR 0xFF1E /* chip version */
171 #define ENE_ECVER_MINOR 0xFF1F
172 #define ENE_HW_VER_OLD 0xFD00
174 /******************************************************************************/
176 #define ENE_DRIVER_NAME "ene_ir"
178 #define ENE_IRQ_RX 1
179 #define ENE_IRQ_TX 2
181 #define ENE_HW_B 1 /* 3926B */
182 #define ENE_HW_C 2 /* 3926C */
183 #define ENE_HW_D 3 /* 3926D or later */
185 #define ene_printk(level, text, ...) \
186 printk(level ENE_DRIVER_NAME ": " text "\n", ## __VA_ARGS__)
188 #define ene_notice(text, ...) ene_printk(KERN_NOTICE, text, ## __VA_ARGS__)
189 #define ene_warn(text, ...) ene_printk(KERN_WARNING, text, ## __VA_ARGS__)
192 #define __dbg(level, format, ...) \
193 do { \
194 if (debug >= level) \
195 printk(KERN_DEBUG ENE_DRIVER_NAME \
196 ": " format "\n", ## __VA_ARGS__); \
197 } while (0)
200 #define dbg(format, ...) __dbg(1, format, ## __VA_ARGS__)
201 #define dbg_verbose(format, ...) __dbg(2, format, ## __VA_ARGS__)
202 #define dbg_regs(format, ...) __dbg(3, format, ## __VA_ARGS__)
204 struct ene_device {
205 struct pnp_dev *pnp_dev;
206 struct rc_dev *rdev;
208 /* hw IO settings */
209 long hw_io;
210 int irq;
211 spinlock_t hw_lock;
213 /* HW features */
214 int hw_revision; /* hardware revision */
215 bool hw_use_gpio_0a; /* gpio0a is demodulated input*/
216 bool hw_extra_buffer; /* hardware has 'extra buffer' */
217 bool hw_fan_input; /* fan input is IR data source */
218 bool hw_learning_and_tx_capable; /* learning & tx capable */
219 int pll_freq;
220 int buffer_len;
222 /* Extra RX buffer location */
223 int extra_buf1_address;
224 int extra_buf1_len;
225 int extra_buf2_address;
226 int extra_buf2_len;
228 /* HW state*/
229 int r_pointer; /* pointer to next sample to read */
230 int w_pointer; /* pointer to next sample hw will write */
231 bool rx_fan_input_inuse; /* is fan input in use for rx*/
232 int tx_reg; /* current reg used for TX */
233 u8 saved_conf1; /* saved FEC0 reg */
234 unsigned int tx_sample; /* current sample for TX */
235 bool tx_sample_pulse; /* current sample is pulse */
237 /* TX buffer */
238 unsigned *tx_buffer; /* input samples buffer*/
239 int tx_pos; /* position in that bufer */
240 int tx_len; /* current len of tx buffer */
241 int tx_done; /* done transmitting */
242 /* one more sample pending*/
243 struct completion tx_complete; /* TX completion */
244 struct timer_list tx_sim_timer;
246 /* TX settings */
247 int tx_period;
248 int tx_duty_cycle;
249 int transmitter_mask;
251 /* RX settings */
252 bool learning_mode_enabled; /* learning input enabled */
253 bool carrier_detect_enabled; /* carrier detect enabled */
254 int rx_period_adjust;
255 bool rx_enabled;
258 static int ene_irq_status(struct ene_device *dev);
259 static void ene_rx_read_hw_pointer(struct ene_device *dev);