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Add linux-next specific files for 20110831
[linux-2.6/next.git] / drivers / media / video / cx231xx / cx231xx-avcore.c
blob53ff26e7abf77036136b60f2a5520e41623fbd14
1 /*
2 cx231xx_avcore.c - driver for Conexant Cx23100/101/102
3 USB video capture devices
4
5 Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
6
7 This program contains the specific code to control the avdecoder chip and
8 other related usb control functions for cx231xx based chipset.
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #include <linux/init.h>
26 #include <linux/list.h>
27 #include <linux/module.h>
28 #include <linux/kernel.h>
29 #include <linux/bitmap.h>
30 #include <linux/usb.h>
31 #include <linux/i2c.h>
32 #include <linux/mm.h>
33 #include <linux/mutex.h>
34 #include <media/tuner.h>
35
36 #include <media/v4l2-common.h>
37 #include <media/v4l2-ioctl.h>
38 #include <media/v4l2-chip-ident.h>
39
40 #include "cx231xx.h"
41 #include "cx231xx-dif.h"
42
43 #define TUNER_MODE_FM_RADIO 0
44 /******************************************************************************
45 -: BLOCK ARRANGEMENT :-
46 I2S block ----------------------|
47 [I2S audio] |
48 |
49 Analog Front End --> Direct IF -|-> Cx25840 --> Audio
50 [video & audio] | [Audio]
51 |
52 |-> Cx25840 --> Video
53 [Video]
54
55 *******************************************************************************/
56 /******************************************************************************
57 * VERVE REGISTER *
58 * *
59 ******************************************************************************/
60 static int verve_write_byte(struct cx231xx *dev, u8 saddr, u8 data)
61 {
62 return cx231xx_write_i2c_data(dev, VERVE_I2C_ADDRESS,
63 saddr, 1, data, 1);
64 }
65
66 static int verve_read_byte(struct cx231xx *dev, u8 saddr, u8 *data)
67 {
68 int status;
69 u32 temp = 0;
70
71 status = cx231xx_read_i2c_data(dev, VERVE_I2C_ADDRESS,
72 saddr, 1, &temp, 1);
73 *data = (u8) temp;
74 return status;
75 }
76 void initGPIO(struct cx231xx *dev)
77 {
78 u32 _gpio_direction = 0;
79 u32 value = 0;
80 u8 val = 0;
81
82 _gpio_direction = _gpio_direction & 0xFC0003FF;
83 _gpio_direction = _gpio_direction | 0x03FDFC00;
84 cx231xx_send_gpio_cmd(dev, _gpio_direction, (u8 *)&value, 4, 0, 0);
85
86 verve_read_byte(dev, 0x07, &val);
87 cx231xx_info(" verve_read_byte address0x07=0x%x\n", val);
88 verve_write_byte(dev, 0x07, 0xF4);
89 verve_read_byte(dev, 0x07, &val);
90 cx231xx_info(" verve_read_byte address0x07=0x%x\n", val);
91
92 cx231xx_capture_start(dev, 1, 2);
93
94 cx231xx_mode_register(dev, EP_MODE_SET, 0x0500FE00);
95 cx231xx_mode_register(dev, GBULK_BIT_EN, 0xFFFDFFFF);
96
97 }
98 void uninitGPIO(struct cx231xx *dev)
99 {
100 u8 value[4] = { 0, 0, 0, 0 };
101
102 cx231xx_capture_start(dev, 0, 2);
103 verve_write_byte(dev, 0x07, 0x14);
104 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
105 0x68, value, 4);
106 }
107
108 /******************************************************************************
109 * A F E - B L O C K C O N T R O L functions *
110 * [ANALOG FRONT END] *
111 ******************************************************************************/
112 static int afe_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
113 {
114 return cx231xx_write_i2c_data(dev, AFE_DEVICE_ADDRESS,
115 saddr, 2, data, 1);
116 }
117
118 static int afe_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
119 {
120 int status;
121 u32 temp = 0;
122
123 status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS,
124 saddr, 2, &temp, 1);
125 *data = (u8) temp;
126 return status;
127 }
128
129 int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count)
130 {
131 int status = 0;
132 u8 temp = 0;
133 u8 afe_power_status = 0;
134 int i = 0;
135
136 /* super block initialize */
137 temp = (u8) (ref_count & 0xff);
138 status = afe_write_byte(dev, SUP_BLK_TUNE2, temp);
139 if (status < 0)
140 return status;
141
142 status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status);
143 if (status < 0)
144 return status;
145
146 temp = (u8) ((ref_count & 0x300) >> 8);
147 temp |= 0x40;
148 status = afe_write_byte(dev, SUP_BLK_TUNE1, temp);
149 if (status < 0)
150 return status;
151
152 status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f);
153 if (status < 0)
154 return status;
155
156 /* enable pll */
157 while (afe_power_status != 0x18) {
158 status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18);
159 if (status < 0) {
160 cx231xx_info(
161 ": Init Super Block failed in send cmd\n");
162 break;
163 }
164
165 status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status);
166 afe_power_status &= 0xff;
167 if (status < 0) {
168 cx231xx_info(
169 ": Init Super Block failed in receive cmd\n");
170 break;
171 }
172 i++;
173 if (i == 10) {
174 cx231xx_info(
175 ": Init Super Block force break in loop !!!!\n");
176 status = -1;
177 break;
178 }
179 }
180
181 if (status < 0)
182 return status;
183
184 /* start tuning filter */
185 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40);
186 if (status < 0)
187 return status;
188
189 msleep(5);
190
191 /* exit tuning */
192 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00);
193
194 return status;
195 }
196
197 int cx231xx_afe_init_channels(struct cx231xx *dev)
198 {
199 int status = 0;
200
201 /* power up all 3 channels, clear pd_buffer */
202 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00);
203 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00);
204 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00);
205
206 /* Enable quantizer calibration */
207 status = afe_write_byte(dev, ADC_COM_QUANT, 0x02);
208
209 /* channel initialize, force modulator (fb) reset */
210 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17);
211 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17);
212 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17);
213
214 /* start quantilizer calibration */
215 status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10);
216 status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10);
217 status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10);
218 msleep(5);
219
220 /* exit modulator (fb) reset */
221 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07);
222 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07);
223 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07);
224
225 /* enable the pre_clamp in each channel for single-ended input */
226 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0);
227 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0);
228 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0);
229
230 /* use diode instead of resistor, so set term_en to 0, res_en to 0 */
231 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
232 ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00);
233 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
234 ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00);
235 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
236 ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00);
237
238 /* dynamic element matching off */
239 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03);
240 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03);
241 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03);
242
243 return status;
244 }
245
246 int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev)
247 {
248 u8 c_value = 0;
249 int status = 0;
250
251 status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value);
252 c_value &= (~(0x50));
253 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value);
254
255 return status;
256 }
257
258 /*
259 The Analog Front End in Cx231xx has 3 channels. These
260 channels are used to share between different inputs
261 like tuner, s-video and composite inputs.
262
263 channel 1 ----- pin 1 to pin4(in reg is 1-4)
264 channel 2 ----- pin 5 to pin8(in reg is 5-8)
265 channel 3 ----- pin 9 to pin 12(in reg is 9-11)
266 */
267 int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux)
268 {
269 u8 ch1_setting = (u8) input_mux;
270 u8 ch2_setting = (u8) (input_mux >> 8);
271 u8 ch3_setting = (u8) (input_mux >> 16);
272 int status = 0;
273 u8 value = 0;
274
275 if (ch1_setting != 0) {
276 status = afe_read_byte(dev, ADC_INPUT_CH1, &value);
277 value &= ~INPUT_SEL_MASK;
278 value |= (ch1_setting - 1) << 4;
279 value &= 0xff;
280 status = afe_write_byte(dev, ADC_INPUT_CH1, value);
281 }
282
283 if (ch2_setting != 0) {
284 status = afe_read_byte(dev, ADC_INPUT_CH2, &value);
285 value &= ~INPUT_SEL_MASK;
286 value |= (ch2_setting - 1) << 4;
287 value &= 0xff;
288 status = afe_write_byte(dev, ADC_INPUT_CH2, value);
289 }
290
291 /* For ch3_setting, the value to put in the register is
292 7 less than the input number */
293 if (ch3_setting != 0) {
294 status = afe_read_byte(dev, ADC_INPUT_CH3, &value);
295 value &= ~INPUT_SEL_MASK;
296 value |= (ch3_setting - 1) << 4;
297 value &= 0xff;
298 status = afe_write_byte(dev, ADC_INPUT_CH3, value);
299 }
300
301 return status;
302 }
303
304 int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode)
305 {
306 int status = 0;
307
308 /*
309 * FIXME: We need to implement the AFE code for LOW IF and for HI IF.
310 * Currently, only baseband works.
311 */
312
313 switch (mode) {
314 case AFE_MODE_LOW_IF:
315 cx231xx_Setup_AFE_for_LowIF(dev);
316 break;
317 case AFE_MODE_BASEBAND:
318 status = cx231xx_afe_setup_AFE_for_baseband(dev);
319 break;
320 case AFE_MODE_EU_HI_IF:
321 /* SetupAFEforEuHiIF(); */
322 break;
323 case AFE_MODE_US_HI_IF:
324 /* SetupAFEforUsHiIF(); */
325 break;
326 case AFE_MODE_JAPAN_HI_IF:
327 /* SetupAFEforJapanHiIF(); */
328 break;
329 }
330
331 if ((mode != dev->afe_mode) &&
332 (dev->video_input == CX231XX_VMUX_TELEVISION))
333 status = cx231xx_afe_adjust_ref_count(dev,
334 CX231XX_VMUX_TELEVISION);
335
336 dev->afe_mode = mode;
337
338 return status;
339 }
340
341 int cx231xx_afe_update_power_control(struct cx231xx *dev,
342 enum AV_MODE avmode)
343 {
344 u8 afe_power_status = 0;
345 int status = 0;
346
347 switch (dev->model) {
348 case CX231XX_BOARD_CNXT_CARRAERA:
349 case CX231XX_BOARD_CNXT_RDE_250:
350 case CX231XX_BOARD_CNXT_SHELBY:
351 case CX231XX_BOARD_CNXT_RDU_250:
352 case CX231XX_BOARD_CNXT_RDE_253S:
353 case CX231XX_BOARD_CNXT_RDU_253S:
354 case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
355 case CX231XX_BOARD_HAUPPAUGE_EXETER:
356 case CX231XX_BOARD_HAUPPAUGE_USBLIVE2:
357 case CX231XX_BOARD_PV_PLAYTV_USB_HYBRID:
358 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL:
359 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC:
360 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
361 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
362 FLD_PWRDN_ENABLE_PLL)) {
363 status = afe_write_byte(dev, SUP_BLK_PWRDN,
364 FLD_PWRDN_TUNING_BIAS |
365 FLD_PWRDN_ENABLE_PLL);
366 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
367 &afe_power_status);
368 if (status < 0)
369 break;
370 }
371
372 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
373 0x00);
374 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
375 0x00);
376 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
377 0x00);
378 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
379 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
380 0x70);
381 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
382 0x70);
383 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
384 0x70);
385
386 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
387 &afe_power_status);
388 afe_power_status |= FLD_PWRDN_PD_BANDGAP |
389 FLD_PWRDN_PD_BIAS |
390 FLD_PWRDN_PD_TUNECK;
391 status |= afe_write_byte(dev, SUP_BLK_PWRDN,
392 afe_power_status);
393 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
394 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
395 FLD_PWRDN_ENABLE_PLL)) {
396 status = afe_write_byte(dev, SUP_BLK_PWRDN,
397 FLD_PWRDN_TUNING_BIAS |
398 FLD_PWRDN_ENABLE_PLL);
399 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
400 &afe_power_status);
401 if (status < 0)
402 break;
403 }
404
405 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
406 0x00);
407 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
408 0x00);
409 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
410 0x00);
411 } else {
412 cx231xx_info("Invalid AV mode input\n");
413 status = -1;
414 }
415 break;
416 default:
417 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
418 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
419 FLD_PWRDN_ENABLE_PLL)) {
420 status = afe_write_byte(dev, SUP_BLK_PWRDN,
421 FLD_PWRDN_TUNING_BIAS |
422 FLD_PWRDN_ENABLE_PLL);
423 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
424 &afe_power_status);
425 if (status < 0)
426 break;
427 }
428
429 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
430 0x40);
431 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
432 0x40);
433 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
434 0x00);
435 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
436 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
437 0x70);
438 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
439 0x70);
440 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
441 0x70);
442
443 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
444 &afe_power_status);
445 afe_power_status |= FLD_PWRDN_PD_BANDGAP |
446 FLD_PWRDN_PD_BIAS |
447 FLD_PWRDN_PD_TUNECK;
448 status |= afe_write_byte(dev, SUP_BLK_PWRDN,
449 afe_power_status);
450 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
451 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
452 FLD_PWRDN_ENABLE_PLL)) {
453 status = afe_write_byte(dev, SUP_BLK_PWRDN,
454 FLD_PWRDN_TUNING_BIAS |
455 FLD_PWRDN_ENABLE_PLL);
456 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
457 &afe_power_status);
458 if (status < 0)
459 break;
460 }
461
462 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
463 0x00);
464 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
465 0x00);
466 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
467 0x40);
468 } else {
469 cx231xx_info("Invalid AV mode input\n");
470 status = -1;
471 }
472 } /* switch */
473
474 return status;
475 }
476
477 int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input)
478 {
479 u8 input_mode = 0;
480 u8 ntf_mode = 0;
481 int status = 0;
482
483 dev->video_input = video_input;
484
485 if (video_input == CX231XX_VMUX_TELEVISION) {
486 status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode);
487 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3,
488 &ntf_mode);
489 } else {
490 status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode);
491 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1,
492 &ntf_mode);
493 }
494
495 input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1);
496
497 switch (input_mode) {
498 case SINGLE_ENDED:
499 dev->afe_ref_count = 0x23C;
500 break;
501 case LOW_IF:
502 dev->afe_ref_count = 0x24C;
503 break;
504 case EU_IF:
505 dev->afe_ref_count = 0x258;
506 break;
507 case US_IF:
508 dev->afe_ref_count = 0x260;
509 break;
510 default:
511 break;
512 }
513
514 status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count);
515
516 return status;
517 }
518
519 /******************************************************************************
520 * V I D E O / A U D I O D E C O D E R C O N T R O L functions *
521 ******************************************************************************/
522 static int vid_blk_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
523 {
524 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
525 saddr, 2, data, 1);
526 }
527
528 static int vid_blk_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
529 {
530 int status;
531 u32 temp = 0;
532
533 status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
534 saddr, 2, &temp, 1);
535 *data = (u8) temp;
536 return status;
537 }
538
539 static int vid_blk_write_word(struct cx231xx *dev, u16 saddr, u32 data)
540 {
541 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
542 saddr, 2, data, 4);
543 }
544
545 static int vid_blk_read_word(struct cx231xx *dev, u16 saddr, u32 *data)
546 {
547 return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
548 saddr, 2, data, 4);
549 }
550 int cx231xx_check_fw(struct cx231xx *dev)
551 {
552 u8 temp = 0;
553 int status = 0;
554 status = vid_blk_read_byte(dev, DL_CTL_ADDRESS_LOW, &temp);
555 if (status < 0)
556 return status;
557 else
558 return temp;
559
560 }
561
562 int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input)
563 {
564 int status = 0;
565
566 switch (INPUT(input)->type) {
567 case CX231XX_VMUX_COMPOSITE1:
568 case CX231XX_VMUX_SVIDEO:
569 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
570 (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) {
571 /* External AV */
572 status = cx231xx_set_power_mode(dev,
573 POLARIS_AVMODE_ENXTERNAL_AV);
574 if (status < 0) {
575 cx231xx_errdev("%s: set_power_mode : Failed to"
576 " set Power - errCode [%d]!\n",
577 __func__, status);
578 return status;
579 }
580 }
581 status = cx231xx_set_decoder_video_input(dev,
582 INPUT(input)->type,
583 INPUT(input)->vmux);
584 break;
585 case CX231XX_VMUX_TELEVISION:
586 case CX231XX_VMUX_CABLE:
587 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
588 (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) {
589 /* Tuner */
590 status = cx231xx_set_power_mode(dev,
591 POLARIS_AVMODE_ANALOGT_TV);
592 if (status < 0) {
593 cx231xx_errdev("%s: set_power_mode:Failed"
594 " to set Power - errCode [%d]!\n",
595 __func__, status);
596 return status;
597 }
598 }
599 if (dev->tuner_type == TUNER_NXP_TDA18271)
600 status = cx231xx_set_decoder_video_input(dev,
601 CX231XX_VMUX_TELEVISION,
602 INPUT(input)->vmux);
603 else
604 status = cx231xx_set_decoder_video_input(dev,
605 CX231XX_VMUX_COMPOSITE1,
606 INPUT(input)->vmux);
607
608 break;
609 default:
610 cx231xx_errdev("%s: set_power_mode : Unknown Input %d !\n",
611 __func__, INPUT(input)->type);
612 break;
613 }
614
615 /* save the selection */
616 dev->video_input = input;
617
618 return status;
619 }
620
621 int cx231xx_set_decoder_video_input(struct cx231xx *dev,
622 u8 pin_type, u8 input)
623 {
624 int status = 0;
625 u32 value = 0;
626
627 if (pin_type != dev->video_input) {
628 status = cx231xx_afe_adjust_ref_count(dev, pin_type);
629 if (status < 0) {
630 cx231xx_errdev("%s: adjust_ref_count :Failed to set"
631 "AFE input mux - errCode [%d]!\n",
632 __func__, status);
633 return status;
634 }
635 }
636
637 /* call afe block to set video inputs */
638 status = cx231xx_afe_set_input_mux(dev, input);
639 if (status < 0) {
640 cx231xx_errdev("%s: set_input_mux :Failed to set"
641 " AFE input mux - errCode [%d]!\n",
642 __func__, status);
643 return status;
644 }
645
646 switch (pin_type) {
647 case CX231XX_VMUX_COMPOSITE1:
648 status = vid_blk_read_word(dev, AFE_CTRL, &value);
649 value |= (0 << 13) | (1 << 4);
650 value &= ~(1 << 5);
651
652 /* set [24:23] [22:15] to 0 */
653 value &= (~(0x1ff8000));
654 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
655 value |= 0x1000000;
656 status = vid_blk_write_word(dev, AFE_CTRL, value);
657
658 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
659 value |= (1 << 7);
660 status = vid_blk_write_word(dev, OUT_CTRL1, value);
661
662 /* Set output mode */
663 status = cx231xx_read_modify_write_i2c_dword(dev,
664 VID_BLK_I2C_ADDRESS,
665 OUT_CTRL1,
666 FLD_OUT_MODE,
667 dev->board.output_mode);
668
669 /* Tell DIF object to go to baseband mode */
670 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
671 if (status < 0) {
672 cx231xx_errdev("%s: cx231xx_dif set to By pass"
673 " mode- errCode [%d]!\n",
674 __func__, status);
675 return status;
676 }
677
678 /* Read the DFE_CTRL1 register */
679 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
680
681 /* enable the VBI_GATE_EN */
682 value |= FLD_VBI_GATE_EN;
683
684 /* Enable the auto-VGA enable */
685 value |= FLD_VGA_AUTO_EN;
686
687 /* Write it back */
688 status = vid_blk_write_word(dev, DFE_CTRL1, value);
689
690 /* Disable auto config of registers */
691 status = cx231xx_read_modify_write_i2c_dword(dev,
692 VID_BLK_I2C_ADDRESS,
693 MODE_CTRL, FLD_ACFG_DIS,
694 cx231xx_set_field(FLD_ACFG_DIS, 1));
695
696 /* Set CVBS input mode */
697 status = cx231xx_read_modify_write_i2c_dword(dev,
698 VID_BLK_I2C_ADDRESS,
699 MODE_CTRL, FLD_INPUT_MODE,
700 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0));
701 break;
702 case CX231XX_VMUX_SVIDEO:
703 /* Disable the use of DIF */
704
705 status = vid_blk_read_word(dev, AFE_CTRL, &value);
706
707 /* set [24:23] [22:15] to 0 */
708 value &= (~(0x1ff8000));
709 /* set FUNC_MODE[24:23] = 2
710 IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */
711 value |= 0x1000010;
712 status = vid_blk_write_word(dev, AFE_CTRL, value);
713
714 /* Tell DIF object to go to baseband mode */
715 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
716 if (status < 0) {
717 cx231xx_errdev("%s: cx231xx_dif set to By pass"
718 " mode- errCode [%d]!\n",
719 __func__, status);
720 return status;
721 }
722
723 /* Read the DFE_CTRL1 register */
724 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
725
726 /* enable the VBI_GATE_EN */
727 value |= FLD_VBI_GATE_EN;
728
729 /* Enable the auto-VGA enable */
730 value |= FLD_VGA_AUTO_EN;
731
732 /* Write it back */
733 status = vid_blk_write_word(dev, DFE_CTRL1, value);
734
735 /* Disable auto config of registers */
736 status = cx231xx_read_modify_write_i2c_dword(dev,
737 VID_BLK_I2C_ADDRESS,
738 MODE_CTRL, FLD_ACFG_DIS,
739 cx231xx_set_field(FLD_ACFG_DIS, 1));
740
741 /* Set YC input mode */
742 status = cx231xx_read_modify_write_i2c_dword(dev,
743 VID_BLK_I2C_ADDRESS,
744 MODE_CTRL,
745 FLD_INPUT_MODE,
746 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1));
747
748 /* Chroma to ADC2 */
749 status = vid_blk_read_word(dev, AFE_CTRL, &value);
750 value |= FLD_CHROMA_IN_SEL; /* set the chroma in select */
751
752 /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8)
753 This sets them to use video
754 rather than audio. Only one of the two will be in use. */
755 value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3);
756
757 status = vid_blk_write_word(dev, AFE_CTRL, value);
758
759 status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND);
760 break;
761 case CX231XX_VMUX_TELEVISION:
762 case CX231XX_VMUX_CABLE:
763 default:
764 /* TODO: Test if this is also needed for xc2028/xc3028 */
765 if (dev->board.tuner_type == TUNER_XC5000) {
766 /* Disable the use of DIF */
767
768 status = vid_blk_read_word(dev, AFE_CTRL, &value);
769 value |= (0 << 13) | (1 << 4);
770 value &= ~(1 << 5);
771
772 /* set [24:23] [22:15] to 0 */
773 value &= (~(0x1FF8000));
774 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
775 value |= 0x1000000;
776 status = vid_blk_write_word(dev, AFE_CTRL, value);
777
778 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
779 value |= (1 << 7);
780 status = vid_blk_write_word(dev, OUT_CTRL1, value);
781
782 /* Set output mode */
783 status = cx231xx_read_modify_write_i2c_dword(dev,
784 VID_BLK_I2C_ADDRESS,
785 OUT_CTRL1, FLD_OUT_MODE,
786 dev->board.output_mode);
787
788 /* Tell DIF object to go to baseband mode */
789 status = cx231xx_dif_set_standard(dev,
790 DIF_USE_BASEBAND);
791 if (status < 0) {
792 cx231xx_errdev("%s: cx231xx_dif set to By pass"
793 " mode- errCode [%d]!\n",
794 __func__, status);
795 return status;
796 }
797
798 /* Read the DFE_CTRL1 register */
799 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
800
801 /* enable the VBI_GATE_EN */
802 value |= FLD_VBI_GATE_EN;
803
804 /* Enable the auto-VGA enable */
805 value |= FLD_VGA_AUTO_EN;
806
807 /* Write it back */
808 status = vid_blk_write_word(dev, DFE_CTRL1, value);
809
810 /* Disable auto config of registers */
811 status = cx231xx_read_modify_write_i2c_dword(dev,
812 VID_BLK_I2C_ADDRESS,
813 MODE_CTRL, FLD_ACFG_DIS,
814 cx231xx_set_field(FLD_ACFG_DIS, 1));
815
816 /* Set CVBS input mode */
817 status = cx231xx_read_modify_write_i2c_dword(dev,
818 VID_BLK_I2C_ADDRESS,
819 MODE_CTRL, FLD_INPUT_MODE,
820 cx231xx_set_field(FLD_INPUT_MODE,
821 INPUT_MODE_CVBS_0));
822 } else {
823 /* Enable the DIF for the tuner */
824
825 /* Reinitialize the DIF */
826 status = cx231xx_dif_set_standard(dev, dev->norm);
827 if (status < 0) {
828 cx231xx_errdev("%s: cx231xx_dif set to By pass"
829 " mode- errCode [%d]!\n",
830 __func__, status);
831 return status;
832 }
833
834 /* Make sure bypass is cleared */
835 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value);
836
837 /* Clear the bypass bit */
838 value &= ~FLD_DIF_DIF_BYPASS;
839
840 /* Enable the use of the DIF block */
841 status = vid_blk_write_word(dev, DIF_MISC_CTRL, value);
842
843 /* Read the DFE_CTRL1 register */
844 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
845
846 /* Disable the VBI_GATE_EN */
847 value &= ~FLD_VBI_GATE_EN;
848
849 /* Enable the auto-VGA enable, AGC, and
850 set the skip count to 2 */
851 value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000;
852
853 /* Write it back */
854 status = vid_blk_write_word(dev, DFE_CTRL1, value);
855
856 /* Wait until AGC locks up */
857 msleep(1);
858
859 /* Disable the auto-VGA enable AGC */
860 value &= ~(FLD_VGA_AUTO_EN);
861
862 /* Write it back */
863 status = vid_blk_write_word(dev, DFE_CTRL1, value);
864
865 /* Enable Polaris B0 AGC output */
866 status = vid_blk_read_word(dev, PIN_CTRL, &value);
867 value |= (FLD_OEF_AGC_RF) |
868 (FLD_OEF_AGC_IFVGA) |
869 (FLD_OEF_AGC_IF);
870 status = vid_blk_write_word(dev, PIN_CTRL, value);
871
872 /* Set output mode */
873 status = cx231xx_read_modify_write_i2c_dword(dev,
874 VID_BLK_I2C_ADDRESS,
875 OUT_CTRL1, FLD_OUT_MODE,
876 dev->board.output_mode);
877
878 /* Disable auto config of registers */
879 status = cx231xx_read_modify_write_i2c_dword(dev,
880 VID_BLK_I2C_ADDRESS,
881 MODE_CTRL, FLD_ACFG_DIS,
882 cx231xx_set_field(FLD_ACFG_DIS, 1));
883
884 /* Set CVBS input mode */
885 status = cx231xx_read_modify_write_i2c_dword(dev,
886 VID_BLK_I2C_ADDRESS,
887 MODE_CTRL, FLD_INPUT_MODE,
888 cx231xx_set_field(FLD_INPUT_MODE,
889 INPUT_MODE_CVBS_0));
890
891 /* Set some bits in AFE_CTRL so that channel 2 or 3
892 * is ready to receive audio */
893 /* Clear clamp for channels 2 and 3 (bit 16-17) */
894 /* Clear droop comp (bit 19-20) */
895 /* Set VGA_SEL (for audio control) (bit 7-8) */
896 status = vid_blk_read_word(dev, AFE_CTRL, &value);
897
898 /*Set Func mode:01-DIF 10-baseband 11-YUV*/
899 value &= (~(FLD_FUNC_MODE));
900 value |= 0x800000;
901
902 value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2;
903
904 status = vid_blk_write_word(dev, AFE_CTRL, value);
905
906 if (dev->tuner_type == TUNER_NXP_TDA18271) {
907 status = vid_blk_read_word(dev, PIN_CTRL,
908 &value);
909 status = vid_blk_write_word(dev, PIN_CTRL,
910 (value & 0xFFFFFFEF));
911 }
912
913 break;
914
915 }
916 break;
917 }
918
919 /* Set raw VBI mode */
920 status = cx231xx_read_modify_write_i2c_dword(dev,
921 VID_BLK_I2C_ADDRESS,
922 OUT_CTRL1, FLD_VBIHACTRAW_EN,
923 cx231xx_set_field(FLD_VBIHACTRAW_EN, 1));
924
925 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
926 if (value & 0x02) {
927 value |= (1 << 19);
928 status = vid_blk_write_word(dev, OUT_CTRL1, value);
929 }
930
931 return status;
932 }
933
934 void cx231xx_enable656(struct cx231xx *dev)
935 {
936 u8 temp = 0;
937 int status;
938 /*enable TS1 data[0:7] as output to export 656*/
939
940 status = vid_blk_write_byte(dev, TS1_PIN_CTL0, 0xFF);
941
942 /*enable TS1 clock as output to export 656*/
943
944 status = vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
945 temp = temp|0x04;
946
947 status = vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
948
949 }
950 EXPORT_SYMBOL_GPL(cx231xx_enable656);
951
952 void cx231xx_disable656(struct cx231xx *dev)
953 {
954 u8 temp = 0;
955 int status;
956
957
958 status = vid_blk_write_byte(dev, TS1_PIN_CTL0, 0x00);
959
960 status = vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
961 temp = temp&0xFB;
962
963 status = vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
964 }
965 EXPORT_SYMBOL_GPL(cx231xx_disable656);
966
967 /*
968 * Handle any video-mode specific overrides that are different
969 * on a per video standards basis after touching the MODE_CTRL
970 * register which resets many values for autodetect
971 */
972 int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
973 {
974 int status = 0;
975
976 cx231xx_info("do_mode_ctrl_overrides : 0x%x\n",
977 (unsigned int)dev->norm);
978
979 /* Change the DFE_CTRL3 bp_percent to fix flagging */
980 status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280);
981
982 if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) {
983 cx231xx_info("do_mode_ctrl_overrides NTSC\n");
984
985 /* Move the close caption lines out of active video,
986 adjust the active video start point */
987 status = cx231xx_read_modify_write_i2c_dword(dev,
988 VID_BLK_I2C_ADDRESS,
989 VERT_TIM_CTRL,
990 FLD_VBLANK_CNT, 0x18);
991 status = cx231xx_read_modify_write_i2c_dword(dev,
992 VID_BLK_I2C_ADDRESS,
993 VERT_TIM_CTRL,
994 FLD_VACTIVE_CNT,
995 0x1E7000);
996 status = cx231xx_read_modify_write_i2c_dword(dev,
997 VID_BLK_I2C_ADDRESS,
998 VERT_TIM_CTRL,
999 FLD_V656BLANK_CNT,
1000 0x1C000000);
1001
1002 status = cx231xx_read_modify_write_i2c_dword(dev,
1003 VID_BLK_I2C_ADDRESS,
1004 HORIZ_TIM_CTRL,
1005 FLD_HBLANK_CNT,
1006 cx231xx_set_field
1007 (FLD_HBLANK_CNT, 0x79));
1008
1009 } else if (dev->norm & V4L2_STD_SECAM) {
1010 cx231xx_info("do_mode_ctrl_overrides SECAM\n");
1011 status = cx231xx_read_modify_write_i2c_dword(dev,
1012 VID_BLK_I2C_ADDRESS,
1013 VERT_TIM_CTRL,
1014 FLD_VBLANK_CNT, 0x20);
1015 status = cx231xx_read_modify_write_i2c_dword(dev,
1016 VID_BLK_I2C_ADDRESS,
1017 VERT_TIM_CTRL,
1018 FLD_VACTIVE_CNT,
1019 cx231xx_set_field
1020 (FLD_VACTIVE_CNT,
1021 0x244));
1022 status = cx231xx_read_modify_write_i2c_dword(dev,
1023 VID_BLK_I2C_ADDRESS,
1024 VERT_TIM_CTRL,
1025 FLD_V656BLANK_CNT,
1026 cx231xx_set_field
1027 (FLD_V656BLANK_CNT,
1028 0x24));
1029 /* Adjust the active video horizontal start point */
1030 status = cx231xx_read_modify_write_i2c_dword(dev,
1031 VID_BLK_I2C_ADDRESS,
1032 HORIZ_TIM_CTRL,
1033 FLD_HBLANK_CNT,
1034 cx231xx_set_field
1035 (FLD_HBLANK_CNT, 0x85));
1036 } else {
1037 cx231xx_info("do_mode_ctrl_overrides PAL\n");
1038 status = cx231xx_read_modify_write_i2c_dword(dev,
1039 VID_BLK_I2C_ADDRESS,
1040 VERT_TIM_CTRL,
1041 FLD_VBLANK_CNT, 0x20);
1042 status = cx231xx_read_modify_write_i2c_dword(dev,
1043 VID_BLK_I2C_ADDRESS,
1044 VERT_TIM_CTRL,
1045 FLD_VACTIVE_CNT,
1046 cx231xx_set_field
1047 (FLD_VACTIVE_CNT,
1048 0x244));
1049 status = cx231xx_read_modify_write_i2c_dword(dev,
1050 VID_BLK_I2C_ADDRESS,
1051 VERT_TIM_CTRL,
1052 FLD_V656BLANK_CNT,
1053 cx231xx_set_field
1054 (FLD_V656BLANK_CNT,
1055 0x24));
1056 /* Adjust the active video horizontal start point */
1057 status = cx231xx_read_modify_write_i2c_dword(dev,
1058 VID_BLK_I2C_ADDRESS,
1059 HORIZ_TIM_CTRL,
1060 FLD_HBLANK_CNT,
1061 cx231xx_set_field
1062 (FLD_HBLANK_CNT, 0x85));
1063
1064 }
1065
1066 return status;
1067 }
1068
1069 int cx231xx_unmute_audio(struct cx231xx *dev)
1070 {
1071 return vid_blk_write_byte(dev, PATH1_VOL_CTL, 0x24);
1072 }
1073 EXPORT_SYMBOL_GPL(cx231xx_unmute_audio);
1074
1075 int stopAudioFirmware(struct cx231xx *dev)
1076 {
1077 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x03);
1078 }
1079
1080 int restartAudioFirmware(struct cx231xx *dev)
1081 {
1082 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x13);
1083 }
1084
1085 int cx231xx_set_audio_input(struct cx231xx *dev, u8 input)
1086 {
1087 int status = 0;
1088 enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE;
1089
1090 switch (INPUT(input)->amux) {
1091 case CX231XX_AMUX_VIDEO:
1092 ainput = AUDIO_INPUT_TUNER_TV;
1093 break;
1094 case CX231XX_AMUX_LINE_IN:
1095 status = cx231xx_i2s_blk_set_audio_input(dev, input);
1096 ainput = AUDIO_INPUT_LINE;
1097 break;
1098 default:
1099 break;
1100 }
1101
1102 status = cx231xx_set_audio_decoder_input(dev, ainput);
1103
1104 return status;
1105 }
1106
1107 int cx231xx_set_audio_decoder_input(struct cx231xx *dev,
1108 enum AUDIO_INPUT audio_input)
1109 {
1110 u32 dwval;
1111 int status;
1112 u8 gen_ctrl;
1113 u32 value = 0;
1114
1115 /* Put it in soft reset */
1116 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
1117 gen_ctrl |= 1;
1118 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
1119
1120 switch (audio_input) {
1121 case AUDIO_INPUT_LINE:
1122 /* setup AUD_IO control from Merlin paralle output */
1123 value = cx231xx_set_field(FLD_AUD_CHAN1_SRC,
1124 AUD_CHAN_SRC_PARALLEL);
1125 status = vid_blk_write_word(dev, AUD_IO_CTRL, value);
1126
1127 /* setup input to Merlin, SRC2 connect to AC97
1128 bypass upsample-by-2, slave mode, sony mode, left justify
1129 adr 091c, dat 01000000 */
1130 status = vid_blk_read_word(dev, AC97_CTL, &dwval);
1131
1132 status = vid_blk_write_word(dev, AC97_CTL,
1133 (dwval | FLD_AC97_UP2X_BYPASS));
1134
1135 /* select the parallel1 and SRC3 */
1136 status = vid_blk_write_word(dev, BAND_OUT_SEL,
1137 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) |
1138 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) |
1139 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0));
1140
1141 /* unmute all, AC97 in, independence mode
1142 adr 08d0, data 0x00063073 */
1143 status = vid_blk_write_word(dev, DL_CTL, 0x3000001);
1144 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073);
1145
1146 /* set AVC maximum threshold, adr 08d4, dat ffff0024 */
1147 status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval);
1148 status = vid_blk_write_word(dev, PATH1_VOL_CTL,
1149 (dwval | FLD_PATH1_AVC_THRESHOLD));
1150
1151 /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */
1152 status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval);
1153 status = vid_blk_write_word(dev, PATH1_SC_CTL,
1154 (dwval | FLD_PATH1_SC_THRESHOLD));
1155 break;
1156
1157 case AUDIO_INPUT_TUNER_TV:
1158 default:
1159 status = stopAudioFirmware(dev);
1160 /* Setup SRC sources and clocks */
1161 status = vid_blk_write_word(dev, BAND_OUT_SEL,
1162 cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00) |
1163 cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01) |
1164 cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00) |
1165 cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02) |
1166 cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02) |
1167 cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03) |
1168 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00) |
1169 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00) |
1170 cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) |
1171 cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03) |
1172 cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00) |
1173 cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02) |
1174 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01));
1175
1176 /* Setup the AUD_IO control */
1177 status = vid_blk_write_word(dev, AUD_IO_CTRL,
1178 cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00) |
1179 cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00) |
1180 cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) |
1181 cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) |
1182 cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03));
1183
1184 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870);
1185
1186 /* setAudioStandard(_audio_standard); */
1187 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870);
1188
1189 status = restartAudioFirmware(dev);
1190
1191 switch (dev->board.tuner_type) {
1192 case TUNER_XC5000:
1193 /* SIF passthrough at 28.6363 MHz sample rate */
1194 status = cx231xx_read_modify_write_i2c_dword(dev,
1195 VID_BLK_I2C_ADDRESS,
1196 CHIP_CTRL,
1197 FLD_SIF_EN,
1198 cx231xx_set_field(FLD_SIF_EN, 1));
1199 break;
1200 case TUNER_NXP_TDA18271:
1201 /* Normal mode: SIF passthrough at 14.32 MHz */
1202 status = cx231xx_read_modify_write_i2c_dword(dev,
1203 VID_BLK_I2C_ADDRESS,
1204 CHIP_CTRL,
1205 FLD_SIF_EN,
1206 cx231xx_set_field(FLD_SIF_EN, 0));
1207 break;
1208 default:
1209 /* This is just a casual suggestion to people adding
1210 new boards in case they use a tuner type we don't
1211 currently know about */
1212 printk(KERN_INFO "Unknown tuner type configuring SIF");
1213 break;
1214 }
1215 break;
1216
1217 case AUDIO_INPUT_TUNER_FM:
1218 /* use SIF for FM radio
1219 setupFM();
1220 setAudioStandard(_audio_standard);
1221 */
1222 break;
1223
1224 case AUDIO_INPUT_MUTE:
1225 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012);
1226 break;
1227 }
1228
1229 /* Take it out of soft reset */
1230 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
1231 gen_ctrl &= ~1;
1232 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
1233
1234 return status;
1235 }
1236
1237 /******************************************************************************
1238 * C H I P Specific C O N T R O L functions *
1239 ******************************************************************************/
1240 int cx231xx_init_ctrl_pin_status(struct cx231xx *dev)
1241 {
1242 u32 value;
1243 int status = 0;
1244
1245 status = vid_blk_read_word(dev, PIN_CTRL, &value);
1246 value |= (~dev->board.ctl_pin_status_mask);
1247 status = vid_blk_write_word(dev, PIN_CTRL, value);
1248
1249 return status;
1250 }
1251
1252 int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev,
1253 u8 analog_or_digital)
1254 {
1255 int status = 0;
1256
1257 /* first set the direction to output */
1258 status = cx231xx_set_gpio_direction(dev,
1259 dev->board.
1260 agc_analog_digital_select_gpio, 1);
1261
1262 /* 0 - demod ; 1 - Analog mode */
1263 status = cx231xx_set_gpio_value(dev,
1264 dev->board.agc_analog_digital_select_gpio,
1265 analog_or_digital);
1266
1267 return status;
1268 }
1269
1270 int cx231xx_enable_i2c_port_3(struct cx231xx *dev, bool is_port_3)
1271 {
1272 u8 value[4] = { 0, 0, 0, 0 };
1273 int status = 0;
1274 bool current_is_port_3;
1275
1276 if (dev->board.dont_use_port_3)
1277 is_port_3 = false;
1278 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER,
1279 PWR_CTL_EN, value, 4);
1280 if (status < 0)
1281 return status;
1282
1283 current_is_port_3 = value[0] & I2C_DEMOD_EN ? true : false;
1284
1285 /* Just return, if already using the right port */
1286 if (current_is_port_3 == is_port_3)
1287 return 0;
1288
1289 if (is_port_3)
1290 value[0] |= I2C_DEMOD_EN;
1291 else
1292 value[0] &= ~I2C_DEMOD_EN;
1293
1294 cx231xx_info("Changing the i2c master port to %d\n",
1295 is_port_3 ? 3 : 1);
1296
1297 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1298 PWR_CTL_EN, value, 4);
1299
1300 return status;
1301
1302 }
1303 EXPORT_SYMBOL_GPL(cx231xx_enable_i2c_port_3);
1304
1305 void update_HH_register_after_set_DIF(struct cx231xx *dev)
1306 {
1307 /*
1308 u8 status = 0;
1309 u32 value = 0;
1310
1311 vid_blk_write_word(dev, PIN_CTRL, 0xA0FFF82F);
1312 vid_blk_write_word(dev, DIF_MISC_CTRL, 0x0A203F11);
1313 vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0x1BEFBF06);
1314
1315 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1316 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390);
1317 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1318 */
1319 }
1320
1321 void cx231xx_dump_HH_reg(struct cx231xx *dev)
1322 {
1323 u8 status = 0;
1324 u32 value = 0;
1325 u16 i = 0;
1326
1327 value = 0x45005390;
1328 status = vid_blk_write_word(dev, 0x104, value);
1329
1330 for (i = 0x100; i < 0x140; i++) {
1331 status = vid_blk_read_word(dev, i, &value);
1332 cx231xx_info("reg0x%x=0x%x\n", i, value);
1333 i = i+3;
1334 }
1335
1336 for (i = 0x300; i < 0x400; i++) {
1337 status = vid_blk_read_word(dev, i, &value);
1338 cx231xx_info("reg0x%x=0x%x\n", i, value);
1339 i = i+3;
1340 }
1341
1342 for (i = 0x400; i < 0x440; i++) {
1343 status = vid_blk_read_word(dev, i, &value);
1344 cx231xx_info("reg0x%x=0x%x\n", i, value);
1345 i = i+3;
1346 }
1347
1348 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1349 cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
1350 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390);
1351 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1352 cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
1353 }
1354
1355 void cx231xx_dump_SC_reg(struct cx231xx *dev)
1356 {
1357 u8 value[4] = { 0, 0, 0, 0 };
1358 int status = 0;
1359 cx231xx_info("cx231xx_dump_SC_reg!\n");
1360
1361 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, BOARD_CFG_STAT,
1362 value, 4);
1363 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", BOARD_CFG_STAT, value[0],
1364 value[1], value[2], value[3]);
1365 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS_MODE_REG,
1366 value, 4);
1367 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS_MODE_REG, value[0],
1368 value[1], value[2], value[3]);
1369 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_CFG_REG,
1370 value, 4);
1371 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_CFG_REG, value[0],
1372 value[1], value[2], value[3]);
1373 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_LENGTH_REG,
1374 value, 4);
1375 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_LENGTH_REG, value[0],
1376 value[1], value[2], value[3]);
1377
1378 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_CFG_REG,
1379 value, 4);
1380 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_CFG_REG, value[0],
1381 value[1], value[2], value[3]);
1382 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_LENGTH_REG,
1383 value, 4);
1384 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_LENGTH_REG, value[0],
1385 value[1], value[2], value[3]);
1386 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
1387 value, 4);
1388 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", EP_MODE_SET, value[0],
1389 value[1], value[2], value[3]);
1390 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN1,
1391 value, 4);
1392 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN1, value[0],
1393 value[1], value[2], value[3]);
1394
1395 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN2,
1396 value, 4);
1397 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN2, value[0],
1398 value[1], value[2], value[3]);
1399 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN3,
1400 value, 4);
1401 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN3, value[0],
1402 value[1], value[2], value[3]);
1403 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK0,
1404 value, 4);
1405 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK0, value[0],
1406 value[1], value[2], value[3]);
1407 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK1,
1408 value, 4);
1409 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK1, value[0],
1410 value[1], value[2], value[3]);
1411
1412 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK2,
1413 value, 4);
1414 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK2, value[0],
1415 value[1], value[2], value[3]);
1416 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_GAIN,
1417 value, 4);
1418 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_GAIN, value[0],
1419 value[1], value[2], value[3]);
1420 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_CAR_REG,
1421 value, 4);
1422 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_CAR_REG, value[0],
1423 value[1], value[2], value[3]);
1424 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG1,
1425 value, 4);
1426 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG1, value[0],
1427 value[1], value[2], value[3]);
1428
1429 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG2,
1430 value, 4);
1431 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG2, value[0],
1432 value[1], value[2], value[3]);
1433 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
1434 value, 4);
1435 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", PWR_CTL_EN, value[0],
1436 value[1], value[2], value[3]);
1437
1438
1439 }
1440
1441 void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev)
1442
1443 {
1444 u8 status = 0;
1445 u8 value = 0;
1446
1447
1448
1449 status = afe_read_byte(dev, ADC_STATUS2_CH3, &value);
1450 value = (value & 0xFE)|0x01;
1451 status = afe_write_byte(dev, ADC_STATUS2_CH3, value);
1452
1453 status = afe_read_byte(dev, ADC_STATUS2_CH3, &value);
1454 value = (value & 0xFE)|0x00;
1455 status = afe_write_byte(dev, ADC_STATUS2_CH3, value);
1456
1457
1458 /*
1459 config colibri to lo-if mode
1460
1461 FIXME: ntf_mode = 2'b00 by default. But set 0x1 would reduce
1462 the diff IF input by half,
1463
1464 for low-if agc defect
1465 */
1466
1467 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, &value);
1468 value = (value & 0xFC)|0x00;
1469 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, value);
1470
1471 status = afe_read_byte(dev, ADC_INPUT_CH3, &value);
1472 value = (value & 0xF9)|0x02;
1473 status = afe_write_byte(dev, ADC_INPUT_CH3, value);
1474
1475 status = afe_read_byte(dev, ADC_FB_FRCRST_CH3, &value);
1476 value = (value & 0xFB)|0x04;
1477 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, value);
1478
1479 status = afe_read_byte(dev, ADC_DCSERVO_DEM_CH3, &value);
1480 value = (value & 0xFC)|0x03;
1481 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, value);
1482
1483 status = afe_read_byte(dev, ADC_CTRL_DAC1_CH3, &value);
1484 value = (value & 0xFB)|0x04;
1485 status = afe_write_byte(dev, ADC_CTRL_DAC1_CH3, value);
1486
1487 status = afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
1488 value = (value & 0xF8)|0x06;
1489 status = afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
1490
1491 status = afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
1492 value = (value & 0x8F)|0x40;
1493 status = afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
1494
1495 status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH3, &value);
1496 value = (value & 0xDF)|0x20;
1497 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, value);
1498 }
1499
1500 void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq,
1501 u8 spectral_invert, u32 mode)
1502 {
1503 u32 colibri_carrier_offset = 0;
1504 u8 status = 0;
1505 u32 func_mode = 0x01; /* Device has a DIF if this function is called */
1506 u32 standard = 0;
1507 u8 value[4] = { 0, 0, 0, 0 };
1508
1509 cx231xx_info("Enter cx231xx_set_Colibri_For_LowIF()\n");
1510 value[0] = (u8) 0x6F;
1511 value[1] = (u8) 0x6F;
1512 value[2] = (u8) 0x6F;
1513 value[3] = (u8) 0x6F;
1514 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1515 PWR_CTL_EN, value, 4);
1516
1517 /*Set colibri for low IF*/
1518 status = cx231xx_afe_set_mode(dev, AFE_MODE_LOW_IF);
1519
1520 /* Set C2HH for low IF operation.*/
1521 standard = dev->norm;
1522 status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
1523 func_mode, standard);
1524
1525 /* Get colibri offsets.*/
1526 colibri_carrier_offset = cx231xx_Get_Colibri_CarrierOffset(mode,
1527 standard);
1528
1529 cx231xx_info("colibri_carrier_offset=%d, standard=0x%x\n",
1530 colibri_carrier_offset, standard);
1531
1532 /* Set the band Pass filter for DIF*/
1533 cx231xx_set_DIF_bandpass(dev, (if_freq+colibri_carrier_offset),
1534 spectral_invert, mode);
1535 }
1536
1537 u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd)
1538 {
1539 u32 colibri_carrier_offset = 0;
1540
1541 if (mode == TUNER_MODE_FM_RADIO) {
1542 colibri_carrier_offset = 1100000;
1543 } else if (standerd & (V4L2_STD_MN | V4L2_STD_NTSC_M_JP)) {
1544 colibri_carrier_offset = 4832000; /*4.83MHz */
1545 } else if (standerd & (V4L2_STD_PAL_B | V4L2_STD_PAL_G)) {
1546 colibri_carrier_offset = 2700000; /*2.70MHz */
1547 } else if (standerd & (V4L2_STD_PAL_D | V4L2_STD_PAL_I
1548 | V4L2_STD_SECAM)) {
1549 colibri_carrier_offset = 2100000; /*2.10MHz */
1550 }
1551
1552 return colibri_carrier_offset;
1553 }
1554
1555 void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq,
1556 u8 spectral_invert, u32 mode)
1557 {
1558 unsigned long pll_freq_word;
1559 int status = 0;
1560 u32 dif_misc_ctrl_value = 0;
1561 u64 pll_freq_u64 = 0;
1562 u32 i = 0;
1563
1564 cx231xx_info("if_freq=%d;spectral_invert=0x%x;mode=0x%x\n",
1565 if_freq, spectral_invert, mode);
1566
1567
1568 if (mode == TUNER_MODE_FM_RADIO) {
1569 pll_freq_word = 0x905A1CAC;
1570 status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word);
1571
1572 } else /*KSPROPERTY_TUNER_MODE_TV*/{
1573 /* Calculate the PLL frequency word based on the adjusted if_freq*/
1574 pll_freq_word = if_freq;
1575 pll_freq_u64 = (u64)pll_freq_word << 28L;
1576 do_div(pll_freq_u64, 50000000);
1577 pll_freq_word = (u32)pll_freq_u64;
1578 /*pll_freq_word = 0x3463497;*/
1579 status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word);
1580
1581 if (spectral_invert) {
1582 if_freq -= 400000;
1583 /* Enable Spectral Invert*/
1584 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1585 &dif_misc_ctrl_value);
1586 dif_misc_ctrl_value = dif_misc_ctrl_value | 0x00200000;
1587 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1588 dif_misc_ctrl_value);
1589 } else {
1590 if_freq += 400000;
1591 /* Disable Spectral Invert*/
1592 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1593 &dif_misc_ctrl_value);
1594 dif_misc_ctrl_value = dif_misc_ctrl_value & 0xFFDFFFFF;
1595 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1596 dif_misc_ctrl_value);
1597 }
1598
1599 if_freq = (if_freq/100000)*100000;
1600
1601 if (if_freq < 3000000)
1602 if_freq = 3000000;
1603
1604 if (if_freq > 16000000)
1605 if_freq = 16000000;
1606 }
1607
1608 cx231xx_info("Enter IF=%zd\n",
1609 sizeof(Dif_set_array)/sizeof(struct dif_settings));
1610 for (i = 0; i < sizeof(Dif_set_array)/sizeof(struct dif_settings); i++) {
1611 if (Dif_set_array[i].if_freq == if_freq) {
1612 status = vid_blk_write_word(dev,
1613 Dif_set_array[i].register_address, Dif_set_array[i].value);
1614 }
1615 }
1616 }
1617
1618 /******************************************************************************
1619 * D I F - B L O C K C O N T R O L functions *
1620 ******************************************************************************/
1621 int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
1622 u32 function_mode, u32 standard)
1623 {
1624 int status = 0;
1625
1626
1627 if (mode == V4L2_TUNER_RADIO) {
1628 /* C2HH */
1629 /* lo if big signal */
1630 status = cx231xx_reg_mask_write(dev,
1631 VID_BLK_I2C_ADDRESS, 32,
1632 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1633 /* FUNC_MODE = DIF */
1634 status = cx231xx_reg_mask_write(dev,
1635 VID_BLK_I2C_ADDRESS, 32,
1636 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode);
1637 /* IF_MODE */
1638 status = cx231xx_reg_mask_write(dev,
1639 VID_BLK_I2C_ADDRESS, 32,
1640 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF);
1641 /* no inv */
1642 status = cx231xx_reg_mask_write(dev,
1643 VID_BLK_I2C_ADDRESS, 32,
1644 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1645 } else if (standard != DIF_USE_BASEBAND) {
1646 if (standard & V4L2_STD_MN) {
1647 /* lo if big signal */
1648 status = cx231xx_reg_mask_write(dev,
1649 VID_BLK_I2C_ADDRESS, 32,
1650 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1651 /* FUNC_MODE = DIF */
1652 status = cx231xx_reg_mask_write(dev,
1653 VID_BLK_I2C_ADDRESS, 32,
1654 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1655 function_mode);
1656 /* IF_MODE */
1657 status = cx231xx_reg_mask_write(dev,
1658 VID_BLK_I2C_ADDRESS, 32,
1659 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb);
1660 /* no inv */
1661 status = cx231xx_reg_mask_write(dev,
1662 VID_BLK_I2C_ADDRESS, 32,
1663 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1664 /* 0x124, AUD_CHAN1_SRC = 0x3 */
1665 status = cx231xx_reg_mask_write(dev,
1666 VID_BLK_I2C_ADDRESS, 32,
1667 AUD_IO_CTRL, 0, 31, 0x00000003);
1668 } else if ((standard == V4L2_STD_PAL_I) |
1669 (standard & V4L2_STD_PAL_D) |
1670 (standard & V4L2_STD_SECAM)) {
1671 /* C2HH setup */
1672 /* lo if big signal */
1673 status = cx231xx_reg_mask_write(dev,
1674 VID_BLK_I2C_ADDRESS, 32,
1675 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1676 /* FUNC_MODE = DIF */
1677 status = cx231xx_reg_mask_write(dev,
1678 VID_BLK_I2C_ADDRESS, 32,
1679 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1680 function_mode);
1681 /* IF_MODE */
1682 status = cx231xx_reg_mask_write(dev,
1683 VID_BLK_I2C_ADDRESS, 32,
1684 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF);
1685 /* no inv */
1686 status = cx231xx_reg_mask_write(dev,
1687 VID_BLK_I2C_ADDRESS, 32,
1688 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1689 } else {
1690 /* default PAL BG */
1691 /* C2HH setup */
1692 /* lo if big signal */
1693 status = cx231xx_reg_mask_write(dev,
1694 VID_BLK_I2C_ADDRESS, 32,
1695 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1696 /* FUNC_MODE = DIF */
1697 status = cx231xx_reg_mask_write(dev,
1698 VID_BLK_I2C_ADDRESS, 32,
1699 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1700 function_mode);
1701 /* IF_MODE */
1702 status = cx231xx_reg_mask_write(dev,
1703 VID_BLK_I2C_ADDRESS, 32,
1704 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE);
1705 /* no inv */
1706 status = cx231xx_reg_mask_write(dev,
1707 VID_BLK_I2C_ADDRESS, 32,
1708 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1709 }
1710 }
1711
1712 return status;
1713 }
1714
1715 int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1716 {
1717 int status = 0;
1718 u32 dif_misc_ctrl_value = 0;
1719 u32 func_mode = 0;
1720
1721 cx231xx_info("%s: setStandard to %x\n", __func__, standard);
1722
1723 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value);
1724 if (standard != DIF_USE_BASEBAND)
1725 dev->norm = standard;
1726
1727 switch (dev->model) {
1728 case CX231XX_BOARD_CNXT_CARRAERA:
1729 case CX231XX_BOARD_CNXT_RDE_250:
1730 case CX231XX_BOARD_CNXT_SHELBY:
1731 case CX231XX_BOARD_CNXT_RDU_250:
1732 case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
1733 case CX231XX_BOARD_HAUPPAUGE_EXETER:
1734 func_mode = 0x03;
1735 break;
1736 case CX231XX_BOARD_CNXT_RDE_253S:
1737 case CX231XX_BOARD_CNXT_RDU_253S:
1738 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL:
1739 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC:
1740 func_mode = 0x01;
1741 break;
1742 default:
1743 func_mode = 0x01;
1744 }
1745
1746 status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
1747 func_mode, standard);
1748
1749 if (standard == DIF_USE_BASEBAND) { /* base band */
1750 /* There is a different SRC_PHASE_INC value
1751 for baseband vs. DIF */
1752 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0xDF7DF83);
1753 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1754 &dif_misc_ctrl_value);
1755 dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS;
1756 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1757 dif_misc_ctrl_value);
1758 } else if (standard & V4L2_STD_PAL_D) {
1759 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1760 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1761 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1762 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1763 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1764 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1765 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1766 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1767 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1768 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1769 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1770 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1771 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1772 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1773 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1774 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1775 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1776 DIF_AGC_IF_INT_CURRENT, 0, 31,
1777 0x26001700);
1778 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1779 DIF_AGC_RF_CURRENT, 0, 31,
1780 0x00002660);
1781 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1782 DIF_VIDEO_AGC_CTRL, 0, 31,
1783 0x72500800);
1784 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1785 DIF_VID_AUD_OVERRIDE, 0, 31,
1786 0x27000100);
1787 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1788 DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA);
1789 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1790 DIF_COMP_FLT_CTRL, 0, 31,
1791 0x00000000);
1792 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1793 DIF_SRC_PHASE_INC, 0, 31,
1794 0x1befbf06);
1795 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1796 DIF_SRC_GAIN_CONTROL, 0, 31,
1797 0x000035e8);
1798 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1799 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1800 /* Save the Spec Inversion value */
1801 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1802 dif_misc_ctrl_value |= 0x3a023F11;
1803 } else if (standard & V4L2_STD_PAL_I) {
1804 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1805 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1806 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1807 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1808 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1809 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1810 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1811 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1812 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1813 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1814 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1815 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1816 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1817 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1818 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1819 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1820 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1821 DIF_AGC_IF_INT_CURRENT, 0, 31,
1822 0x26001700);
1823 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1824 DIF_AGC_RF_CURRENT, 0, 31,
1825 0x00002660);
1826 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1827 DIF_VIDEO_AGC_CTRL, 0, 31,
1828 0x72500800);
1829 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1830 DIF_VID_AUD_OVERRIDE, 0, 31,
1831 0x27000100);
1832 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1833 DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934);
1834 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1835 DIF_COMP_FLT_CTRL, 0, 31,
1836 0x00000000);
1837 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1838 DIF_SRC_PHASE_INC, 0, 31,
1839 0x1befbf06);
1840 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1841 DIF_SRC_GAIN_CONTROL, 0, 31,
1842 0x000035e8);
1843 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1844 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1845 /* Save the Spec Inversion value */
1846 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1847 dif_misc_ctrl_value |= 0x3a033F11;
1848 } else if (standard & V4L2_STD_PAL_M) {
1849 /* improved Low Frequency Phase Noise */
1850 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1851 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1852 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1853 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1854 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1855 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1856 0x26001700);
1857 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1858 0x00002660);
1859 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1860 0x72500800);
1861 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1862 0x27000100);
1863 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x012c405d);
1864 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1865 0x009f50c1);
1866 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1867 0x1befbf06);
1868 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1869 0x000035e8);
1870 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1871 0x00000000);
1872 /* Save the Spec Inversion value */
1873 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1874 dif_misc_ctrl_value |= 0x3A0A3F10;
1875 } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) {
1876 /* improved Low Frequency Phase Noise */
1877 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1878 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1879 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1880 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1881 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1882 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1883 0x26001700);
1884 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1885 0x00002660);
1886 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1887 0x72500800);
1888 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1889 0x27000100);
1890 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL,
1891 0x012c405d);
1892 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1893 0x009f50c1);
1894 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1895 0x1befbf06);
1896 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1897 0x000035e8);
1898 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1899 0x00000000);
1900 /* Save the Spec Inversion value */
1901 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1902 dif_misc_ctrl_value = 0x3A093F10;
1903 } else if (standard &
1904 (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G |
1905 V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) {
1906
1907 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1908 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1909 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1910 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1911 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1912 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1913 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1914 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1915 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1916 DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1917 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1918 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1919 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1920 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1921 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1922 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1923 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1924 DIF_AGC_IF_INT_CURRENT, 0, 31,
1925 0x26001700);
1926 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1927 DIF_AGC_RF_CURRENT, 0, 31,
1928 0x00002660);
1929 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1930 DIF_VID_AUD_OVERRIDE, 0, 31,
1931 0x27000100);
1932 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1933 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
1934 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1935 DIF_COMP_FLT_CTRL, 0, 31,
1936 0x00000000);
1937 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1938 DIF_SRC_PHASE_INC, 0, 31,
1939 0x1befbf06);
1940 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1941 DIF_SRC_GAIN_CONTROL, 0, 31,
1942 0x000035e8);
1943 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1944 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1945 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1946 DIF_VIDEO_AGC_CTRL, 0, 31,
1947 0xf4000000);
1948
1949 /* Save the Spec Inversion value */
1950 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1951 dif_misc_ctrl_value |= 0x3a023F11;
1952 } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) {
1953 /* Is it SECAM_L1? */
1954 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1955 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1956 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1957 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1958 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1959 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1960 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1961 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1962 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1963 DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1964 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1965 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1966 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1967 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1968 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1969 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1970 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1971 DIF_AGC_IF_INT_CURRENT, 0, 31,
1972 0x26001700);
1973 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1974 DIF_AGC_RF_CURRENT, 0, 31,
1975 0x00002660);
1976 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1977 DIF_VID_AUD_OVERRIDE, 0, 31,
1978 0x27000100);
1979 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1980 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
1981 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1982 DIF_COMP_FLT_CTRL, 0, 31,
1983 0x00000000);
1984 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1985 DIF_SRC_PHASE_INC, 0, 31,
1986 0x1befbf06);
1987 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1988 DIF_SRC_GAIN_CONTROL, 0, 31,
1989 0x000035e8);
1990 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1991 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1992 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1993 DIF_VIDEO_AGC_CTRL, 0, 31,
1994 0xf2560000);
1995
1996 /* Save the Spec Inversion value */
1997 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1998 dif_misc_ctrl_value |= 0x3a023F11;
1999
2000 } else if (standard & V4L2_STD_NTSC_M) {
2001 /* V4L2_STD_NTSC_M (75 IRE Setup) Or
2002 V4L2_STD_NTSC_M_JP (Japan, 0 IRE Setup) */
2003
2004 /* For NTSC the centre frequency of video coming out of
2005 sidewinder is around 7.1MHz or 3.6MHz depending on the
2006 spectral inversion. so for a non spectrally inverted channel
2007 the pll freq word is 0x03420c49
2008 */
2009
2010 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0x6503BC0C);
2011 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xBD038C85);
2012 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1DB4640A);
2013 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
2014 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C0380);
2015 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
2016 0x26001700);
2017 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
2018 0x00002660);
2019 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
2020 0x04000800);
2021 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
2022 0x27000100);
2023 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x01296e1f);
2024
2025 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
2026 0x009f50c1);
2027 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
2028 0x1befbf06);
2029 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
2030 0x000035e8);
2031
2032 status = vid_blk_write_word(dev, DIF_AGC_CTRL_IF, 0xC2262600);
2033 status = vid_blk_write_word(dev, DIF_AGC_CTRL_INT,
2034 0xC2262600);
2035 status = vid_blk_write_word(dev, DIF_AGC_CTRL_RF, 0xC2262600);
2036
2037 /* Save the Spec Inversion value */
2038 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
2039 dif_misc_ctrl_value |= 0x3a003F10;
2040 } else {
2041 /* default PAL BG */
2042 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2043 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
2044 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2045 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
2046 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2047 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
2048 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2049 DIF_PLL_CTRL3, 0, 31, 0x00008800);
2050 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2051 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
2052 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2053 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
2054 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2055 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
2056 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2057 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
2058 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2059 DIF_AGC_IF_INT_CURRENT, 0, 31,
2060 0x26001700);
2061 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2062 DIF_AGC_RF_CURRENT, 0, 31,
2063 0x00002660);
2064 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2065 DIF_VIDEO_AGC_CTRL, 0, 31,
2066 0x72500800);
2067 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2068 DIF_VID_AUD_OVERRIDE, 0, 31,
2069 0x27000100);
2070 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2071 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC);
2072 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2073 DIF_COMP_FLT_CTRL, 0, 31,
2074 0x00A653A8);
2075 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2076 DIF_SRC_PHASE_INC, 0, 31,
2077 0x1befbf06);
2078 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2079 DIF_SRC_GAIN_CONTROL, 0, 31,
2080 0x000035e8);
2081 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2082 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
2083 /* Save the Spec Inversion value */
2084 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
2085 dif_misc_ctrl_value |= 0x3a013F11;
2086 }
2087
2088 /* The AGC values should be the same for all standards,
2089 AUD_SRC_SEL[19] should always be disabled */
2090 dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL;
2091
2092 /* It is still possible to get Set Standard calls even when we
2093 are in FM mode.
2094 This is done to override the value for FM. */
2095 if (dev->active_mode == V4L2_TUNER_RADIO)
2096 dif_misc_ctrl_value = 0x7a080000;
2097
2098 /* Write the calculated value for misc ontrol register */
2099 status = vid_blk_write_word(dev, DIF_MISC_CTRL, dif_misc_ctrl_value);
2100
2101 return status;
2102 }
2103
2104 int cx231xx_tuner_pre_channel_change(struct cx231xx *dev)
2105 {
2106 int status = 0;
2107 u32 dwval;
2108
2109 /* Set the RF and IF k_agc values to 3 */
2110 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
2111 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
2112 dwval |= 0x33000000;
2113
2114 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
2115
2116 return status;
2117 }
2118
2119 int cx231xx_tuner_post_channel_change(struct cx231xx *dev)
2120 {
2121 int status = 0;
2122 u32 dwval;
2123 cx231xx_info("cx231xx_tuner_post_channel_change dev->tuner_type =0%d\n",
2124 dev->tuner_type);
2125 /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for
2126 * SECAM L/B/D standards */
2127 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
2128 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
2129
2130 if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B |
2131 V4L2_STD_SECAM_D)) {
2132 if (dev->tuner_type == TUNER_NXP_TDA18271) {
2133 dwval &= ~FLD_DIF_IF_REF;
2134 dwval |= 0x88000300;
2135 } else
2136 dwval |= 0x88000000;
2137 } else {
2138 if (dev->tuner_type == TUNER_NXP_TDA18271) {
2139 dwval &= ~FLD_DIF_IF_REF;
2140 dwval |= 0xCC000300;
2141 } else
2142 dwval |= 0x44000000;
2143 }
2144
2145 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
2146
2147 return status;
2148 }
2149
2150 /******************************************************************************
2151 * I 2 S - B L O C K C O N T R O L functions *
2152 ******************************************************************************/
2153 int cx231xx_i2s_blk_initialize(struct cx231xx *dev)
2154 {
2155 int status = 0;
2156 u32 value;
2157
2158 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2159 CH_PWR_CTRL1, 1, &value, 1);
2160 /* enables clock to delta-sigma and decimation filter */
2161 value |= 0x80;
2162 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2163 CH_PWR_CTRL1, 1, value, 1);
2164 /* power up all channel */
2165 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2166 CH_PWR_CTRL2, 1, 0x00, 1);
2167
2168 return status;
2169 }
2170
2171 int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev,
2172 enum AV_MODE avmode)
2173 {
2174 int status = 0;
2175 u32 value = 0;
2176
2177 if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) {
2178 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2179 CH_PWR_CTRL2, 1, &value, 1);
2180 value |= 0xfe;
2181 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2182 CH_PWR_CTRL2, 1, value, 1);
2183 } else {
2184 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2185 CH_PWR_CTRL2, 1, 0x00, 1);
2186 }
2187
2188 return status;
2189 }
2190
2191 /* set i2s_blk for audio input types */
2192 int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input)
2193 {
2194 int status = 0;
2195
2196 switch (audio_input) {
2197 case CX231XX_AMUX_LINE_IN:
2198 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2199 CH_PWR_CTRL2, 1, 0x00, 1);
2200 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2201 CH_PWR_CTRL1, 1, 0x80, 1);
2202 break;
2203 case CX231XX_AMUX_VIDEO:
2204 default:
2205 break;
2206 }
2207
2208 dev->ctl_ainput = audio_input;
2209
2210 return status;
2211 }
2212
2213 /******************************************************************************
2214 * P O W E R C O N T R O L functions *
2215 ******************************************************************************/
2216 int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode)
2217 {
2218 u8 value[4] = { 0, 0, 0, 0 };
2219 u32 tmp = 0;
2220 int status = 0;
2221
2222 if (dev->power_mode != mode)
2223 dev->power_mode = mode;
2224 else {
2225 cx231xx_info(" setPowerMode::mode = %d, No Change req.\n",
2226 mode);
2227 return 0;
2228 }
2229
2230 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
2231 4);
2232 if (status < 0)
2233 return status;
2234
2235 tmp = *((u32 *) value);
2236
2237 switch (mode) {
2238 case POLARIS_AVMODE_ENXTERNAL_AV:
2239
2240 tmp &= (~PWR_MODE_MASK);
2241
2242 tmp |= PWR_AV_EN;
2243 value[0] = (u8) tmp;
2244 value[1] = (u8) (tmp >> 8);
2245 value[2] = (u8) (tmp >> 16);
2246 value[3] = (u8) (tmp >> 24);
2247 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2248 PWR_CTL_EN, value, 4);
2249 msleep(PWR_SLEEP_INTERVAL);
2250
2251 tmp |= PWR_ISO_EN;
2252 value[0] = (u8) tmp;
2253 value[1] = (u8) (tmp >> 8);
2254 value[2] = (u8) (tmp >> 16);
2255 value[3] = (u8) (tmp >> 24);
2256 status =
2257 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
2258 value, 4);
2259 msleep(PWR_SLEEP_INTERVAL);
2260
2261 tmp |= POLARIS_AVMODE_ENXTERNAL_AV;
2262 value[0] = (u8) tmp;
2263 value[1] = (u8) (tmp >> 8);
2264 value[2] = (u8) (tmp >> 16);
2265 value[3] = (u8) (tmp >> 24);
2266 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2267 PWR_CTL_EN, value, 4);
2268
2269 /* reset state of xceive tuner */
2270 dev->xc_fw_load_done = 0;
2271 break;
2272
2273 case POLARIS_AVMODE_ANALOGT_TV:
2274
2275 tmp |= PWR_DEMOD_EN;
2276 tmp |= (I2C_DEMOD_EN);
2277 value[0] = (u8) tmp;
2278 value[1] = (u8) (tmp >> 8);
2279 value[2] = (u8) (tmp >> 16);
2280 value[3] = (u8) (tmp >> 24);
2281 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2282 PWR_CTL_EN, value, 4);
2283 msleep(PWR_SLEEP_INTERVAL);
2284
2285 if (!(tmp & PWR_TUNER_EN)) {
2286 tmp |= (PWR_TUNER_EN);
2287 value[0] = (u8) tmp;
2288 value[1] = (u8) (tmp >> 8);
2289 value[2] = (u8) (tmp >> 16);
2290 value[3] = (u8) (tmp >> 24);
2291 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2292 PWR_CTL_EN, value, 4);
2293 msleep(PWR_SLEEP_INTERVAL);
2294 }
2295
2296 if (!(tmp & PWR_AV_EN)) {
2297 tmp |= PWR_AV_EN;
2298 value[0] = (u8) tmp;
2299 value[1] = (u8) (tmp >> 8);
2300 value[2] = (u8) (tmp >> 16);
2301 value[3] = (u8) (tmp >> 24);
2302 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2303 PWR_CTL_EN, value, 4);
2304 msleep(PWR_SLEEP_INTERVAL);
2305 }
2306 if (!(tmp & PWR_ISO_EN)) {
2307 tmp |= PWR_ISO_EN;
2308 value[0] = (u8) tmp;
2309 value[1] = (u8) (tmp >> 8);
2310 value[2] = (u8) (tmp >> 16);
2311 value[3] = (u8) (tmp >> 24);
2312 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2313 PWR_CTL_EN, value, 4);
2314 msleep(PWR_SLEEP_INTERVAL);
2315 }
2316
2317 if (!(tmp & POLARIS_AVMODE_ANALOGT_TV)) {
2318 tmp |= POLARIS_AVMODE_ANALOGT_TV;
2319 value[0] = (u8) tmp;
2320 value[1] = (u8) (tmp >> 8);
2321 value[2] = (u8) (tmp >> 16);
2322 value[3] = (u8) (tmp >> 24);
2323 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2324 PWR_CTL_EN, value, 4);
2325 msleep(PWR_SLEEP_INTERVAL);
2326 }
2327
2328 if (dev->board.tuner_type != TUNER_ABSENT) {
2329 /* Enable tuner */
2330 cx231xx_enable_i2c_port_3(dev, true);
2331
2332 /* reset the Tuner */
2333 if (dev->board.tuner_gpio)
2334 cx231xx_gpio_set(dev, dev->board.tuner_gpio);
2335
2336 if (dev->cx231xx_reset_analog_tuner)
2337 dev->cx231xx_reset_analog_tuner(dev);
2338 }
2339
2340 break;
2341
2342 case POLARIS_AVMODE_DIGITAL:
2343 if (!(tmp & PWR_TUNER_EN)) {
2344 tmp |= (PWR_TUNER_EN);
2345 value[0] = (u8) tmp;
2346 value[1] = (u8) (tmp >> 8);
2347 value[2] = (u8) (tmp >> 16);
2348 value[3] = (u8) (tmp >> 24);
2349 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2350 PWR_CTL_EN, value, 4);
2351 msleep(PWR_SLEEP_INTERVAL);
2352 }
2353 if (!(tmp & PWR_AV_EN)) {
2354 tmp |= PWR_AV_EN;
2355 value[0] = (u8) tmp;
2356 value[1] = (u8) (tmp >> 8);
2357 value[2] = (u8) (tmp >> 16);
2358 value[3] = (u8) (tmp >> 24);
2359 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2360 PWR_CTL_EN, value, 4);
2361 msleep(PWR_SLEEP_INTERVAL);
2362 }
2363 if (!(tmp & PWR_ISO_EN)) {
2364 tmp |= PWR_ISO_EN;
2365 value[0] = (u8) tmp;
2366 value[1] = (u8) (tmp >> 8);
2367 value[2] = (u8) (tmp >> 16);
2368 value[3] = (u8) (tmp >> 24);
2369 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2370 PWR_CTL_EN, value, 4);
2371 msleep(PWR_SLEEP_INTERVAL);
2372 }
2373
2374 tmp &= (~PWR_AV_MODE);
2375 tmp |= POLARIS_AVMODE_DIGITAL | I2C_DEMOD_EN;
2376 value[0] = (u8) tmp;
2377 value[1] = (u8) (tmp >> 8);
2378 value[2] = (u8) (tmp >> 16);
2379 value[3] = (u8) (tmp >> 24);
2380 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2381 PWR_CTL_EN, value, 4);
2382 msleep(PWR_SLEEP_INTERVAL);
2383
2384 if (!(tmp & PWR_DEMOD_EN)) {
2385 tmp |= PWR_DEMOD_EN;
2386 value[0] = (u8) tmp;
2387 value[1] = (u8) (tmp >> 8);
2388 value[2] = (u8) (tmp >> 16);
2389 value[3] = (u8) (tmp >> 24);
2390 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2391 PWR_CTL_EN, value, 4);
2392 msleep(PWR_SLEEP_INTERVAL);
2393 }
2394
2395 if (dev->board.tuner_type != TUNER_ABSENT) {
2396 /*
2397 * Enable tuner
2398 * Hauppauge Exeter seems to need to do something different!
2399 */
2400 if (dev->model == CX231XX_BOARD_HAUPPAUGE_EXETER)
2401 cx231xx_enable_i2c_port_3(dev, false);
2402 else
2403 cx231xx_enable_i2c_port_3(dev, true);
2404
2405 /* reset the Tuner */
2406 if (dev->board.tuner_gpio)
2407 cx231xx_gpio_set(dev, dev->board.tuner_gpio);
2408
2409 if (dev->cx231xx_reset_analog_tuner)
2410 dev->cx231xx_reset_analog_tuner(dev);
2411 }
2412 break;
2413
2414 default:
2415 break;
2416 }
2417
2418 msleep(PWR_SLEEP_INTERVAL);
2419
2420 /* For power saving, only enable Pwr_resetout_n
2421 when digital TV is selected. */
2422 if (mode == POLARIS_AVMODE_DIGITAL) {
2423 tmp |= PWR_RESETOUT_EN;
2424 value[0] = (u8) tmp;
2425 value[1] = (u8) (tmp >> 8);
2426 value[2] = (u8) (tmp >> 16);
2427 value[3] = (u8) (tmp >> 24);
2428 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2429 PWR_CTL_EN, value, 4);
2430 msleep(PWR_SLEEP_INTERVAL);
2431 }
2432
2433 /* update power control for afe */
2434 status = cx231xx_afe_update_power_control(dev, mode);
2435
2436 /* update power control for i2s_blk */
2437 status = cx231xx_i2s_blk_update_power_control(dev, mode);
2438
2439 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
2440 4);
2441
2442 return status;
2443 }
2444
2445 int cx231xx_power_suspend(struct cx231xx *dev)
2446 {
2447 u8 value[4] = { 0, 0, 0, 0 };
2448 u32 tmp = 0;
2449 int status = 0;
2450
2451 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
2452 value, 4);
2453 if (status > 0)
2454 return status;
2455
2456 tmp = *((u32 *) value);
2457 tmp &= (~PWR_MODE_MASK);
2458
2459 value[0] = (u8) tmp;
2460 value[1] = (u8) (tmp >> 8);
2461 value[2] = (u8) (tmp >> 16);
2462 value[3] = (u8) (tmp >> 24);
2463 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
2464 value, 4);
2465
2466 return status;
2467 }
2468
2469 /******************************************************************************
2470 * S T R E A M C O N T R O L functions *
2471 ******************************************************************************/
2472 int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask)
2473 {
2474 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
2475 u32 tmp = 0;
2476 int status = 0;
2477
2478 cx231xx_info("cx231xx_start_stream():: ep_mask = %x\n", ep_mask);
2479 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
2480 value, 4);
2481 if (status < 0)
2482 return status;
2483
2484 tmp = *((u32 *) value);
2485 tmp |= ep_mask;
2486 value[0] = (u8) tmp;
2487 value[1] = (u8) (tmp >> 8);
2488 value[2] = (u8) (tmp >> 16);
2489 value[3] = (u8) (tmp >> 24);
2490
2491 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
2492 value, 4);
2493
2494 return status;
2495 }
2496
2497 int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask)
2498 {
2499 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
2500 u32 tmp = 0;
2501 int status = 0;
2502
2503 cx231xx_info("cx231xx_stop_stream():: ep_mask = %x\n", ep_mask);
2504 status =
2505 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4);
2506 if (status < 0)
2507 return status;
2508
2509 tmp = *((u32 *) value);
2510 tmp &= (~ep_mask);
2511 value[0] = (u8) tmp;
2512 value[1] = (u8) (tmp >> 8);
2513 value[2] = (u8) (tmp >> 16);
2514 value[3] = (u8) (tmp >> 24);
2515
2516 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
2517 value, 4);
2518
2519 return status;
2520 }
2521
2522 int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type)
2523 {
2524 int status = 0;
2525 u32 value = 0;
2526 u8 val[4] = { 0, 0, 0, 0 };
2527
2528 if (dev->udev->speed == USB_SPEED_HIGH) {
2529 switch (media_type) {
2530 case 81: /* audio */
2531 cx231xx_info("%s: Audio enter HANC\n", __func__);
2532 status =
2533 cx231xx_mode_register(dev, TS_MODE_REG, 0x9300);
2534 break;
2535
2536 case 2: /* vbi */
2537 cx231xx_info("%s: set vanc registers\n", __func__);
2538 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300);
2539 break;
2540
2541 case 3: /* sliced cc */
2542 cx231xx_info("%s: set hanc registers\n", __func__);
2543 status =
2544 cx231xx_mode_register(dev, TS_MODE_REG, 0x1300);
2545 break;
2546
2547 case 0: /* video */
2548 cx231xx_info("%s: set video registers\n", __func__);
2549 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2550 break;
2551
2552 case 4: /* ts1 */
2553 cx231xx_info("%s: set ts1 registers", __func__);
2554
2555 if (dev->board.has_417) {
2556 cx231xx_info(" MPEG\n");
2557 value &= 0xFFFFFFFC;
2558 value |= 0x3;
2559
2560 status = cx231xx_mode_register(dev, TS_MODE_REG, value);
2561
2562 val[0] = 0x04;
2563 val[1] = 0xA3;
2564 val[2] = 0x3B;
2565 val[3] = 0x00;
2566 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2567 TS1_CFG_REG, val, 4);
2568
2569 val[0] = 0x00;
2570 val[1] = 0x08;
2571 val[2] = 0x00;
2572 val[3] = 0x08;
2573 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2574 TS1_LENGTH_REG, val, 4);
2575
2576 } else {
2577 cx231xx_info(" BDA\n");
2578 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2579 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x010);
2580 }
2581 break;
2582
2583 case 6: /* ts1 parallel mode */
2584 cx231xx_info("%s: set ts1 parallel mode registers\n",
2585 __func__);
2586 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2587 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400);
2588 break;
2589 }
2590 } else {
2591 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2592 }
2593
2594 return status;
2595 }
2596
2597 int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type)
2598 {
2599 int rc = -1;
2600 u32 ep_mask = -1;
2601 struct pcb_config *pcb_config;
2602
2603 /* get EP for media type */
2604 pcb_config = (struct pcb_config *)&dev->current_pcb_config;
2605
2606 if (pcb_config->config_num == 1) {
2607 switch (media_type) {
2608 case 0: /* Video */
2609 ep_mask = ENABLE_EP4; /* ep4 [00:1000] */
2610 break;
2611 case 1: /* Audio */
2612 ep_mask = ENABLE_EP3; /* ep3 [00:0100] */
2613 break;
2614 case 2: /* Vbi */
2615 ep_mask = ENABLE_EP5; /* ep5 [01:0000] */
2616 break;
2617 case 3: /* Sliced_cc */
2618 ep_mask = ENABLE_EP6; /* ep6 [10:0000] */
2619 break;
2620 case 4: /* ts1 */
2621 case 6: /* ts1 parallel mode */
2622 ep_mask = ENABLE_EP1; /* ep1 [00:0001] */
2623 break;
2624 case 5: /* ts2 */
2625 ep_mask = ENABLE_EP2; /* ep2 [00:0010] */
2626 break;
2627 }
2628
2629 } else if (pcb_config->config_num > 1) {
2630 switch (media_type) {
2631 case 0: /* Video */
2632 ep_mask = ENABLE_EP4; /* ep4 [00:1000] */
2633 break;
2634 case 1: /* Audio */
2635 ep_mask = ENABLE_EP3; /* ep3 [00:0100] */
2636 break;
2637 case 2: /* Vbi */
2638 ep_mask = ENABLE_EP5; /* ep5 [01:0000] */
2639 break;
2640 case 3: /* Sliced_cc */
2641 ep_mask = ENABLE_EP6; /* ep6 [10:0000] */
2642 break;
2643 case 4: /* ts1 */
2644 case 6: /* ts1 parallel mode */
2645 ep_mask = ENABLE_EP1; /* ep1 [00:0001] */
2646 break;
2647 case 5: /* ts2 */
2648 ep_mask = ENABLE_EP2; /* ep2 [00:0010] */
2649 break;
2650 }
2651
2652 }
2653
2654 if (start) {
2655 rc = cx231xx_initialize_stream_xfer(dev, media_type);
2656
2657 if (rc < 0)
2658 return rc;
2659
2660 /* enable video capture */
2661 if (ep_mask > 0)
2662 rc = cx231xx_start_stream(dev, ep_mask);
2663 } else {
2664 /* disable video capture */
2665 if (ep_mask > 0)
2666 rc = cx231xx_stop_stream(dev, ep_mask);
2667 }
2668
2669 if (dev->mode == CX231XX_ANALOG_MODE)
2670 ;/* do any in Analog mode */
2671 else
2672 ;/* do any in digital mode */
2673
2674 return rc;
2675 }
2676 EXPORT_SYMBOL_GPL(cx231xx_capture_start);
2677
2678 /*****************************************************************************
2679 * G P I O B I T control functions *
2680 ******************************************************************************/
2681 int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val)
2682 {
2683 int status = 0;
2684
2685 status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 0);
2686
2687 return status;
2688 }
2689
2690 int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val)
2691 {
2692 int status = 0;
2693
2694 status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 1);
2695
2696 return status;
2697 }
2698
2699 /*
2700 * cx231xx_set_gpio_direction
2701 * Sets the direction of the GPIO pin to input or output
2702 *
2703 * Parameters :
2704 * pin_number : The GPIO Pin number to program the direction for
2705 * from 0 to 31
2706 * pin_value : The Direction of the GPIO Pin under reference.
2707 * 0 = Input direction
2708 * 1 = Output direction
2709 */
2710 int cx231xx_set_gpio_direction(struct cx231xx *dev,
2711 int pin_number, int pin_value)
2712 {
2713 int status = 0;
2714 u32 value = 0;
2715
2716 /* Check for valid pin_number - if 32 , bail out */
2717 if (pin_number >= 32)
2718 return -EINVAL;
2719
2720 /* input */
2721 if (pin_value == 0)
2722 value = dev->gpio_dir & (~(1 << pin_number)); /* clear */
2723 else
2724 value = dev->gpio_dir | (1 << pin_number);
2725
2726 status = cx231xx_set_gpio_bit(dev, value, (u8 *) &dev->gpio_val);
2727
2728 /* cache the value for future */
2729 dev->gpio_dir = value;
2730
2731 return status;
2732 }
2733
2734 /*
2735 * cx231xx_set_gpio_value
2736 * Sets the value of the GPIO pin to Logic high or low. The Pin under
2737 * reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!!
2738 *
2739 * Parameters :
2740 * pin_number : The GPIO Pin number to program the direction for
2741 * pin_value : The value of the GPIO Pin under reference.
2742 * 0 = set it to 0
2743 * 1 = set it to 1
2744 */
2745 int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value)
2746 {
2747 int status = 0;
2748 u32 value = 0;
2749
2750 /* Check for valid pin_number - if 0xFF , bail out */
2751 if (pin_number >= 32)
2752 return -EINVAL;
2753
2754 /* first do a sanity check - if the Pin is not output, make it output */
2755 if ((dev->gpio_dir & (1 << pin_number)) == 0x00) {
2756 /* It was in input mode */
2757 value = dev->gpio_dir | (1 << pin_number);
2758 dev->gpio_dir = value;
2759 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2760 (u8 *) &dev->gpio_val);
2761 value = 0;
2762 }
2763
2764 if (pin_value == 0)
2765 value = dev->gpio_val & (~(1 << pin_number));
2766 else
2767 value = dev->gpio_val | (1 << pin_number);
2768
2769 /* store the value */
2770 dev->gpio_val = value;
2771
2772 /* toggle bit0 of GP_IO */
2773 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2774
2775 return status;
2776 }
2777
2778 /*****************************************************************************
2779 * G P I O I2C related functions *
2780 ******************************************************************************/
2781 int cx231xx_gpio_i2c_start(struct cx231xx *dev)
2782 {
2783 int status = 0;
2784
2785 /* set SCL to output 1 ; set SDA to output 1 */
2786 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2787 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2788 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2789 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2790
2791 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2792 if (status < 0)
2793 return -EINVAL;
2794
2795 /* set SCL to output 1; set SDA to output 0 */
2796 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2797 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2798
2799 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2800 if (status < 0)
2801 return -EINVAL;
2802
2803 /* set SCL to output 0; set SDA to output 0 */
2804 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2805 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2806
2807 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2808 if (status < 0)
2809 return -EINVAL;
2810
2811 return status;
2812 }
2813
2814 int cx231xx_gpio_i2c_end(struct cx231xx *dev)
2815 {
2816 int status = 0;
2817
2818 /* set SCL to output 0; set SDA to output 0 */
2819 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2820 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2821
2822 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2823 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2824
2825 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2826 if (status < 0)
2827 return -EINVAL;
2828
2829 /* set SCL to output 1; set SDA to output 0 */
2830 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2831 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2832
2833 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2834 if (status < 0)
2835 return -EINVAL;
2836
2837 /* set SCL to input ,release SCL cable control
2838 set SDA to input ,release SDA cable control */
2839 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2840 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2841
2842 status =
2843 cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2844 if (status < 0)
2845 return -EINVAL;
2846
2847 return status;
2848 }
2849
2850 int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data)
2851 {
2852 int status = 0;
2853 u8 i;
2854
2855 /* set SCL to output ; set SDA to output */
2856 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2857 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2858
2859 for (i = 0; i < 8; i++) {
2860 if (((data << i) & 0x80) == 0) {
2861 /* set SCL to output 0; set SDA to output 0 */
2862 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2863 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2864 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2865 (u8 *)&dev->gpio_val);
2866
2867 /* set SCL to output 1; set SDA to output 0 */
2868 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2869 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2870 (u8 *)&dev->gpio_val);
2871
2872 /* set SCL to output 0; set SDA to output 0 */
2873 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2874 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2875 (u8 *)&dev->gpio_val);
2876 } else {
2877 /* set SCL to output 0; set SDA to output 1 */
2878 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2879 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2880 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2881 (u8 *)&dev->gpio_val);
2882
2883 /* set SCL to output 1; set SDA to output 1 */
2884 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2885 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2886 (u8 *)&dev->gpio_val);
2887
2888 /* set SCL to output 0; set SDA to output 1 */
2889 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2890 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2891 (u8 *)&dev->gpio_val);
2892 }
2893 }
2894 return status;
2895 }
2896
2897 int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 *buf)
2898 {
2899 u8 value = 0;
2900 int status = 0;
2901 u32 gpio_logic_value = 0;
2902 u8 i;
2903
2904 /* read byte */
2905 for (i = 0; i < 8; i++) { /* send write I2c addr */
2906
2907 /* set SCL to output 0; set SDA to input */
2908 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2909 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2910 (u8 *)&dev->gpio_val);
2911
2912 /* set SCL to output 1; set SDA to input */
2913 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2914 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2915 (u8 *)&dev->gpio_val);
2916
2917 /* get SDA data bit */
2918 gpio_logic_value = dev->gpio_val;
2919 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2920 (u8 *)&dev->gpio_val);
2921 if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0)
2922 value |= (1 << (8 - i - 1));
2923
2924 dev->gpio_val = gpio_logic_value;
2925 }
2926
2927 /* set SCL to output 0,finish the read latest SCL signal.
2928 !!!set SDA to input, never to modify SDA direction at
2929 the same times */
2930 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2931 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2932
2933 /* store the value */
2934 *buf = value & 0xff;
2935
2936 return status;
2937 }
2938
2939 int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev)
2940 {
2941 int status = 0;
2942 u32 gpio_logic_value = 0;
2943 int nCnt = 10;
2944 int nInit = nCnt;
2945
2946 /* clock stretch; set SCL to input; set SDA to input;
2947 get SCL value till SCL = 1 */
2948 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2949 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2950
2951 gpio_logic_value = dev->gpio_val;
2952 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2953
2954 do {
2955 msleep(2);
2956 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2957 (u8 *)&dev->gpio_val);
2958 nCnt--;
2959 } while (((dev->gpio_val &
2960 (1 << dev->board.tuner_scl_gpio)) == 0) &&
2961 (nCnt > 0));
2962
2963 if (nCnt == 0)
2964 cx231xx_info("No ACK after %d msec -GPIO I2C failed!",
2965 nInit * 10);
2966
2967 /*
2968 * readAck
2969 * through clock stretch, slave has given a SCL signal,
2970 * so the SDA data can be directly read.
2971 */
2972 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2973
2974 if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) {
2975 dev->gpio_val = gpio_logic_value;
2976 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2977 status = 0;
2978 } else {
2979 dev->gpio_val = gpio_logic_value;
2980 dev->gpio_val |= (1 << dev->board.tuner_sda_gpio);
2981 }
2982
2983 /* read SDA end, set the SCL to output 0, after this operation,
2984 SDA direction can be changed. */
2985 dev->gpio_val = gpio_logic_value;
2986 dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio);
2987 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2988 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2989
2990 return status;
2991 }
2992
2993 int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev)
2994 {
2995 int status = 0;
2996
2997 /* set SDA to ouput */
2998 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2999 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3000
3001 /* set SCL = 0 (output); set SDA = 0 (output) */
3002 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
3003 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
3004 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3005
3006 /* set SCL = 1 (output); set SDA = 0 (output) */
3007 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
3008 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3009
3010 /* set SCL = 0 (output); set SDA = 0 (output) */
3011 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
3012 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3013
3014 /* set SDA to input,and then the slave will read data from SDA. */
3015 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
3016 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3017
3018 return status;
3019 }
3020
3021 int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev)
3022 {
3023 int status = 0;
3024
3025 /* set scl to output ; set sda to input */
3026 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
3027 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
3028 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3029
3030 /* set scl to output 0; set sda to input */
3031 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
3032 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3033
3034 /* set scl to output 1; set sda to input */
3035 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
3036 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3037
3038 return status;
3039 }
3040
3041 /*****************************************************************************
3042 * G P I O I2C related functions *
3043 ******************************************************************************/
3044 /* cx231xx_gpio_i2c_read
3045 * Function to read data from gpio based I2C interface
3046 */
3047 int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len)
3048 {
3049 int status = 0;
3050 int i = 0;
3051
3052 /* get the lock */
3053 mutex_lock(&dev->gpio_i2c_lock);
3054
3055 /* start */
3056 status = cx231xx_gpio_i2c_start(dev);
3057
3058 /* write dev_addr */
3059 status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) + 1);
3060
3061 /* readAck */
3062 status = cx231xx_gpio_i2c_read_ack(dev);
3063
3064 /* read data */
3065 for (i = 0; i < len; i++) {
3066 /* read data */
3067 buf[i] = 0;
3068 status = cx231xx_gpio_i2c_read_byte(dev, &buf[i]);
3069
3070 if ((i + 1) != len) {
3071 /* only do write ack if we more length */
3072 status = cx231xx_gpio_i2c_write_ack(dev);
3073 }
3074 }
3075
3076 /* write NAK - inform reads are complete */
3077 status = cx231xx_gpio_i2c_write_nak(dev);
3078
3079 /* write end */
3080 status = cx231xx_gpio_i2c_end(dev);
3081
3082 /* release the lock */
3083 mutex_unlock(&dev->gpio_i2c_lock);
3084
3085 return status;
3086 }
3087
3088 /* cx231xx_gpio_i2c_write
3089 * Function to write data to gpio based I2C interface
3090 */
3091 int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len)
3092 {
3093 int status = 0;
3094 int i = 0;
3095
3096 /* get the lock */
3097 mutex_lock(&dev->gpio_i2c_lock);
3098
3099 /* start */
3100 status = cx231xx_gpio_i2c_start(dev);
3101
3102 /* write dev_addr */
3103 status = cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1);
3104
3105 /* read Ack */
3106 status = cx231xx_gpio_i2c_read_ack(dev);
3107
3108 for (i = 0; i < len; i++) {
3109 /* Write data */
3110 status = cx231xx_gpio_i2c_write_byte(dev, buf[i]);
3111
3112 /* read Ack */
3113 status = cx231xx_gpio_i2c_read_ack(dev);
3114 }
3115
3116 /* write End */
3117 status = cx231xx_gpio_i2c_end(dev);
3118
3119 /* release the lock */
3120 mutex_unlock(&dev->gpio_i2c_lock);
3121
3122 return 0;
3123 }
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