2 * Driver for the Conexant CX2584x Audio/Video decoder chip and related cores
4 * Integrated Consumer Infrared Controller
6 * Copyright (C) 2010 Andy Walls <awalls@md.metrocast.net>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
24 #include <linux/slab.h>
25 #include <linux/kfifo.h>
26 #include <linux/module.h>
27 #include <media/cx25840.h>
28 #include <media/rc-core.h>
30 #include "cx25840-core.h"
32 static unsigned int ir_debug
;
33 module_param(ir_debug
, int, 0644);
34 MODULE_PARM_DESC(ir_debug
, "enable integrated IR debug messages");
36 #define CX25840_IR_REG_BASE 0x200
38 #define CX25840_IR_CNTRL_REG 0x200
39 #define CNTRL_WIN_3_3 0x00000000
40 #define CNTRL_WIN_4_3 0x00000001
41 #define CNTRL_WIN_3_4 0x00000002
42 #define CNTRL_WIN_4_4 0x00000003
43 #define CNTRL_WIN 0x00000003
44 #define CNTRL_EDG_NONE 0x00000000
45 #define CNTRL_EDG_FALL 0x00000004
46 #define CNTRL_EDG_RISE 0x00000008
47 #define CNTRL_EDG_BOTH 0x0000000C
48 #define CNTRL_EDG 0x0000000C
49 #define CNTRL_DMD 0x00000010
50 #define CNTRL_MOD 0x00000020
51 #define CNTRL_RFE 0x00000040
52 #define CNTRL_TFE 0x00000080
53 #define CNTRL_RXE 0x00000100
54 #define CNTRL_TXE 0x00000200
55 #define CNTRL_RIC 0x00000400
56 #define CNTRL_TIC 0x00000800
57 #define CNTRL_CPL 0x00001000
58 #define CNTRL_LBM 0x00002000
59 #define CNTRL_R 0x00004000
61 #define CX25840_IR_TXCLK_REG 0x204
62 #define TXCLK_TCD 0x0000FFFF
64 #define CX25840_IR_RXCLK_REG 0x208
65 #define RXCLK_RCD 0x0000FFFF
67 #define CX25840_IR_CDUTY_REG 0x20C
68 #define CDUTY_CDC 0x0000000F
70 #define CX25840_IR_STATS_REG 0x210
71 #define STATS_RTO 0x00000001
72 #define STATS_ROR 0x00000002
73 #define STATS_RBY 0x00000004
74 #define STATS_TBY 0x00000008
75 #define STATS_RSR 0x00000010
76 #define STATS_TSR 0x00000020
78 #define CX25840_IR_IRQEN_REG 0x214
79 #define IRQEN_RTE 0x00000001
80 #define IRQEN_ROE 0x00000002
81 #define IRQEN_RSE 0x00000010
82 #define IRQEN_TSE 0x00000020
83 #define IRQEN_MSK 0x00000033
85 #define CX25840_IR_FILTR_REG 0x218
86 #define FILTR_LPF 0x0000FFFF
88 #define CX25840_IR_FIFO_REG 0x23C
89 #define FIFO_RXTX 0x0000FFFF
90 #define FIFO_RXTX_LVL 0x00010000
91 #define FIFO_RXTX_RTO 0x0001FFFF
92 #define FIFO_RX_NDV 0x00020000
93 #define FIFO_RX_DEPTH 8
94 #define FIFO_TX_DEPTH 8
96 #define CX25840_VIDCLK_FREQ 108000000 /* 108 MHz, BT.656 */
97 #define CX25840_IR_REFCLK_FREQ (CX25840_VIDCLK_FREQ / 2)
100 * We use this union internally for convenience, but callers to tx_write
101 * and rx_read will be expecting records of type struct ir_raw_event.
102 * Always ensure the size of this union is dictated by struct ir_raw_event.
104 union cx25840_ir_fifo_rec
{
106 struct ir_raw_event ir_core_data
;
109 #define CX25840_IR_RX_KFIFO_SIZE (256 * sizeof(union cx25840_ir_fifo_rec))
110 #define CX25840_IR_TX_KFIFO_SIZE (256 * sizeof(union cx25840_ir_fifo_rec))
112 struct cx25840_ir_state
{
113 struct i2c_client
*c
;
115 struct v4l2_subdev_ir_parameters rx_params
;
116 struct mutex rx_params_lock
; /* protects Rx parameter settings cache */
117 atomic_t rxclk_divider
;
120 struct kfifo rx_kfifo
;
121 spinlock_t rx_kfifo_lock
; /* protect Rx data kfifo */
123 struct v4l2_subdev_ir_parameters tx_params
;
124 struct mutex tx_params_lock
; /* protects Tx parameter settings cache */
125 atomic_t txclk_divider
;
128 static inline struct cx25840_ir_state
*to_ir_state(struct v4l2_subdev
*sd
)
130 struct cx25840_state
*state
= to_state(sd
);
131 return state
? state
->ir_state
: NULL
;
136 * Rx and Tx Clock Divider register computations
138 * Note the largest clock divider value of 0xffff corresponds to:
139 * (0xffff + 1) * 1000 / 108/2 MHz = 1,213,629.629... ns
140 * which fits in 21 bits, so we'll use unsigned int for time arguments.
142 static inline u16
count_to_clock_divider(unsigned int d
)
144 if (d
> RXCLK_RCD
+ 1)
153 static inline u16
ns_to_clock_divider(unsigned int ns
)
155 return count_to_clock_divider(
156 DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ
/ 1000000 * ns
, 1000));
159 static inline unsigned int clock_divider_to_ns(unsigned int divider
)
161 /* Period of the Rx or Tx clock in ns */
162 return DIV_ROUND_CLOSEST((divider
+ 1) * 1000,
163 CX25840_IR_REFCLK_FREQ
/ 1000000);
166 static inline u16
carrier_freq_to_clock_divider(unsigned int freq
)
168 return count_to_clock_divider(
169 DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ
, freq
* 16));
172 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider
)
174 return DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ
, (divider
+ 1) * 16);
177 static inline u16
freq_to_clock_divider(unsigned int freq
,
178 unsigned int rollovers
)
180 return count_to_clock_divider(
181 DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ
, freq
* rollovers
));
184 static inline unsigned int clock_divider_to_freq(unsigned int divider
,
185 unsigned int rollovers
)
187 return DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ
,
188 (divider
+ 1) * rollovers
);
192 * Low Pass Filter register calculations
194 * Note the largest count value of 0xffff corresponds to:
195 * 0xffff * 1000 / 108/2 MHz = 1,213,611.11... ns
196 * which fits in 21 bits, so we'll use unsigned int for time arguments.
198 static inline u16
count_to_lpf_count(unsigned int d
)
207 static inline u16
ns_to_lpf_count(unsigned int ns
)
209 return count_to_lpf_count(
210 DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ
/ 1000000 * ns
, 1000));
213 static inline unsigned int lpf_count_to_ns(unsigned int count
)
215 /* Duration of the Low Pass Filter rejection window in ns */
216 return DIV_ROUND_CLOSEST(count
* 1000,
217 CX25840_IR_REFCLK_FREQ
/ 1000000);
220 static inline unsigned int lpf_count_to_us(unsigned int count
)
222 /* Duration of the Low Pass Filter rejection window in us */
223 return DIV_ROUND_CLOSEST(count
, CX25840_IR_REFCLK_FREQ
/ 1000000);
227 * FIFO register pulse width count compuations
229 static u32
clock_divider_to_resolution(u16 divider
)
232 * Resolution is the duration of 1 tick of the readable portion of
233 * of the pulse width counter as read from the FIFO. The two lsb's are
234 * not readable, hence the << 2. This function returns ns.
236 return DIV_ROUND_CLOSEST((1 << 2) * ((u32
) divider
+ 1) * 1000,
237 CX25840_IR_REFCLK_FREQ
/ 1000000);
240 static u64
pulse_width_count_to_ns(u16 count
, u16 divider
)
246 * The 2 lsb's of the pulse width timer count are not readable, hence
247 * the (count << 2) | 0x3
249 n
= (((u64
) count
<< 2) | 0x3) * (divider
+ 1) * 1000; /* millicycles */
250 rem
= do_div(n
, CX25840_IR_REFCLK_FREQ
/ 1000000); /* / MHz => ns */
251 if (rem
>= CX25840_IR_REFCLK_FREQ
/ 1000000 / 2)
257 /* Keep as we will need this for Transmit functionality */
258 static u16
ns_to_pulse_width_count(u32 ns
, u16 divider
)
265 * The 2 lsb's of the pulse width timer count are not accessible, hence
268 n
= ((u64
) ns
) * CX25840_IR_REFCLK_FREQ
/ 1000000; /* millicycles */
269 d
= (1 << 2) * ((u32
) divider
+ 1) * 1000; /* millicycles/count */
282 static unsigned int pulse_width_count_to_us(u16 count
, u16 divider
)
288 * The 2 lsb's of the pulse width timer count are not readable, hence
289 * the (count << 2) | 0x3
291 n
= (((u64
) count
<< 2) | 0x3) * (divider
+ 1); /* cycles */
292 rem
= do_div(n
, CX25840_IR_REFCLK_FREQ
/ 1000000); /* / MHz => us */
293 if (rem
>= CX25840_IR_REFCLK_FREQ
/ 1000000 / 2)
295 return (unsigned int) n
;
299 * Pulse Clocks computations: Combined Pulse Width Count & Rx Clock Counts
301 * The total pulse clock count is an 18 bit pulse width timer count as the most
302 * significant part and (up to) 16 bit clock divider count as a modulus.
303 * When the Rx clock divider ticks down to 0, it increments the 18 bit pulse
304 * width timer count's least significant bit.
306 static u64
ns_to_pulse_clocks(u32 ns
)
310 clocks
= CX25840_IR_REFCLK_FREQ
/ 1000000 * (u64
) ns
; /* millicycles */
311 rem
= do_div(clocks
, 1000); /* /1000 = cycles */
317 static u16
pulse_clocks_to_clock_divider(u64 count
)
321 rem
= do_div(count
, (FIFO_RXTX
<< 2) | 0x3);
323 /* net result needs to be rounded down and decremented by 1 */
324 if (count
> RXCLK_RCD
+ 1)
334 * IR Control Register helpers
336 enum tx_fifo_watermark
{
337 TX_FIFO_HALF_EMPTY
= 0,
338 TX_FIFO_EMPTY
= CNTRL_TIC
,
341 enum rx_fifo_watermark
{
342 RX_FIFO_HALF_FULL
= 0,
343 RX_FIFO_NOT_EMPTY
= CNTRL_RIC
,
346 static inline void control_tx_irq_watermark(struct i2c_client
*c
,
347 enum tx_fifo_watermark level
)
349 cx25840_and_or4(c
, CX25840_IR_CNTRL_REG
, ~CNTRL_TIC
, level
);
352 static inline void control_rx_irq_watermark(struct i2c_client
*c
,
353 enum rx_fifo_watermark level
)
355 cx25840_and_or4(c
, CX25840_IR_CNTRL_REG
, ~CNTRL_RIC
, level
);
358 static inline void control_tx_enable(struct i2c_client
*c
, bool enable
)
360 cx25840_and_or4(c
, CX25840_IR_CNTRL_REG
, ~(CNTRL_TXE
| CNTRL_TFE
),
361 enable
? (CNTRL_TXE
| CNTRL_TFE
) : 0);
364 static inline void control_rx_enable(struct i2c_client
*c
, bool enable
)
366 cx25840_and_or4(c
, CX25840_IR_CNTRL_REG
, ~(CNTRL_RXE
| CNTRL_RFE
),
367 enable
? (CNTRL_RXE
| CNTRL_RFE
) : 0);
370 static inline void control_tx_modulation_enable(struct i2c_client
*c
,
373 cx25840_and_or4(c
, CX25840_IR_CNTRL_REG
, ~CNTRL_MOD
,
374 enable
? CNTRL_MOD
: 0);
377 static inline void control_rx_demodulation_enable(struct i2c_client
*c
,
380 cx25840_and_or4(c
, CX25840_IR_CNTRL_REG
, ~CNTRL_DMD
,
381 enable
? CNTRL_DMD
: 0);
384 static inline void control_rx_s_edge_detection(struct i2c_client
*c
,
387 cx25840_and_or4(c
, CX25840_IR_CNTRL_REG
, ~CNTRL_EDG_BOTH
,
388 edge_types
& CNTRL_EDG_BOTH
);
391 static void control_rx_s_carrier_window(struct i2c_client
*c
,
392 unsigned int carrier
,
393 unsigned int *carrier_range_low
,
394 unsigned int *carrier_range_high
)
397 unsigned int c16
= carrier
* 16;
399 if (*carrier_range_low
< DIV_ROUND_CLOSEST(c16
, 16 + 3)) {
401 *carrier_range_low
= DIV_ROUND_CLOSEST(c16
, 16 + 4);
404 *carrier_range_low
= DIV_ROUND_CLOSEST(c16
, 16 + 3);
407 if (*carrier_range_high
> DIV_ROUND_CLOSEST(c16
, 16 - 3)) {
409 *carrier_range_high
= DIV_ROUND_CLOSEST(c16
, 16 - 4);
412 *carrier_range_high
= DIV_ROUND_CLOSEST(c16
, 16 - 3);
414 cx25840_and_or4(c
, CX25840_IR_CNTRL_REG
, ~CNTRL_WIN
, v
);
417 static inline void control_tx_polarity_invert(struct i2c_client
*c
,
420 cx25840_and_or4(c
, CX25840_IR_CNTRL_REG
, ~CNTRL_CPL
,
421 invert
? CNTRL_CPL
: 0);
425 * IR Rx & Tx Clock Register helpers
427 static unsigned int txclk_tx_s_carrier(struct i2c_client
*c
,
431 *divider
= carrier_freq_to_clock_divider(freq
);
432 cx25840_write4(c
, CX25840_IR_TXCLK_REG
, *divider
);
433 return clock_divider_to_carrier_freq(*divider
);
436 static unsigned int rxclk_rx_s_carrier(struct i2c_client
*c
,
440 *divider
= carrier_freq_to_clock_divider(freq
);
441 cx25840_write4(c
, CX25840_IR_RXCLK_REG
, *divider
);
442 return clock_divider_to_carrier_freq(*divider
);
445 static u32
txclk_tx_s_max_pulse_width(struct i2c_client
*c
, u32 ns
,
450 if (ns
> IR_MAX_DURATION
)
451 ns
= IR_MAX_DURATION
;
452 pulse_clocks
= ns_to_pulse_clocks(ns
);
453 *divider
= pulse_clocks_to_clock_divider(pulse_clocks
);
454 cx25840_write4(c
, CX25840_IR_TXCLK_REG
, *divider
);
455 return (u32
) pulse_width_count_to_ns(FIFO_RXTX
, *divider
);
458 static u32
rxclk_rx_s_max_pulse_width(struct i2c_client
*c
, u32 ns
,
463 if (ns
> IR_MAX_DURATION
)
464 ns
= IR_MAX_DURATION
;
465 pulse_clocks
= ns_to_pulse_clocks(ns
);
466 *divider
= pulse_clocks_to_clock_divider(pulse_clocks
);
467 cx25840_write4(c
, CX25840_IR_RXCLK_REG
, *divider
);
468 return (u32
) pulse_width_count_to_ns(FIFO_RXTX
, *divider
);
472 * IR Tx Carrier Duty Cycle register helpers
474 static unsigned int cduty_tx_s_duty_cycle(struct i2c_client
*c
,
475 unsigned int duty_cycle
)
478 n
= DIV_ROUND_CLOSEST(duty_cycle
* 100, 625); /* 16ths of 100% */
483 cx25840_write4(c
, CX25840_IR_CDUTY_REG
, n
);
484 return DIV_ROUND_CLOSEST((n
+ 1) * 100, 16);
488 * IR Filter Register helpers
490 static u32
filter_rx_s_min_width(struct i2c_client
*c
, u32 min_width_ns
)
492 u32 count
= ns_to_lpf_count(min_width_ns
);
493 cx25840_write4(c
, CX25840_IR_FILTR_REG
, count
);
494 return lpf_count_to_ns(count
);
498 * IR IRQ Enable Register helpers
500 static inline void irqenable_rx(struct v4l2_subdev
*sd
, u32 mask
)
502 struct cx25840_state
*state
= to_state(sd
);
504 if (is_cx23885(state
) || is_cx23887(state
))
506 mask
&= (IRQEN_RTE
| IRQEN_ROE
| IRQEN_RSE
);
507 cx25840_and_or4(state
->c
, CX25840_IR_IRQEN_REG
,
508 ~(IRQEN_RTE
| IRQEN_ROE
| IRQEN_RSE
), mask
);
511 static inline void irqenable_tx(struct v4l2_subdev
*sd
, u32 mask
)
513 struct cx25840_state
*state
= to_state(sd
);
515 if (is_cx23885(state
) || is_cx23887(state
))
518 cx25840_and_or4(state
->c
, CX25840_IR_IRQEN_REG
, ~IRQEN_TSE
, mask
);
522 * V4L2 Subdevice IR Ops
524 int cx25840_ir_irq_handler(struct v4l2_subdev
*sd
, u32 status
, bool *handled
)
526 struct cx25840_state
*state
= to_state(sd
);
527 struct cx25840_ir_state
*ir_state
= to_ir_state(sd
);
528 struct i2c_client
*c
= NULL
;
531 union cx25840_ir_fifo_rec rx_data
[FIFO_RX_DEPTH
];
532 unsigned int i
, j
, k
;
534 int tsr
, rsr
, rto
, ror
, tse
, rse
, rte
, roe
, kror
;
535 u32 cntrl
, irqen
, stats
;
538 if (ir_state
== NULL
)
543 /* Only support the IR controller for the CX2388[57] AV Core for now */
544 if (!(is_cx23885(state
) || is_cx23887(state
)))
547 cntrl
= cx25840_read4(c
, CX25840_IR_CNTRL_REG
);
548 irqen
= cx25840_read4(c
, CX25840_IR_IRQEN_REG
);
549 if (is_cx23885(state
) || is_cx23887(state
))
551 stats
= cx25840_read4(c
, CX25840_IR_STATS_REG
);
553 tsr
= stats
& STATS_TSR
; /* Tx FIFO Service Request */
554 rsr
= stats
& STATS_RSR
; /* Rx FIFO Service Request */
555 rto
= stats
& STATS_RTO
; /* Rx Pulse Width Timer Time Out */
556 ror
= stats
& STATS_ROR
; /* Rx FIFO Over Run */
558 tse
= irqen
& IRQEN_TSE
; /* Tx FIFO Service Request IRQ Enable */
559 rse
= irqen
& IRQEN_RSE
; /* Rx FIFO Service Reuqest IRQ Enable */
560 rte
= irqen
& IRQEN_RTE
; /* Rx Pulse Width Timer Time Out IRQ Enable */
561 roe
= irqen
& IRQEN_ROE
; /* Rx FIFO Over Run IRQ Enable */
563 v4l2_dbg(2, ir_debug
, sd
, "IR IRQ Status: %s %s %s %s %s %s\n",
564 tsr
? "tsr" : " ", rsr
? "rsr" : " ",
565 rto
? "rto" : " ", ror
? "ror" : " ",
566 stats
& STATS_TBY
? "tby" : " ",
567 stats
& STATS_RBY
? "rby" : " ");
569 v4l2_dbg(2, ir_debug
, sd
, "IR IRQ Enables: %s %s %s %s\n",
570 tse
? "tse" : " ", rse
? "rse" : " ",
571 rte
? "rte" : " ", roe
? "roe" : " ");
574 * Transmitter interrupt service
579 * Check the watermark threshold setting
580 * Pull FIFO_TX_DEPTH or FIFO_TX_DEPTH/2 entries from tx_kfifo
581 * Push the data to the hardware FIFO.
582 * If there was nothing more to send in the tx_kfifo, disable
583 * the TSR IRQ and notify the v4l2_device.
584 * If there was something in the tx_kfifo, check the tx_kfifo
585 * level and notify the v4l2_device, if it is low.
587 /* For now, inhibit TSR interrupt until Tx is implemented */
589 events
= V4L2_SUBDEV_IR_TX_FIFO_SERVICE_REQ
;
590 v4l2_subdev_notify(sd
, V4L2_SUBDEV_IR_TX_NOTIFY
, &events
);
595 * Receiver interrupt service
598 if ((rse
&& rsr
) || (rte
&& rto
)) {
600 * Receive data on RSR to clear the STATS_RSR.
601 * Receive data on RTO, since we may not have yet hit the RSR
602 * watermark when we receive the RTO.
604 for (i
= 0, v
= FIFO_RX_NDV
;
605 (v
& FIFO_RX_NDV
) && !kror
; i
= 0) {
607 (v
& FIFO_RX_NDV
) && j
< FIFO_RX_DEPTH
; j
++) {
608 v
= cx25840_read4(c
, CX25840_IR_FIFO_REG
);
609 rx_data
[i
].hw_fifo_data
= v
& ~FIFO_RX_NDV
;
614 j
= i
* sizeof(union cx25840_ir_fifo_rec
);
615 k
= kfifo_in_locked(&ir_state
->rx_kfifo
,
616 (unsigned char *) rx_data
, j
,
617 &ir_state
->rx_kfifo_lock
);
619 kror
++; /* rx_kfifo over run */
627 events
|= V4L2_SUBDEV_IR_RX_SW_FIFO_OVERRUN
;
628 v4l2_err(sd
, "IR receiver software FIFO overrun\n");
632 * The RX FIFO Enable (CNTRL_RFE) must be toggled to clear
633 * the Rx FIFO Over Run status (STATS_ROR)
636 events
|= V4L2_SUBDEV_IR_RX_HW_FIFO_OVERRUN
;
637 v4l2_err(sd
, "IR receiver hardware FIFO overrun\n");
641 * The IR Receiver Enable (CNTRL_RXE) must be toggled to clear
642 * the Rx Pulse Width Timer Time Out (STATS_RTO)
645 events
|= V4L2_SUBDEV_IR_RX_END_OF_RX_DETECTED
;
648 /* Clear STATS_ROR & STATS_RTO as needed by reseting hardware */
649 cx25840_write4(c
, CX25840_IR_CNTRL_REG
, cntrl
& ~v
);
650 cx25840_write4(c
, CX25840_IR_CNTRL_REG
, cntrl
);
653 spin_lock_irqsave(&ir_state
->rx_kfifo_lock
, flags
);
654 if (kfifo_len(&ir_state
->rx_kfifo
) >= CX25840_IR_RX_KFIFO_SIZE
/ 2)
655 events
|= V4L2_SUBDEV_IR_RX_FIFO_SERVICE_REQ
;
656 spin_unlock_irqrestore(&ir_state
->rx_kfifo_lock
, flags
);
659 v4l2_subdev_notify(sd
, V4L2_SUBDEV_IR_RX_NOTIFY
, &events
);
664 static int cx25840_ir_rx_read(struct v4l2_subdev
*sd
, u8
*buf
, size_t count
,
667 struct cx25840_ir_state
*ir_state
= to_ir_state(sd
);
671 union cx25840_ir_fifo_rec
*p
;
674 if (ir_state
== NULL
)
677 invert
= (bool) atomic_read(&ir_state
->rx_invert
);
678 divider
= (u16
) atomic_read(&ir_state
->rxclk_divider
);
680 n
= count
/ sizeof(union cx25840_ir_fifo_rec
)
681 * sizeof(union cx25840_ir_fifo_rec
);
687 n
= kfifo_out_locked(&ir_state
->rx_kfifo
, buf
, n
,
688 &ir_state
->rx_kfifo_lock
);
690 n
/= sizeof(union cx25840_ir_fifo_rec
);
691 *num
= n
* sizeof(union cx25840_ir_fifo_rec
);
693 for (p
= (union cx25840_ir_fifo_rec
*) buf
, i
= 0; i
< n
; p
++, i
++) {
695 if ((p
->hw_fifo_data
& FIFO_RXTX_RTO
) == FIFO_RXTX_RTO
) {
696 /* Assume RTO was because of no IR light input */
698 v4l2_dbg(2, ir_debug
, sd
, "rx read: end of rx\n");
700 u
= (p
->hw_fifo_data
& FIFO_RXTX_LVL
) ? 1 : 0;
705 v
= (unsigned) pulse_width_count_to_ns(
706 (u16
) (p
->hw_fifo_data
& FIFO_RXTX
), divider
);
707 if (v
> IR_MAX_DURATION
)
710 init_ir_raw_event(&p
->ir_core_data
);
711 p
->ir_core_data
.pulse
= u
;
712 p
->ir_core_data
.duration
= v
;
714 v4l2_dbg(2, ir_debug
, sd
, "rx read: %10u ns %s\n",
715 v
, u
? "mark" : "space");
720 static int cx25840_ir_rx_g_parameters(struct v4l2_subdev
*sd
,
721 struct v4l2_subdev_ir_parameters
*p
)
723 struct cx25840_ir_state
*ir_state
= to_ir_state(sd
);
725 if (ir_state
== NULL
)
728 mutex_lock(&ir_state
->rx_params_lock
);
729 memcpy(p
, &ir_state
->rx_params
,
730 sizeof(struct v4l2_subdev_ir_parameters
));
731 mutex_unlock(&ir_state
->rx_params_lock
);
735 static int cx25840_ir_rx_shutdown(struct v4l2_subdev
*sd
)
737 struct cx25840_ir_state
*ir_state
= to_ir_state(sd
);
738 struct i2c_client
*c
;
740 if (ir_state
== NULL
)
744 mutex_lock(&ir_state
->rx_params_lock
);
746 /* Disable or slow down all IR Rx circuits and counters */
748 control_rx_enable(c
, false);
749 control_rx_demodulation_enable(c
, false);
750 control_rx_s_edge_detection(c
, CNTRL_EDG_NONE
);
751 filter_rx_s_min_width(c
, 0);
752 cx25840_write4(c
, CX25840_IR_RXCLK_REG
, RXCLK_RCD
);
754 ir_state
->rx_params
.shutdown
= true;
756 mutex_unlock(&ir_state
->rx_params_lock
);
760 static int cx25840_ir_rx_s_parameters(struct v4l2_subdev
*sd
,
761 struct v4l2_subdev_ir_parameters
*p
)
763 struct cx25840_ir_state
*ir_state
= to_ir_state(sd
);
764 struct i2c_client
*c
;
765 struct v4l2_subdev_ir_parameters
*o
;
768 if (ir_state
== NULL
)
772 return cx25840_ir_rx_shutdown(sd
);
774 if (p
->mode
!= V4L2_SUBDEV_IR_MODE_PULSE_WIDTH
)
778 o
= &ir_state
->rx_params
;
780 mutex_lock(&ir_state
->rx_params_lock
);
782 o
->shutdown
= p
->shutdown
;
784 p
->mode
= V4L2_SUBDEV_IR_MODE_PULSE_WIDTH
;
787 p
->bytes_per_data_element
= sizeof(union cx25840_ir_fifo_rec
);
788 o
->bytes_per_data_element
= p
->bytes_per_data_element
;
790 /* Before we tweak the hardware, we have to disable the receiver */
792 control_rx_enable(c
, false);
794 control_rx_demodulation_enable(c
, p
->modulation
);
795 o
->modulation
= p
->modulation
;
798 p
->carrier_freq
= rxclk_rx_s_carrier(c
, p
->carrier_freq
,
801 o
->carrier_freq
= p
->carrier_freq
;
804 o
->duty_cycle
= p
->duty_cycle
;
806 control_rx_s_carrier_window(c
, p
->carrier_freq
,
807 &p
->carrier_range_lower
,
808 &p
->carrier_range_upper
);
809 o
->carrier_range_lower
= p
->carrier_range_lower
;
810 o
->carrier_range_upper
= p
->carrier_range_upper
;
813 (u32
) pulse_width_count_to_ns(FIFO_RXTX
, rxclk_divider
);
816 rxclk_rx_s_max_pulse_width(c
, p
->max_pulse_width
,
819 o
->max_pulse_width
= p
->max_pulse_width
;
820 atomic_set(&ir_state
->rxclk_divider
, rxclk_divider
);
822 p
->noise_filter_min_width
=
823 filter_rx_s_min_width(c
, p
->noise_filter_min_width
);
824 o
->noise_filter_min_width
= p
->noise_filter_min_width
;
826 p
->resolution
= clock_divider_to_resolution(rxclk_divider
);
827 o
->resolution
= p
->resolution
;
829 /* FIXME - make this dependent on resolution for better performance */
830 control_rx_irq_watermark(c
, RX_FIFO_HALF_FULL
);
832 control_rx_s_edge_detection(c
, CNTRL_EDG_BOTH
);
834 o
->invert_level
= p
->invert_level
;
835 atomic_set(&ir_state
->rx_invert
, p
->invert_level
);
837 o
->interrupt_enable
= p
->interrupt_enable
;
838 o
->enable
= p
->enable
;
842 spin_lock_irqsave(&ir_state
->rx_kfifo_lock
, flags
);
843 kfifo_reset(&ir_state
->rx_kfifo
);
844 spin_unlock_irqrestore(&ir_state
->rx_kfifo_lock
, flags
);
845 if (p
->interrupt_enable
)
846 irqenable_rx(sd
, IRQEN_RSE
| IRQEN_RTE
| IRQEN_ROE
);
847 control_rx_enable(c
, p
->enable
);
850 mutex_unlock(&ir_state
->rx_params_lock
);
855 static int cx25840_ir_tx_write(struct v4l2_subdev
*sd
, u8
*buf
, size_t count
,
858 struct cx25840_ir_state
*ir_state
= to_ir_state(sd
);
859 struct i2c_client
*c
;
861 if (ir_state
== NULL
)
867 * FIXME - the code below is an incomplete and untested sketch of what
868 * may need to be done. The critical part is to get 4 (or 8) pulses
869 * from the tx_kfifo, or converted from ns to the proper units from the
870 * input, and push them off to the hardware Tx FIFO right away, if the
871 * HW TX fifo needs service. The rest can be pushed to the tx_kfifo in
872 * a less critical timeframe. Also watch out for overruning the
873 * tx_kfifo - don't let it happen and let the caller know not all his
874 * pulses were written.
876 u32
*ns_pulse
= (u32
*) buf
;
878 u32 fifo_pulse
[FIFO_TX_DEPTH
];
881 /* Compute how much we can fit in the tx kfifo */
882 n
= CX25840_IR_TX_KFIFO_SIZE
- kfifo_len(ir_state
->tx_kfifo
);
883 n
= min(n
, (unsigned int) count
);
886 /* FIXME - turn on Tx Fifo service interrupt
887 * check hardware fifo level, and other stuff
889 for (i
= 0; i
< n
; ) {
890 for (j
= 0; j
< FIFO_TX_DEPTH
/ 2 && i
< n
; j
++) {
891 mark
= ns_pulse
[i
] & LEVEL_MASK
;
892 fifo_pulse
[j
] = ns_to_pulse_width_count(
895 ir_state
->txclk_divider
);
897 fifo_pulse
[j
] &= FIFO_RXTX_LVL
;
900 kfifo_put(ir_state
->tx_kfifo
, (u8
*) fifo_pulse
,
903 *num
= n
* sizeof(u32
);
905 /* For now enable the Tx FIFO Service interrupt & pretend we did work */
906 irqenable_tx(sd
, IRQEN_TSE
);
912 static int cx25840_ir_tx_g_parameters(struct v4l2_subdev
*sd
,
913 struct v4l2_subdev_ir_parameters
*p
)
915 struct cx25840_ir_state
*ir_state
= to_ir_state(sd
);
917 if (ir_state
== NULL
)
920 mutex_lock(&ir_state
->tx_params_lock
);
921 memcpy(p
, &ir_state
->tx_params
,
922 sizeof(struct v4l2_subdev_ir_parameters
));
923 mutex_unlock(&ir_state
->tx_params_lock
);
927 static int cx25840_ir_tx_shutdown(struct v4l2_subdev
*sd
)
929 struct cx25840_ir_state
*ir_state
= to_ir_state(sd
);
930 struct i2c_client
*c
;
932 if (ir_state
== NULL
)
936 mutex_lock(&ir_state
->tx_params_lock
);
938 /* Disable or slow down all IR Tx circuits and counters */
940 control_tx_enable(c
, false);
941 control_tx_modulation_enable(c
, false);
942 cx25840_write4(c
, CX25840_IR_TXCLK_REG
, TXCLK_TCD
);
944 ir_state
->tx_params
.shutdown
= true;
946 mutex_unlock(&ir_state
->tx_params_lock
);
950 static int cx25840_ir_tx_s_parameters(struct v4l2_subdev
*sd
,
951 struct v4l2_subdev_ir_parameters
*p
)
953 struct cx25840_ir_state
*ir_state
= to_ir_state(sd
);
954 struct i2c_client
*c
;
955 struct v4l2_subdev_ir_parameters
*o
;
958 if (ir_state
== NULL
)
962 return cx25840_ir_tx_shutdown(sd
);
964 if (p
->mode
!= V4L2_SUBDEV_IR_MODE_PULSE_WIDTH
)
968 o
= &ir_state
->tx_params
;
969 mutex_lock(&ir_state
->tx_params_lock
);
971 o
->shutdown
= p
->shutdown
;
973 p
->mode
= V4L2_SUBDEV_IR_MODE_PULSE_WIDTH
;
976 p
->bytes_per_data_element
= sizeof(union cx25840_ir_fifo_rec
);
977 o
->bytes_per_data_element
= p
->bytes_per_data_element
;
979 /* Before we tweak the hardware, we have to disable the transmitter */
981 control_tx_enable(c
, false);
983 control_tx_modulation_enable(c
, p
->modulation
);
984 o
->modulation
= p
->modulation
;
987 p
->carrier_freq
= txclk_tx_s_carrier(c
, p
->carrier_freq
,
989 o
->carrier_freq
= p
->carrier_freq
;
991 p
->duty_cycle
= cduty_tx_s_duty_cycle(c
, p
->duty_cycle
);
992 o
->duty_cycle
= p
->duty_cycle
;
995 (u32
) pulse_width_count_to_ns(FIFO_RXTX
, txclk_divider
);
998 txclk_tx_s_max_pulse_width(c
, p
->max_pulse_width
,
1001 o
->max_pulse_width
= p
->max_pulse_width
;
1002 atomic_set(&ir_state
->txclk_divider
, txclk_divider
);
1004 p
->resolution
= clock_divider_to_resolution(txclk_divider
);
1005 o
->resolution
= p
->resolution
;
1007 /* FIXME - make this dependent on resolution for better performance */
1008 control_tx_irq_watermark(c
, TX_FIFO_HALF_EMPTY
);
1010 control_tx_polarity_invert(c
, p
->invert_carrier_sense
);
1011 o
->invert_carrier_sense
= p
->invert_carrier_sense
;
1014 * FIXME: we don't have hardware help for IO pin level inversion
1015 * here like we have on the CX23888.
1016 * Act on this with some mix of logical inversion of data levels,
1017 * carrier polarity, and carrier duty cycle.
1019 o
->invert_level
= p
->invert_level
;
1021 o
->interrupt_enable
= p
->interrupt_enable
;
1022 o
->enable
= p
->enable
;
1024 /* reset tx_fifo here */
1025 if (p
->interrupt_enable
)
1026 irqenable_tx(sd
, IRQEN_TSE
);
1027 control_tx_enable(c
, p
->enable
);
1030 mutex_unlock(&ir_state
->tx_params_lock
);
1036 * V4L2 Subdevice Core Ops support
1038 int cx25840_ir_log_status(struct v4l2_subdev
*sd
)
1040 struct cx25840_state
*state
= to_state(sd
);
1041 struct i2c_client
*c
= state
->c
;
1044 u32 cntrl
, txclk
, rxclk
, cduty
, stats
, irqen
, filtr
;
1046 /* The CX23888 chip doesn't have an IR controller on the A/V core */
1047 if (is_cx23888(state
))
1050 cntrl
= cx25840_read4(c
, CX25840_IR_CNTRL_REG
);
1051 txclk
= cx25840_read4(c
, CX25840_IR_TXCLK_REG
) & TXCLK_TCD
;
1052 rxclk
= cx25840_read4(c
, CX25840_IR_RXCLK_REG
) & RXCLK_RCD
;
1053 cduty
= cx25840_read4(c
, CX25840_IR_CDUTY_REG
) & CDUTY_CDC
;
1054 stats
= cx25840_read4(c
, CX25840_IR_STATS_REG
);
1055 irqen
= cx25840_read4(c
, CX25840_IR_IRQEN_REG
);
1056 if (is_cx23885(state
) || is_cx23887(state
))
1058 filtr
= cx25840_read4(c
, CX25840_IR_FILTR_REG
) & FILTR_LPF
;
1060 v4l2_info(sd
, "IR Receiver:\n");
1061 v4l2_info(sd
, "\tEnabled: %s\n",
1062 cntrl
& CNTRL_RXE
? "yes" : "no");
1063 v4l2_info(sd
, "\tDemodulation from a carrier: %s\n",
1064 cntrl
& CNTRL_DMD
? "enabled" : "disabled");
1065 v4l2_info(sd
, "\tFIFO: %s\n",
1066 cntrl
& CNTRL_RFE
? "enabled" : "disabled");
1067 switch (cntrl
& CNTRL_EDG
) {
1068 case CNTRL_EDG_NONE
:
1071 case CNTRL_EDG_FALL
:
1074 case CNTRL_EDG_RISE
:
1077 case CNTRL_EDG_BOTH
:
1078 s
= "rising & falling edges";
1084 v4l2_info(sd
, "\tPulse timers' start/stop trigger: %s\n", s
);
1085 v4l2_info(sd
, "\tFIFO data on pulse timer overflow: %s\n",
1086 cntrl
& CNTRL_R
? "not loaded" : "overflow marker");
1087 v4l2_info(sd
, "\tFIFO interrupt watermark: %s\n",
1088 cntrl
& CNTRL_RIC
? "not empty" : "half full or greater");
1089 v4l2_info(sd
, "\tLoopback mode: %s\n",
1090 cntrl
& CNTRL_LBM
? "loopback active" : "normal receive");
1091 if (cntrl
& CNTRL_DMD
) {
1092 v4l2_info(sd
, "\tExpected carrier (16 clocks): %u Hz\n",
1093 clock_divider_to_carrier_freq(rxclk
));
1094 switch (cntrl
& CNTRL_WIN
) {
1116 v4l2_info(sd
, "\tNext carrier edge window: 16 clocks "
1117 "-%1d/+%1d, %u to %u Hz\n", i
, j
,
1118 clock_divider_to_freq(rxclk
, 16 + j
),
1119 clock_divider_to_freq(rxclk
, 16 - i
));
1121 v4l2_info(sd
, "\tMax measurable pulse width: %u us, %llu ns\n",
1122 pulse_width_count_to_us(FIFO_RXTX
, rxclk
),
1123 pulse_width_count_to_ns(FIFO_RXTX
, rxclk
));
1124 v4l2_info(sd
, "\tLow pass filter: %s\n",
1125 filtr
? "enabled" : "disabled");
1127 v4l2_info(sd
, "\tMin acceptable pulse width (LPF): %u us, "
1129 lpf_count_to_us(filtr
),
1130 lpf_count_to_ns(filtr
));
1131 v4l2_info(sd
, "\tPulse width timer timed-out: %s\n",
1132 stats
& STATS_RTO
? "yes" : "no");
1133 v4l2_info(sd
, "\tPulse width timer time-out intr: %s\n",
1134 irqen
& IRQEN_RTE
? "enabled" : "disabled");
1135 v4l2_info(sd
, "\tFIFO overrun: %s\n",
1136 stats
& STATS_ROR
? "yes" : "no");
1137 v4l2_info(sd
, "\tFIFO overrun interrupt: %s\n",
1138 irqen
& IRQEN_ROE
? "enabled" : "disabled");
1139 v4l2_info(sd
, "\tBusy: %s\n",
1140 stats
& STATS_RBY
? "yes" : "no");
1141 v4l2_info(sd
, "\tFIFO service requested: %s\n",
1142 stats
& STATS_RSR
? "yes" : "no");
1143 v4l2_info(sd
, "\tFIFO service request interrupt: %s\n",
1144 irqen
& IRQEN_RSE
? "enabled" : "disabled");
1146 v4l2_info(sd
, "IR Transmitter:\n");
1147 v4l2_info(sd
, "\tEnabled: %s\n",
1148 cntrl
& CNTRL_TXE
? "yes" : "no");
1149 v4l2_info(sd
, "\tModulation onto a carrier: %s\n",
1150 cntrl
& CNTRL_MOD
? "enabled" : "disabled");
1151 v4l2_info(sd
, "\tFIFO: %s\n",
1152 cntrl
& CNTRL_TFE
? "enabled" : "disabled");
1153 v4l2_info(sd
, "\tFIFO interrupt watermark: %s\n",
1154 cntrl
& CNTRL_TIC
? "not empty" : "half full or less");
1155 v4l2_info(sd
, "\tCarrier polarity: %s\n",
1156 cntrl
& CNTRL_CPL
? "space:burst mark:noburst"
1157 : "space:noburst mark:burst");
1158 if (cntrl
& CNTRL_MOD
) {
1159 v4l2_info(sd
, "\tCarrier (16 clocks): %u Hz\n",
1160 clock_divider_to_carrier_freq(txclk
));
1161 v4l2_info(sd
, "\tCarrier duty cycle: %2u/16\n",
1164 v4l2_info(sd
, "\tMax pulse width: %u us, %llu ns\n",
1165 pulse_width_count_to_us(FIFO_RXTX
, txclk
),
1166 pulse_width_count_to_ns(FIFO_RXTX
, txclk
));
1167 v4l2_info(sd
, "\tBusy: %s\n",
1168 stats
& STATS_TBY
? "yes" : "no");
1169 v4l2_info(sd
, "\tFIFO service requested: %s\n",
1170 stats
& STATS_TSR
? "yes" : "no");
1171 v4l2_info(sd
, "\tFIFO service request interrupt: %s\n",
1172 irqen
& IRQEN_TSE
? "enabled" : "disabled");
1178 const struct v4l2_subdev_ir_ops cx25840_ir_ops
= {
1179 .rx_read
= cx25840_ir_rx_read
,
1180 .rx_g_parameters
= cx25840_ir_rx_g_parameters
,
1181 .rx_s_parameters
= cx25840_ir_rx_s_parameters
,
1183 .tx_write
= cx25840_ir_tx_write
,
1184 .tx_g_parameters
= cx25840_ir_tx_g_parameters
,
1185 .tx_s_parameters
= cx25840_ir_tx_s_parameters
,
1189 static const struct v4l2_subdev_ir_parameters default_rx_params
= {
1190 .bytes_per_data_element
= sizeof(union cx25840_ir_fifo_rec
),
1191 .mode
= V4L2_SUBDEV_IR_MODE_PULSE_WIDTH
,
1194 .interrupt_enable
= false,
1198 .carrier_freq
= 36000, /* 36 kHz - RC-5, and RC-6 carrier */
1200 /* RC-5: 666,667 ns = 1/36 kHz * 32 cycles * 1 mark * 0.75 */
1201 /* RC-6: 333,333 ns = 1/36 kHz * 16 cycles * 1 mark * 0.75 */
1202 .noise_filter_min_width
= 333333, /* ns */
1203 .carrier_range_lower
= 35000,
1204 .carrier_range_upper
= 37000,
1205 .invert_level
= false,
1208 static const struct v4l2_subdev_ir_parameters default_tx_params
= {
1209 .bytes_per_data_element
= sizeof(union cx25840_ir_fifo_rec
),
1210 .mode
= V4L2_SUBDEV_IR_MODE_PULSE_WIDTH
,
1213 .interrupt_enable
= false,
1217 .carrier_freq
= 36000, /* 36 kHz - RC-5 carrier */
1218 .duty_cycle
= 25, /* 25 % - RC-5 carrier */
1219 .invert_level
= false,
1220 .invert_carrier_sense
= false,
1223 int cx25840_ir_probe(struct v4l2_subdev
*sd
)
1225 struct cx25840_state
*state
= to_state(sd
);
1226 struct cx25840_ir_state
*ir_state
;
1227 struct v4l2_subdev_ir_parameters default_params
;
1229 /* Only init the IR controller for the CX2388[57] AV Core for now */
1230 if (!(is_cx23885(state
) || is_cx23887(state
)))
1233 ir_state
= kzalloc(sizeof(struct cx25840_ir_state
), GFP_KERNEL
);
1234 if (ir_state
== NULL
)
1237 spin_lock_init(&ir_state
->rx_kfifo_lock
);
1238 if (kfifo_alloc(&ir_state
->rx_kfifo
,
1239 CX25840_IR_RX_KFIFO_SIZE
, GFP_KERNEL
)) {
1244 ir_state
->c
= state
->c
;
1245 state
->ir_state
= ir_state
;
1247 /* Ensure no interrupts arrive yet */
1248 if (is_cx23885(state
) || is_cx23887(state
))
1249 cx25840_write4(ir_state
->c
, CX25840_IR_IRQEN_REG
, IRQEN_MSK
);
1251 cx25840_write4(ir_state
->c
, CX25840_IR_IRQEN_REG
, 0);
1253 mutex_init(&ir_state
->rx_params_lock
);
1254 memcpy(&default_params
, &default_rx_params
,
1255 sizeof(struct v4l2_subdev_ir_parameters
));
1256 v4l2_subdev_call(sd
, ir
, rx_s_parameters
, &default_params
);
1258 mutex_init(&ir_state
->tx_params_lock
);
1259 memcpy(&default_params
, &default_tx_params
,
1260 sizeof(struct v4l2_subdev_ir_parameters
));
1261 v4l2_subdev_call(sd
, ir
, tx_s_parameters
, &default_params
);
1266 int cx25840_ir_remove(struct v4l2_subdev
*sd
)
1268 struct cx25840_state
*state
= to_state(sd
);
1269 struct cx25840_ir_state
*ir_state
= to_ir_state(sd
);
1271 if (ir_state
== NULL
)
1274 cx25840_ir_rx_shutdown(sd
);
1275 cx25840_ir_tx_shutdown(sd
);
1277 kfifo_free(&ir_state
->rx_kfifo
);
1279 state
->ir_state
= NULL
;