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Add linux-next specific files for 20110831
[linux-2.6/next.git] / drivers / media / video / pvrusb2 / pvrusb2-hdw.c
blob9a62d2b894cc29920e10fec21673cb07a5f8822b
1 /*
2 *
3 *
4 * Copyright (C) 2005 Mike Isely <isely@pobox.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 *
19 */
20
21 #include <linux/errno.h>
22 #include <linux/string.h>
23 #include <linux/slab.h>
24 #include <linux/module.h>
25 #include <linux/firmware.h>
26 #include <linux/videodev2.h>
27 #include <media/v4l2-common.h>
28 #include <media/tuner.h>
29 #include "pvrusb2.h"
30 #include "pvrusb2-std.h"
31 #include "pvrusb2-util.h"
32 #include "pvrusb2-hdw.h"
33 #include "pvrusb2-i2c-core.h"
34 #include "pvrusb2-eeprom.h"
35 #include "pvrusb2-hdw-internal.h"
36 #include "pvrusb2-encoder.h"
37 #include "pvrusb2-debug.h"
38 #include "pvrusb2-fx2-cmd.h"
39 #include "pvrusb2-wm8775.h"
40 #include "pvrusb2-video-v4l.h"
41 #include "pvrusb2-cx2584x-v4l.h"
42 #include "pvrusb2-cs53l32a.h"
43 #include "pvrusb2-audio.h"
44
45 #define TV_MIN_FREQ 55250000L
46 #define TV_MAX_FREQ 850000000L
47
48 /* This defines a minimum interval that the decoder must remain quiet
49 before we are allowed to start it running. */
50 #define TIME_MSEC_DECODER_WAIT 50
51
52 /* This defines a minimum interval that the decoder must be allowed to run
53 before we can safely begin using its streaming output. */
54 #define TIME_MSEC_DECODER_STABILIZATION_WAIT 300
55
56 /* This defines a minimum interval that the encoder must remain quiet
57 before we are allowed to configure it. */
58 #define TIME_MSEC_ENCODER_WAIT 50
59
60 /* This defines the minimum interval that the encoder must successfully run
61 before we consider that the encoder has run at least once since its
62 firmware has been loaded. This measurement is in important for cases
63 where we can't do something until we know that the encoder has been run
64 at least once. */
65 #define TIME_MSEC_ENCODER_OK 250
66
67 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
68 static DEFINE_MUTEX(pvr2_unit_mtx);
69
70 static int ctlchg;
71 static int procreload;
72 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
73 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
74 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
75 static int init_pause_msec;
76
77 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
78 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
79 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
80 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
81 module_param(procreload, int, S_IRUGO|S_IWUSR);
82 MODULE_PARM_DESC(procreload,
83 "Attempt init failure recovery with firmware reload");
84 module_param_array(tuner, int, NULL, 0444);
85 MODULE_PARM_DESC(tuner,"specify installed tuner type");
86 module_param_array(video_std, int, NULL, 0444);
87 MODULE_PARM_DESC(video_std,"specify initial video standard");
88 module_param_array(tolerance, int, NULL, 0444);
89 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
90
91 /* US Broadcast channel 3 (61.25 MHz), to help with testing */
92 static int default_tv_freq = 61250000L;
93 /* 104.3 MHz, a usable FM station for my area */
94 static int default_radio_freq = 104300000L;
95
96 module_param_named(tv_freq, default_tv_freq, int, 0444);
97 MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
98 module_param_named(radio_freq, default_radio_freq, int, 0444);
99 MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
100
101 #define PVR2_CTL_WRITE_ENDPOINT 0x01
102 #define PVR2_CTL_READ_ENDPOINT 0x81
103
104 #define PVR2_GPIO_IN 0x9008
105 #define PVR2_GPIO_OUT 0x900c
106 #define PVR2_GPIO_DIR 0x9020
107
108 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
109
110 #define PVR2_FIRMWARE_ENDPOINT 0x02
111
112 /* size of a firmware chunk */
113 #define FIRMWARE_CHUNK_SIZE 0x2000
114
115 typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
116 struct v4l2_subdev *);
117
118 static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
119 [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
120 [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
121 [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
122 [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
123 [PVR2_CLIENT_ID_CS53L32A] = pvr2_cs53l32a_subdev_update,
124 };
125
126 static const char *module_names[] = {
127 [PVR2_CLIENT_ID_MSP3400] = "msp3400",
128 [PVR2_CLIENT_ID_CX25840] = "cx25840",
129 [PVR2_CLIENT_ID_SAA7115] = "saa7115",
130 [PVR2_CLIENT_ID_TUNER] = "tuner",
131 [PVR2_CLIENT_ID_DEMOD] = "tuner",
132 [PVR2_CLIENT_ID_CS53L32A] = "cs53l32a",
133 [PVR2_CLIENT_ID_WM8775] = "wm8775",
134 };
135
136
137 static const unsigned char *module_i2c_addresses[] = {
138 [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
139 [PVR2_CLIENT_ID_DEMOD] = "\x43",
140 [PVR2_CLIENT_ID_MSP3400] = "\x40",
141 [PVR2_CLIENT_ID_SAA7115] = "\x21",
142 [PVR2_CLIENT_ID_WM8775] = "\x1b",
143 [PVR2_CLIENT_ID_CX25840] = "\x44",
144 [PVR2_CLIENT_ID_CS53L32A] = "\x11",
145 };
146
147
148 static const char *ir_scheme_names[] = {
149 [PVR2_IR_SCHEME_NONE] = "none",
150 [PVR2_IR_SCHEME_29XXX] = "29xxx",
151 [PVR2_IR_SCHEME_24XXX] = "24xxx (29xxx emulation)",
152 [PVR2_IR_SCHEME_24XXX_MCE] = "24xxx (MCE device)",
153 [PVR2_IR_SCHEME_ZILOG] = "Zilog",
154 };
155
156
157 /* Define the list of additional controls we'll dynamically construct based
158 on query of the cx2341x module. */
159 struct pvr2_mpeg_ids {
160 const char *strid;
161 int id;
162 };
163 static const struct pvr2_mpeg_ids mpeg_ids[] = {
164 {
165 .strid = "audio_layer",
166 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
167 },{
168 .strid = "audio_bitrate",
169 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
170 },{
171 /* Already using audio_mode elsewhere :-( */
172 .strid = "mpeg_audio_mode",
173 .id = V4L2_CID_MPEG_AUDIO_MODE,
174 },{
175 .strid = "mpeg_audio_mode_extension",
176 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
177 },{
178 .strid = "audio_emphasis",
179 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
180 },{
181 .strid = "audio_crc",
182 .id = V4L2_CID_MPEG_AUDIO_CRC,
183 },{
184 .strid = "video_aspect",
185 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
186 },{
187 .strid = "video_b_frames",
188 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
189 },{
190 .strid = "video_gop_size",
191 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
192 },{
193 .strid = "video_gop_closure",
194 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
195 },{
196 .strid = "video_bitrate_mode",
197 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
198 },{
199 .strid = "video_bitrate",
200 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
201 },{
202 .strid = "video_bitrate_peak",
203 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
204 },{
205 .strid = "video_temporal_decimation",
206 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
207 },{
208 .strid = "stream_type",
209 .id = V4L2_CID_MPEG_STREAM_TYPE,
210 },{
211 .strid = "video_spatial_filter_mode",
212 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
213 },{
214 .strid = "video_spatial_filter",
215 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
216 },{
217 .strid = "video_luma_spatial_filter_type",
218 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
219 },{
220 .strid = "video_chroma_spatial_filter_type",
221 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
222 },{
223 .strid = "video_temporal_filter_mode",
224 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
225 },{
226 .strid = "video_temporal_filter",
227 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
228 },{
229 .strid = "video_median_filter_type",
230 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
231 },{
232 .strid = "video_luma_median_filter_top",
233 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
234 },{
235 .strid = "video_luma_median_filter_bottom",
236 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
237 },{
238 .strid = "video_chroma_median_filter_top",
239 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
240 },{
241 .strid = "video_chroma_median_filter_bottom",
242 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
243 }
244 };
245 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
246
247
248 static const char *control_values_srate[] = {
249 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz",
250 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz",
251 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz",
252 };
253
254
255
256 static const char *control_values_input[] = {
257 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
258 [PVR2_CVAL_INPUT_DTV] = "dtv",
259 [PVR2_CVAL_INPUT_RADIO] = "radio",
260 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
261 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
262 };
263
264
265 static const char *control_values_audiomode[] = {
266 [V4L2_TUNER_MODE_MONO] = "Mono",
267 [V4L2_TUNER_MODE_STEREO] = "Stereo",
268 [V4L2_TUNER_MODE_LANG1] = "Lang1",
269 [V4L2_TUNER_MODE_LANG2] = "Lang2",
270 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
271 };
272
273
274 static const char *control_values_hsm[] = {
275 [PVR2_CVAL_HSM_FAIL] = "Fail",
276 [PVR2_CVAL_HSM_HIGH] = "High",
277 [PVR2_CVAL_HSM_FULL] = "Full",
278 };
279
280
281 static const char *pvr2_state_names[] = {
282 [PVR2_STATE_NONE] = "none",
283 [PVR2_STATE_DEAD] = "dead",
284 [PVR2_STATE_COLD] = "cold",
285 [PVR2_STATE_WARM] = "warm",
286 [PVR2_STATE_ERROR] = "error",
287 [PVR2_STATE_READY] = "ready",
288 [PVR2_STATE_RUN] = "run",
289 };
290
291
292 struct pvr2_fx2cmd_descdef {
293 unsigned char id;
294 unsigned char *desc;
295 };
296
297 static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
298 {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
299 {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
300 {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
301 {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
302 {FX2CMD_REG_WRITE, "write encoder register"},
303 {FX2CMD_REG_READ, "read encoder register"},
304 {FX2CMD_MEMSEL, "encoder memsel"},
305 {FX2CMD_I2C_WRITE, "i2c write"},
306 {FX2CMD_I2C_READ, "i2c read"},
307 {FX2CMD_GET_USB_SPEED, "get USB speed"},
308 {FX2CMD_STREAMING_ON, "stream on"},
309 {FX2CMD_STREAMING_OFF, "stream off"},
310 {FX2CMD_FWPOST1, "fwpost1"},
311 {FX2CMD_POWER_OFF, "power off"},
312 {FX2CMD_POWER_ON, "power on"},
313 {FX2CMD_DEEP_RESET, "deep reset"},
314 {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
315 {FX2CMD_GET_IR_CODE, "get IR code"},
316 {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
317 {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
318 {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
319 {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
320 {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
321 {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
322 {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
323 };
324
325
326 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
327 static void pvr2_hdw_state_sched(struct pvr2_hdw *);
328 static int pvr2_hdw_state_eval(struct pvr2_hdw *);
329 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
330 static void pvr2_hdw_worker_poll(struct work_struct *work);
331 static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
332 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
333 static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
334 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
335 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
336 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
337 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
338 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
339 static void pvr2_hdw_quiescent_timeout(unsigned long);
340 static void pvr2_hdw_decoder_stabilization_timeout(unsigned long);
341 static void pvr2_hdw_encoder_wait_timeout(unsigned long);
342 static void pvr2_hdw_encoder_run_timeout(unsigned long);
343 static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
344 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
345 unsigned int timeout,int probe_fl,
346 void *write_data,unsigned int write_len,
347 void *read_data,unsigned int read_len);
348 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
349
350
351 static void trace_stbit(const char *name,int val)
352 {
353 pvr2_trace(PVR2_TRACE_STBITS,
354 "State bit %s <-- %s",
355 name,(val ? "true" : "false"));
356 }
357
358 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
359 {
360 struct pvr2_hdw *hdw = cptr->hdw;
361 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
362 *vp = hdw->freqTable[hdw->freqProgSlot-1];
363 } else {
364 *vp = 0;
365 }
366 return 0;
367 }
368
369 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
370 {
371 struct pvr2_hdw *hdw = cptr->hdw;
372 unsigned int slotId = hdw->freqProgSlot;
373 if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
374 hdw->freqTable[slotId-1] = v;
375 /* Handle side effects correctly - if we're tuned to this
376 slot, then forgot the slot id relation since the stored
377 frequency has been changed. */
378 if (hdw->freqSelector) {
379 if (hdw->freqSlotRadio == slotId) {
380 hdw->freqSlotRadio = 0;
381 }
382 } else {
383 if (hdw->freqSlotTelevision == slotId) {
384 hdw->freqSlotTelevision = 0;
385 }
386 }
387 }
388 return 0;
389 }
390
391 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
392 {
393 *vp = cptr->hdw->freqProgSlot;
394 return 0;
395 }
396
397 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
398 {
399 struct pvr2_hdw *hdw = cptr->hdw;
400 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
401 hdw->freqProgSlot = v;
402 }
403 return 0;
404 }
405
406 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
407 {
408 struct pvr2_hdw *hdw = cptr->hdw;
409 *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
410 return 0;
411 }
412
413 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
414 {
415 unsigned freq = 0;
416 struct pvr2_hdw *hdw = cptr->hdw;
417 if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
418 if (slotId > 0) {
419 freq = hdw->freqTable[slotId-1];
420 if (!freq) return 0;
421 pvr2_hdw_set_cur_freq(hdw,freq);
422 }
423 if (hdw->freqSelector) {
424 hdw->freqSlotRadio = slotId;
425 } else {
426 hdw->freqSlotTelevision = slotId;
427 }
428 return 0;
429 }
430
431 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
432 {
433 *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
434 return 0;
435 }
436
437 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
438 {
439 return cptr->hdw->freqDirty != 0;
440 }
441
442 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
443 {
444 cptr->hdw->freqDirty = 0;
445 }
446
447 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
448 {
449 pvr2_hdw_set_cur_freq(cptr->hdw,v);
450 return 0;
451 }
452
453 static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
454 {
455 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
456 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
457 if (stat != 0) {
458 return stat;
459 }
460 *left = cap->bounds.left;
461 return 0;
462 }
463
464 static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
465 {
466 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
467 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
468 if (stat != 0) {
469 return stat;
470 }
471 *left = cap->bounds.left;
472 if (cap->bounds.width > cptr->hdw->cropw_val) {
473 *left += cap->bounds.width - cptr->hdw->cropw_val;
474 }
475 return 0;
476 }
477
478 static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
479 {
480 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
481 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
482 if (stat != 0) {
483 return stat;
484 }
485 *top = cap->bounds.top;
486 return 0;
487 }
488
489 static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
490 {
491 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
492 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
493 if (stat != 0) {
494 return stat;
495 }
496 *top = cap->bounds.top;
497 if (cap->bounds.height > cptr->hdw->croph_val) {
498 *top += cap->bounds.height - cptr->hdw->croph_val;
499 }
500 return 0;
501 }
502
503 static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *width)
504 {
505 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
506 int stat, bleftend, cleft;
507
508 stat = pvr2_hdw_check_cropcap(cptr->hdw);
509 if (stat != 0) {
510 return stat;
511 }
512 bleftend = cap->bounds.left+cap->bounds.width;
513 cleft = cptr->hdw->cropl_val;
514
515 *width = cleft < bleftend ? bleftend-cleft : 0;
516 return 0;
517 }
518
519 static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *height)
520 {
521 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
522 int stat, btopend, ctop;
523
524 stat = pvr2_hdw_check_cropcap(cptr->hdw);
525 if (stat != 0) {
526 return stat;
527 }
528 btopend = cap->bounds.top+cap->bounds.height;
529 ctop = cptr->hdw->cropt_val;
530
531 *height = ctop < btopend ? btopend-ctop : 0;
532 return 0;
533 }
534
535 static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
536 {
537 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
538 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
539 if (stat != 0) {
540 return stat;
541 }
542 *val = cap->bounds.left;
543 return 0;
544 }
545
546 static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
547 {
548 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
549 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
550 if (stat != 0) {
551 return stat;
552 }
553 *val = cap->bounds.top;
554 return 0;
555 }
556
557 static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
558 {
559 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
560 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
561 if (stat != 0) {
562 return stat;
563 }
564 *val = cap->bounds.width;
565 return 0;
566 }
567
568 static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
569 {
570 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
571 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
572 if (stat != 0) {
573 return stat;
574 }
575 *val = cap->bounds.height;
576 return 0;
577 }
578
579 static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
580 {
581 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
582 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
583 if (stat != 0) {
584 return stat;
585 }
586 *val = cap->defrect.left;
587 return 0;
588 }
589
590 static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
591 {
592 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
593 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
594 if (stat != 0) {
595 return stat;
596 }
597 *val = cap->defrect.top;
598 return 0;
599 }
600
601 static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
602 {
603 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
604 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
605 if (stat != 0) {
606 return stat;
607 }
608 *val = cap->defrect.width;
609 return 0;
610 }
611
612 static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
613 {
614 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
615 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
616 if (stat != 0) {
617 return stat;
618 }
619 *val = cap->defrect.height;
620 return 0;
621 }
622
623 static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
624 {
625 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
626 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
627 if (stat != 0) {
628 return stat;
629 }
630 *val = cap->pixelaspect.numerator;
631 return 0;
632 }
633
634 static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
635 {
636 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
637 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
638 if (stat != 0) {
639 return stat;
640 }
641 *val = cap->pixelaspect.denominator;
642 return 0;
643 }
644
645 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
646 {
647 /* Actual maximum depends on the video standard in effect. */
648 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
649 *vp = 480;
650 } else {
651 *vp = 576;
652 }
653 return 0;
654 }
655
656 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
657 {
658 /* Actual minimum depends on device digitizer type. */
659 if (cptr->hdw->hdw_desc->flag_has_cx25840) {
660 *vp = 75;
661 } else {
662 *vp = 17;
663 }
664 return 0;
665 }
666
667 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
668 {
669 *vp = cptr->hdw->input_val;
670 return 0;
671 }
672
673 static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
674 {
675 return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
676 }
677
678 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
679 {
680 return pvr2_hdw_set_input(cptr->hdw,v);
681 }
682
683 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
684 {
685 return cptr->hdw->input_dirty != 0;
686 }
687
688 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
689 {
690 cptr->hdw->input_dirty = 0;
691 }
692
693
694 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
695 {
696 unsigned long fv;
697 struct pvr2_hdw *hdw = cptr->hdw;
698 if (hdw->tuner_signal_stale) {
699 pvr2_hdw_status_poll(hdw);
700 }
701 fv = hdw->tuner_signal_info.rangehigh;
702 if (!fv) {
703 /* Safety fallback */
704 *vp = TV_MAX_FREQ;
705 return 0;
706 }
707 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
708 fv = (fv * 125) / 2;
709 } else {
710 fv = fv * 62500;
711 }
712 *vp = fv;
713 return 0;
714 }
715
716 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
717 {
718 unsigned long fv;
719 struct pvr2_hdw *hdw = cptr->hdw;
720 if (hdw->tuner_signal_stale) {
721 pvr2_hdw_status_poll(hdw);
722 }
723 fv = hdw->tuner_signal_info.rangelow;
724 if (!fv) {
725 /* Safety fallback */
726 *vp = TV_MIN_FREQ;
727 return 0;
728 }
729 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
730 fv = (fv * 125) / 2;
731 } else {
732 fv = fv * 62500;
733 }
734 *vp = fv;
735 return 0;
736 }
737
738 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
739 {
740 return cptr->hdw->enc_stale != 0;
741 }
742
743 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
744 {
745 cptr->hdw->enc_stale = 0;
746 cptr->hdw->enc_unsafe_stale = 0;
747 }
748
749 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
750 {
751 int ret;
752 struct v4l2_ext_controls cs;
753 struct v4l2_ext_control c1;
754 memset(&cs,0,sizeof(cs));
755 memset(&c1,0,sizeof(c1));
756 cs.controls = &c1;
757 cs.count = 1;
758 c1.id = cptr->info->v4l_id;
759 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
760 VIDIOC_G_EXT_CTRLS);
761 if (ret) return ret;
762 *vp = c1.value;
763 return 0;
764 }
765
766 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
767 {
768 int ret;
769 struct pvr2_hdw *hdw = cptr->hdw;
770 struct v4l2_ext_controls cs;
771 struct v4l2_ext_control c1;
772 memset(&cs,0,sizeof(cs));
773 memset(&c1,0,sizeof(c1));
774 cs.controls = &c1;
775 cs.count = 1;
776 c1.id = cptr->info->v4l_id;
777 c1.value = v;
778 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
779 hdw->state_encoder_run, &cs,
780 VIDIOC_S_EXT_CTRLS);
781 if (ret == -EBUSY) {
782 /* Oops. cx2341x is telling us it's not safe to change
783 this control while we're capturing. Make a note of this
784 fact so that the pipeline will be stopped the next time
785 controls are committed. Then go on ahead and store this
786 change anyway. */
787 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
788 0, &cs,
789 VIDIOC_S_EXT_CTRLS);
790 if (!ret) hdw->enc_unsafe_stale = !0;
791 }
792 if (ret) return ret;
793 hdw->enc_stale = !0;
794 return 0;
795 }
796
797 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
798 {
799 struct v4l2_queryctrl qctrl;
800 struct pvr2_ctl_info *info;
801 qctrl.id = cptr->info->v4l_id;
802 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
803 /* Strip out the const so we can adjust a function pointer. It's
804 OK to do this here because we know this is a dynamically created
805 control, so the underlying storage for the info pointer is (a)
806 private to us, and (b) not in read-only storage. Either we do
807 this or we significantly complicate the underlying control
808 implementation. */
809 info = (struct pvr2_ctl_info *)(cptr->info);
810 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
811 if (info->set_value) {
812 info->set_value = NULL;
813 }
814 } else {
815 if (!(info->set_value)) {
816 info->set_value = ctrl_cx2341x_set;
817 }
818 }
819 return qctrl.flags;
820 }
821
822 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
823 {
824 *vp = cptr->hdw->state_pipeline_req;
825 return 0;
826 }
827
828 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
829 {
830 *vp = cptr->hdw->master_state;
831 return 0;
832 }
833
834 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
835 {
836 int result = pvr2_hdw_is_hsm(cptr->hdw);
837 *vp = PVR2_CVAL_HSM_FULL;
838 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
839 if (result) *vp = PVR2_CVAL_HSM_HIGH;
840 return 0;
841 }
842
843 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
844 {
845 *vp = cptr->hdw->std_mask_avail;
846 return 0;
847 }
848
849 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
850 {
851 struct pvr2_hdw *hdw = cptr->hdw;
852 v4l2_std_id ns;
853 ns = hdw->std_mask_avail;
854 ns = (ns & ~m) | (v & m);
855 if (ns == hdw->std_mask_avail) return 0;
856 hdw->std_mask_avail = ns;
857 pvr2_hdw_internal_set_std_avail(hdw);
858 pvr2_hdw_internal_find_stdenum(hdw);
859 return 0;
860 }
861
862 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
863 char *bufPtr,unsigned int bufSize,
864 unsigned int *len)
865 {
866 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
867 return 0;
868 }
869
870 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
871 const char *bufPtr,unsigned int bufSize,
872 int *mskp,int *valp)
873 {
874 int ret;
875 v4l2_std_id id;
876 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
877 if (ret < 0) return ret;
878 if (mskp) *mskp = id;
879 if (valp) *valp = id;
880 return 0;
881 }
882
883 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
884 {
885 *vp = cptr->hdw->std_mask_cur;
886 return 0;
887 }
888
889 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
890 {
891 struct pvr2_hdw *hdw = cptr->hdw;
892 v4l2_std_id ns;
893 ns = hdw->std_mask_cur;
894 ns = (ns & ~m) | (v & m);
895 if (ns == hdw->std_mask_cur) return 0;
896 hdw->std_mask_cur = ns;
897 hdw->std_dirty = !0;
898 pvr2_hdw_internal_find_stdenum(hdw);
899 return 0;
900 }
901
902 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
903 {
904 return cptr->hdw->std_dirty != 0;
905 }
906
907 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
908 {
909 cptr->hdw->std_dirty = 0;
910 }
911
912 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
913 {
914 struct pvr2_hdw *hdw = cptr->hdw;
915 pvr2_hdw_status_poll(hdw);
916 *vp = hdw->tuner_signal_info.signal;
917 return 0;
918 }
919
920 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
921 {
922 int val = 0;
923 unsigned int subchan;
924 struct pvr2_hdw *hdw = cptr->hdw;
925 pvr2_hdw_status_poll(hdw);
926 subchan = hdw->tuner_signal_info.rxsubchans;
927 if (subchan & V4L2_TUNER_SUB_MONO) {
928 val |= (1 << V4L2_TUNER_MODE_MONO);
929 }
930 if (subchan & V4L2_TUNER_SUB_STEREO) {
931 val |= (1 << V4L2_TUNER_MODE_STEREO);
932 }
933 if (subchan & V4L2_TUNER_SUB_LANG1) {
934 val |= (1 << V4L2_TUNER_MODE_LANG1);
935 }
936 if (subchan & V4L2_TUNER_SUB_LANG2) {
937 val |= (1 << V4L2_TUNER_MODE_LANG2);
938 }
939 *vp = val;
940 return 0;
941 }
942
943
944 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
945 {
946 struct pvr2_hdw *hdw = cptr->hdw;
947 if (v < 0) return -EINVAL;
948 if (v > hdw->std_enum_cnt) return -EINVAL;
949 hdw->std_enum_cur = v;
950 if (!v) return 0;
951 v--;
952 if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
953 hdw->std_mask_cur = hdw->std_defs[v].id;
954 hdw->std_dirty = !0;
955 return 0;
956 }
957
958
959 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
960 {
961 *vp = cptr->hdw->std_enum_cur;
962 return 0;
963 }
964
965
966 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
967 {
968 return cptr->hdw->std_dirty != 0;
969 }
970
971
972 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
973 {
974 cptr->hdw->std_dirty = 0;
975 }
976
977
978 #define DEFINT(vmin,vmax) \
979 .type = pvr2_ctl_int, \
980 .def.type_int.min_value = vmin, \
981 .def.type_int.max_value = vmax
982
983 #define DEFENUM(tab) \
984 .type = pvr2_ctl_enum, \
985 .def.type_enum.count = ARRAY_SIZE(tab), \
986 .def.type_enum.value_names = tab
987
988 #define DEFBOOL \
989 .type = pvr2_ctl_bool
990
991 #define DEFMASK(msk,tab) \
992 .type = pvr2_ctl_bitmask, \
993 .def.type_bitmask.valid_bits = msk, \
994 .def.type_bitmask.bit_names = tab
995
996 #define DEFREF(vname) \
997 .set_value = ctrl_set_##vname, \
998 .get_value = ctrl_get_##vname, \
999 .is_dirty = ctrl_isdirty_##vname, \
1000 .clear_dirty = ctrl_cleardirty_##vname
1001
1002
1003 #define VCREATE_FUNCS(vname) \
1004 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
1005 {*vp = cptr->hdw->vname##_val; return 0;} \
1006 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
1007 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
1008 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
1009 {return cptr->hdw->vname##_dirty != 0;} \
1010 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
1011 {cptr->hdw->vname##_dirty = 0;}
1012
1013 VCREATE_FUNCS(brightness)
1014 VCREATE_FUNCS(contrast)
1015 VCREATE_FUNCS(saturation)
1016 VCREATE_FUNCS(hue)
1017 VCREATE_FUNCS(volume)
1018 VCREATE_FUNCS(balance)
1019 VCREATE_FUNCS(bass)
1020 VCREATE_FUNCS(treble)
1021 VCREATE_FUNCS(mute)
1022 VCREATE_FUNCS(cropl)
1023 VCREATE_FUNCS(cropt)
1024 VCREATE_FUNCS(cropw)
1025 VCREATE_FUNCS(croph)
1026 VCREATE_FUNCS(audiomode)
1027 VCREATE_FUNCS(res_hor)
1028 VCREATE_FUNCS(res_ver)
1029 VCREATE_FUNCS(srate)
1030
1031 /* Table definition of all controls which can be manipulated */
1032 static const struct pvr2_ctl_info control_defs[] = {
1033 {
1034 .v4l_id = V4L2_CID_BRIGHTNESS,
1035 .desc = "Brightness",
1036 .name = "brightness",
1037 .default_value = 128,
1038 DEFREF(brightness),
1039 DEFINT(0,255),
1040 },{
1041 .v4l_id = V4L2_CID_CONTRAST,
1042 .desc = "Contrast",
1043 .name = "contrast",
1044 .default_value = 68,
1045 DEFREF(contrast),
1046 DEFINT(0,127),
1047 },{
1048 .v4l_id = V4L2_CID_SATURATION,
1049 .desc = "Saturation",
1050 .name = "saturation",
1051 .default_value = 64,
1052 DEFREF(saturation),
1053 DEFINT(0,127),
1054 },{
1055 .v4l_id = V4L2_CID_HUE,
1056 .desc = "Hue",
1057 .name = "hue",
1058 .default_value = 0,
1059 DEFREF(hue),
1060 DEFINT(-128,127),
1061 },{
1062 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1063 .desc = "Volume",
1064 .name = "volume",
1065 .default_value = 62000,
1066 DEFREF(volume),
1067 DEFINT(0,65535),
1068 },{
1069 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1070 .desc = "Balance",
1071 .name = "balance",
1072 .default_value = 0,
1073 DEFREF(balance),
1074 DEFINT(-32768,32767),
1075 },{
1076 .v4l_id = V4L2_CID_AUDIO_BASS,
1077 .desc = "Bass",
1078 .name = "bass",
1079 .default_value = 0,
1080 DEFREF(bass),
1081 DEFINT(-32768,32767),
1082 },{
1083 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1084 .desc = "Treble",
1085 .name = "treble",
1086 .default_value = 0,
1087 DEFREF(treble),
1088 DEFINT(-32768,32767),
1089 },{
1090 .v4l_id = V4L2_CID_AUDIO_MUTE,
1091 .desc = "Mute",
1092 .name = "mute",
1093 .default_value = 0,
1094 DEFREF(mute),
1095 DEFBOOL,
1096 }, {
1097 .desc = "Capture crop left margin",
1098 .name = "crop_left",
1099 .internal_id = PVR2_CID_CROPL,
1100 .default_value = 0,
1101 DEFREF(cropl),
1102 DEFINT(-129, 340),
1103 .get_min_value = ctrl_cropl_min_get,
1104 .get_max_value = ctrl_cropl_max_get,
1105 .get_def_value = ctrl_get_cropcapdl,
1106 }, {
1107 .desc = "Capture crop top margin",
1108 .name = "crop_top",
1109 .internal_id = PVR2_CID_CROPT,
1110 .default_value = 0,
1111 DEFREF(cropt),
1112 DEFINT(-35, 544),
1113 .get_min_value = ctrl_cropt_min_get,
1114 .get_max_value = ctrl_cropt_max_get,
1115 .get_def_value = ctrl_get_cropcapdt,
1116 }, {
1117 .desc = "Capture crop width",
1118 .name = "crop_width",
1119 .internal_id = PVR2_CID_CROPW,
1120 .default_value = 720,
1121 DEFREF(cropw),
1122 DEFINT(0, 864),
1123 .get_max_value = ctrl_cropw_max_get,
1124 .get_def_value = ctrl_get_cropcapdw,
1125 }, {
1126 .desc = "Capture crop height",
1127 .name = "crop_height",
1128 .internal_id = PVR2_CID_CROPH,
1129 .default_value = 480,
1130 DEFREF(croph),
1131 DEFINT(0, 576),
1132 .get_max_value = ctrl_croph_max_get,
1133 .get_def_value = ctrl_get_cropcapdh,
1134 }, {
1135 .desc = "Capture capability pixel aspect numerator",
1136 .name = "cropcap_pixel_numerator",
1137 .internal_id = PVR2_CID_CROPCAPPAN,
1138 .get_value = ctrl_get_cropcappan,
1139 }, {
1140 .desc = "Capture capability pixel aspect denominator",
1141 .name = "cropcap_pixel_denominator",
1142 .internal_id = PVR2_CID_CROPCAPPAD,
1143 .get_value = ctrl_get_cropcappad,
1144 }, {
1145 .desc = "Capture capability bounds top",
1146 .name = "cropcap_bounds_top",
1147 .internal_id = PVR2_CID_CROPCAPBT,
1148 .get_value = ctrl_get_cropcapbt,
1149 }, {
1150 .desc = "Capture capability bounds left",
1151 .name = "cropcap_bounds_left",
1152 .internal_id = PVR2_CID_CROPCAPBL,
1153 .get_value = ctrl_get_cropcapbl,
1154 }, {
1155 .desc = "Capture capability bounds width",
1156 .name = "cropcap_bounds_width",
1157 .internal_id = PVR2_CID_CROPCAPBW,
1158 .get_value = ctrl_get_cropcapbw,
1159 }, {
1160 .desc = "Capture capability bounds height",
1161 .name = "cropcap_bounds_height",
1162 .internal_id = PVR2_CID_CROPCAPBH,
1163 .get_value = ctrl_get_cropcapbh,
1164 },{
1165 .desc = "Video Source",
1166 .name = "input",
1167 .internal_id = PVR2_CID_INPUT,
1168 .default_value = PVR2_CVAL_INPUT_TV,
1169 .check_value = ctrl_check_input,
1170 DEFREF(input),
1171 DEFENUM(control_values_input),
1172 },{
1173 .desc = "Audio Mode",
1174 .name = "audio_mode",
1175 .internal_id = PVR2_CID_AUDIOMODE,
1176 .default_value = V4L2_TUNER_MODE_STEREO,
1177 DEFREF(audiomode),
1178 DEFENUM(control_values_audiomode),
1179 },{
1180 .desc = "Horizontal capture resolution",
1181 .name = "resolution_hor",
1182 .internal_id = PVR2_CID_HRES,
1183 .default_value = 720,
1184 DEFREF(res_hor),
1185 DEFINT(19,720),
1186 },{
1187 .desc = "Vertical capture resolution",
1188 .name = "resolution_ver",
1189 .internal_id = PVR2_CID_VRES,
1190 .default_value = 480,
1191 DEFREF(res_ver),
1192 DEFINT(17,576),
1193 /* Hook in check for video standard and adjust maximum
1194 depending on the standard. */
1195 .get_max_value = ctrl_vres_max_get,
1196 .get_min_value = ctrl_vres_min_get,
1197 },{
1198 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
1199 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1200 .desc = "Audio Sampling Frequency",
1201 .name = "srate",
1202 DEFREF(srate),
1203 DEFENUM(control_values_srate),
1204 },{
1205 .desc = "Tuner Frequency (Hz)",
1206 .name = "frequency",
1207 .internal_id = PVR2_CID_FREQUENCY,
1208 .default_value = 0,
1209 .set_value = ctrl_freq_set,
1210 .get_value = ctrl_freq_get,
1211 .is_dirty = ctrl_freq_is_dirty,
1212 .clear_dirty = ctrl_freq_clear_dirty,
1213 DEFINT(0,0),
1214 /* Hook in check for input value (tv/radio) and adjust
1215 max/min values accordingly */
1216 .get_max_value = ctrl_freq_max_get,
1217 .get_min_value = ctrl_freq_min_get,
1218 },{
1219 .desc = "Channel",
1220 .name = "channel",
1221 .set_value = ctrl_channel_set,
1222 .get_value = ctrl_channel_get,
1223 DEFINT(0,FREQTABLE_SIZE),
1224 },{
1225 .desc = "Channel Program Frequency",
1226 .name = "freq_table_value",
1227 .set_value = ctrl_channelfreq_set,
1228 .get_value = ctrl_channelfreq_get,
1229 DEFINT(0,0),
1230 /* Hook in check for input value (tv/radio) and adjust
1231 max/min values accordingly */
1232 .get_max_value = ctrl_freq_max_get,
1233 .get_min_value = ctrl_freq_min_get,
1234 },{
1235 .desc = "Channel Program ID",
1236 .name = "freq_table_channel",
1237 .set_value = ctrl_channelprog_set,
1238 .get_value = ctrl_channelprog_get,
1239 DEFINT(0,FREQTABLE_SIZE),
1240 },{
1241 .desc = "Streaming Enabled",
1242 .name = "streaming_enabled",
1243 .get_value = ctrl_streamingenabled_get,
1244 DEFBOOL,
1245 },{
1246 .desc = "USB Speed",
1247 .name = "usb_speed",
1248 .get_value = ctrl_hsm_get,
1249 DEFENUM(control_values_hsm),
1250 },{
1251 .desc = "Master State",
1252 .name = "master_state",
1253 .get_value = ctrl_masterstate_get,
1254 DEFENUM(pvr2_state_names),
1255 },{
1256 .desc = "Signal Present",
1257 .name = "signal_present",
1258 .get_value = ctrl_signal_get,
1259 DEFINT(0,65535),
1260 },{
1261 .desc = "Audio Modes Present",
1262 .name = "audio_modes_present",
1263 .get_value = ctrl_audio_modes_present_get,
1264 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1265 v4l. Nothing outside of this module cares about this,
1266 but I reuse it in order to also reuse the
1267 control_values_audiomode string table. */
1268 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1269 (1 << V4L2_TUNER_MODE_STEREO)|
1270 (1 << V4L2_TUNER_MODE_LANG1)|
1271 (1 << V4L2_TUNER_MODE_LANG2)),
1272 control_values_audiomode),
1273 },{
1274 .desc = "Video Standards Available Mask",
1275 .name = "video_standard_mask_available",
1276 .internal_id = PVR2_CID_STDAVAIL,
1277 .skip_init = !0,
1278 .get_value = ctrl_stdavail_get,
1279 .set_value = ctrl_stdavail_set,
1280 .val_to_sym = ctrl_std_val_to_sym,
1281 .sym_to_val = ctrl_std_sym_to_val,
1282 .type = pvr2_ctl_bitmask,
1283 },{
1284 .desc = "Video Standards In Use Mask",
1285 .name = "video_standard_mask_active",
1286 .internal_id = PVR2_CID_STDCUR,
1287 .skip_init = !0,
1288 .get_value = ctrl_stdcur_get,
1289 .set_value = ctrl_stdcur_set,
1290 .is_dirty = ctrl_stdcur_is_dirty,
1291 .clear_dirty = ctrl_stdcur_clear_dirty,
1292 .val_to_sym = ctrl_std_val_to_sym,
1293 .sym_to_val = ctrl_std_sym_to_val,
1294 .type = pvr2_ctl_bitmask,
1295 },{
1296 .desc = "Video Standard Name",
1297 .name = "video_standard",
1298 .internal_id = PVR2_CID_STDENUM,
1299 .skip_init = !0,
1300 .get_value = ctrl_stdenumcur_get,
1301 .set_value = ctrl_stdenumcur_set,
1302 .is_dirty = ctrl_stdenumcur_is_dirty,
1303 .clear_dirty = ctrl_stdenumcur_clear_dirty,
1304 .type = pvr2_ctl_enum,
1305 }
1306 };
1307
1308 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
1309
1310
1311 const char *pvr2_config_get_name(enum pvr2_config cfg)
1312 {
1313 switch (cfg) {
1314 case pvr2_config_empty: return "empty";
1315 case pvr2_config_mpeg: return "mpeg";
1316 case pvr2_config_vbi: return "vbi";
1317 case pvr2_config_pcm: return "pcm";
1318 case pvr2_config_rawvideo: return "raw video";
1319 }
1320 return "<unknown>";
1321 }
1322
1323
1324 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1325 {
1326 return hdw->usb_dev;
1327 }
1328
1329
1330 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1331 {
1332 return hdw->serial_number;
1333 }
1334
1335
1336 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1337 {
1338 return hdw->bus_info;
1339 }
1340
1341
1342 const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1343 {
1344 return hdw->identifier;
1345 }
1346
1347
1348 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1349 {
1350 return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1351 }
1352
1353 /* Set the currently tuned frequency and account for all possible
1354 driver-core side effects of this action. */
1355 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1356 {
1357 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1358 if (hdw->freqSelector) {
1359 /* Swing over to radio frequency selection */
1360 hdw->freqSelector = 0;
1361 hdw->freqDirty = !0;
1362 }
1363 if (hdw->freqValRadio != val) {
1364 hdw->freqValRadio = val;
1365 hdw->freqSlotRadio = 0;
1366 hdw->freqDirty = !0;
1367 }
1368 } else {
1369 if (!(hdw->freqSelector)) {
1370 /* Swing over to television frequency selection */
1371 hdw->freqSelector = 1;
1372 hdw->freqDirty = !0;
1373 }
1374 if (hdw->freqValTelevision != val) {
1375 hdw->freqValTelevision = val;
1376 hdw->freqSlotTelevision = 0;
1377 hdw->freqDirty = !0;
1378 }
1379 }
1380 }
1381
1382 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1383 {
1384 return hdw->unit_number;
1385 }
1386
1387
1388 /* Attempt to locate one of the given set of files. Messages are logged
1389 appropriate to what has been found. The return value will be 0 or
1390 greater on success (it will be the index of the file name found) and
1391 fw_entry will be filled in. Otherwise a negative error is returned on
1392 failure. If the return value is -ENOENT then no viable firmware file
1393 could be located. */
1394 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1395 const struct firmware **fw_entry,
1396 const char *fwtypename,
1397 unsigned int fwcount,
1398 const char *fwnames[])
1399 {
1400 unsigned int idx;
1401 int ret = -EINVAL;
1402 for (idx = 0; idx < fwcount; idx++) {
1403 ret = request_firmware(fw_entry,
1404 fwnames[idx],
1405 &hdw->usb_dev->dev);
1406 if (!ret) {
1407 trace_firmware("Located %s firmware: %s;"
1408 " uploading...",
1409 fwtypename,
1410 fwnames[idx]);
1411 return idx;
1412 }
1413 if (ret == -ENOENT) continue;
1414 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1415 "request_firmware fatal error with code=%d",ret);
1416 return ret;
1417 }
1418 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1419 "***WARNING***"
1420 " Device %s firmware"
1421 " seems to be missing.",
1422 fwtypename);
1423 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1424 "Did you install the pvrusb2 firmware files"
1425 " in their proper location?");
1426 if (fwcount == 1) {
1427 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1428 "request_firmware unable to locate %s file %s",
1429 fwtypename,fwnames[0]);
1430 } else {
1431 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1432 "request_firmware unable to locate"
1433 " one of the following %s files:",
1434 fwtypename);
1435 for (idx = 0; idx < fwcount; idx++) {
1436 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1437 "request_firmware: Failed to find %s",
1438 fwnames[idx]);
1439 }
1440 }
1441 return ret;
1442 }
1443
1444
1445 /*
1446 * pvr2_upload_firmware1().
1447 *
1448 * Send the 8051 firmware to the device. After the upload, arrange for
1449 * device to re-enumerate.
1450 *
1451 * NOTE : the pointer to the firmware data given by request_firmware()
1452 * is not suitable for an usb transaction.
1453 *
1454 */
1455 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1456 {
1457 const struct firmware *fw_entry = NULL;
1458 void *fw_ptr;
1459 unsigned int pipe;
1460 unsigned int fwsize;
1461 int ret;
1462 u16 address;
1463
1464 if (!hdw->hdw_desc->fx2_firmware.cnt) {
1465 hdw->fw1_state = FW1_STATE_OK;
1466 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1467 "Connected device type defines"
1468 " no firmware to upload; ignoring firmware");
1469 return -ENOTTY;
1470 }
1471
1472 hdw->fw1_state = FW1_STATE_FAILED; // default result
1473
1474 trace_firmware("pvr2_upload_firmware1");
1475
1476 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1477 hdw->hdw_desc->fx2_firmware.cnt,
1478 hdw->hdw_desc->fx2_firmware.lst);
1479 if (ret < 0) {
1480 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1481 return ret;
1482 }
1483
1484 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1485
1486 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1487 fwsize = fw_entry->size;
1488
1489 if ((fwsize != 0x2000) &&
1490 (!(hdw->hdw_desc->flag_fx2_16kb && (fwsize == 0x4000)))) {
1491 if (hdw->hdw_desc->flag_fx2_16kb) {
1492 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1493 "Wrong fx2 firmware size"
1494 " (expected 8192 or 16384, got %u)",
1495 fwsize);
1496 } else {
1497 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1498 "Wrong fx2 firmware size"
1499 " (expected 8192, got %u)",
1500 fwsize);
1501 }
1502 release_firmware(fw_entry);
1503 return -ENOMEM;
1504 }
1505
1506 fw_ptr = kmalloc(0x800, GFP_KERNEL);
1507 if (fw_ptr == NULL){
1508 release_firmware(fw_entry);
1509 return -ENOMEM;
1510 }
1511
1512 /* We have to hold the CPU during firmware upload. */
1513 pvr2_hdw_cpureset_assert(hdw,1);
1514
1515 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1516 chunk. */
1517
1518 ret = 0;
1519 for (address = 0; address < fwsize; address += 0x800) {
1520 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1521 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1522 0, fw_ptr, 0x800, HZ);
1523 }
1524
1525 trace_firmware("Upload done, releasing device's CPU");
1526
1527 /* Now release the CPU. It will disconnect and reconnect later. */
1528 pvr2_hdw_cpureset_assert(hdw,0);
1529
1530 kfree(fw_ptr);
1531 release_firmware(fw_entry);
1532
1533 trace_firmware("Upload done (%d bytes sent)",ret);
1534
1535 /* We should have written fwsize bytes */
1536 if (ret == fwsize) {
1537 hdw->fw1_state = FW1_STATE_RELOAD;
1538 return 0;
1539 }
1540
1541 return -EIO;
1542 }
1543
1544
1545 /*
1546 * pvr2_upload_firmware2()
1547 *
1548 * This uploads encoder firmware on endpoint 2.
1549 *
1550 */
1551
1552 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1553 {
1554 const struct firmware *fw_entry = NULL;
1555 void *fw_ptr;
1556 unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1557 int actual_length;
1558 int ret = 0;
1559 int fwidx;
1560 static const char *fw_files[] = {
1561 CX2341X_FIRM_ENC_FILENAME,
1562 };
1563
1564 if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1565 return 0;
1566 }
1567
1568 trace_firmware("pvr2_upload_firmware2");
1569
1570 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1571 ARRAY_SIZE(fw_files), fw_files);
1572 if (ret < 0) return ret;
1573 fwidx = ret;
1574 ret = 0;
1575 /* Since we're about to completely reinitialize the encoder,
1576 invalidate our cached copy of its configuration state. Next
1577 time we configure the encoder, then we'll fully configure it. */
1578 hdw->enc_cur_valid = 0;
1579
1580 /* Encoder is about to be reset so note that as far as we're
1581 concerned now, the encoder has never been run. */
1582 del_timer_sync(&hdw->encoder_run_timer);
1583 if (hdw->state_encoder_runok) {
1584 hdw->state_encoder_runok = 0;
1585 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1586 }
1587
1588 /* First prepare firmware loading */
1589 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1590 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1591 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1592 ret |= pvr2_hdw_cmd_deep_reset(hdw);
1593 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1594 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1595 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1596 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1597 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1598 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1599 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1600 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1601 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1602 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1603 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1604 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1605 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1606 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1607
1608 if (ret) {
1609 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1610 "firmware2 upload prep failed, ret=%d",ret);
1611 release_firmware(fw_entry);
1612 goto done;
1613 }
1614
1615 /* Now send firmware */
1616
1617 fw_len = fw_entry->size;
1618
1619 if (fw_len % sizeof(u32)) {
1620 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1621 "size of %s firmware"
1622 " must be a multiple of %zu bytes",
1623 fw_files[fwidx],sizeof(u32));
1624 release_firmware(fw_entry);
1625 ret = -EINVAL;
1626 goto done;
1627 }
1628
1629 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1630 if (fw_ptr == NULL){
1631 release_firmware(fw_entry);
1632 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1633 "failed to allocate memory for firmware2 upload");
1634 ret = -ENOMEM;
1635 goto done;
1636 }
1637
1638 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1639
1640 fw_done = 0;
1641 for (fw_done = 0; fw_done < fw_len;) {
1642 bcnt = fw_len - fw_done;
1643 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1644 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1645 /* Usbsnoop log shows that we must swap bytes... */
1646 /* Some background info: The data being swapped here is a
1647 firmware image destined for the mpeg encoder chip that
1648 lives at the other end of a USB endpoint. The encoder
1649 chip always talks in 32 bit chunks and its storage is
1650 organized into 32 bit words. However from the file
1651 system to the encoder chip everything is purely a byte
1652 stream. The firmware file's contents are always 32 bit
1653 swapped from what the encoder expects. Thus the need
1654 always exists to swap the bytes regardless of the endian
1655 type of the host processor and therefore swab32() makes
1656 the most sense. */
1657 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1658 ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
1659
1660 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1661 &actual_length, HZ);
1662 ret |= (actual_length != bcnt);
1663 if (ret) break;
1664 fw_done += bcnt;
1665 }
1666
1667 trace_firmware("upload of %s : %i / %i ",
1668 fw_files[fwidx],fw_done,fw_len);
1669
1670 kfree(fw_ptr);
1671 release_firmware(fw_entry);
1672
1673 if (ret) {
1674 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1675 "firmware2 upload transfer failure");
1676 goto done;
1677 }
1678
1679 /* Finish upload */
1680
1681 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1682 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1683 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1684
1685 if (ret) {
1686 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1687 "firmware2 upload post-proc failure");
1688 }
1689
1690 done:
1691 if (hdw->hdw_desc->signal_routing_scheme ==
1692 PVR2_ROUTING_SCHEME_GOTVIEW) {
1693 /* Ensure that GPIO 11 is set to output for GOTVIEW
1694 hardware. */
1695 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1696 }
1697 return ret;
1698 }
1699
1700
1701 static const char *pvr2_get_state_name(unsigned int st)
1702 {
1703 if (st < ARRAY_SIZE(pvr2_state_names)) {
1704 return pvr2_state_names[st];
1705 }
1706 return "???";
1707 }
1708
1709 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1710 {
1711 /* Even though we really only care about the video decoder chip at
1712 this point, we'll broadcast stream on/off to all sub-devices
1713 anyway, just in case somebody else wants to hear the
1714 command... */
1715 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 stream=%s",
1716 (enablefl ? "on" : "off"));
1717 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
1718 v4l2_device_call_all(&hdw->v4l2_dev, 0, audio, s_stream, enablefl);
1719 if (hdw->decoder_client_id) {
1720 /* We get here if the encoder has been noticed. Otherwise
1721 we'll issue a warning to the user (which should
1722 normally never happen). */
1723 return 0;
1724 }
1725 if (!hdw->flag_decoder_missed) {
1726 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1727 "WARNING: No decoder present");
1728 hdw->flag_decoder_missed = !0;
1729 trace_stbit("flag_decoder_missed",
1730 hdw->flag_decoder_missed);
1731 }
1732 return -EIO;
1733 }
1734
1735
1736 int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1737 {
1738 return hdw->master_state;
1739 }
1740
1741
1742 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1743 {
1744 if (!hdw->flag_tripped) return 0;
1745 hdw->flag_tripped = 0;
1746 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1747 "Clearing driver error statuss");
1748 return !0;
1749 }
1750
1751
1752 int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1753 {
1754 int fl;
1755 LOCK_TAKE(hdw->big_lock); do {
1756 fl = pvr2_hdw_untrip_unlocked(hdw);
1757 } while (0); LOCK_GIVE(hdw->big_lock);
1758 if (fl) pvr2_hdw_state_sched(hdw);
1759 return 0;
1760 }
1761
1762
1763
1764
1765 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1766 {
1767 return hdw->state_pipeline_req != 0;
1768 }
1769
1770
1771 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1772 {
1773 int ret,st;
1774 LOCK_TAKE(hdw->big_lock); do {
1775 pvr2_hdw_untrip_unlocked(hdw);
1776 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1777 hdw->state_pipeline_req = enable_flag != 0;
1778 pvr2_trace(PVR2_TRACE_START_STOP,
1779 "/*--TRACE_STREAM--*/ %s",
1780 enable_flag ? "enable" : "disable");
1781 }
1782 pvr2_hdw_state_sched(hdw);
1783 } while (0); LOCK_GIVE(hdw->big_lock);
1784 if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1785 if (enable_flag) {
1786 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1787 if (st != PVR2_STATE_READY) return -EIO;
1788 if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1789 }
1790 }
1791 return 0;
1792 }
1793
1794
1795 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1796 {
1797 int fl;
1798 LOCK_TAKE(hdw->big_lock);
1799 if ((fl = (hdw->desired_stream_type != config)) != 0) {
1800 hdw->desired_stream_type = config;
1801 hdw->state_pipeline_config = 0;
1802 trace_stbit("state_pipeline_config",
1803 hdw->state_pipeline_config);
1804 pvr2_hdw_state_sched(hdw);
1805 }
1806 LOCK_GIVE(hdw->big_lock);
1807 if (fl) return 0;
1808 return pvr2_hdw_wait(hdw,0);
1809 }
1810
1811
1812 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1813 {
1814 int unit_number = hdw->unit_number;
1815 int tp = -1;
1816 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1817 tp = tuner[unit_number];
1818 }
1819 if (tp < 0) return -EINVAL;
1820 hdw->tuner_type = tp;
1821 hdw->tuner_updated = !0;
1822 return 0;
1823 }
1824
1825
1826 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1827 {
1828 int unit_number = hdw->unit_number;
1829 int tp = 0;
1830 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1831 tp = video_std[unit_number];
1832 if (tp) return tp;
1833 }
1834 return 0;
1835 }
1836
1837
1838 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1839 {
1840 int unit_number = hdw->unit_number;
1841 int tp = 0;
1842 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1843 tp = tolerance[unit_number];
1844 }
1845 return tp;
1846 }
1847
1848
1849 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1850 {
1851 /* Try a harmless request to fetch the eeprom's address over
1852 endpoint 1. See what happens. Only the full FX2 image can
1853 respond to this. If this probe fails then likely the FX2
1854 firmware needs be loaded. */
1855 int result;
1856 LOCK_TAKE(hdw->ctl_lock); do {
1857 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1858 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1859 hdw->cmd_buffer,1,
1860 hdw->cmd_buffer,1);
1861 if (result < 0) break;
1862 } while(0); LOCK_GIVE(hdw->ctl_lock);
1863 if (result) {
1864 pvr2_trace(PVR2_TRACE_INIT,
1865 "Probe of device endpoint 1 result status %d",
1866 result);
1867 } else {
1868 pvr2_trace(PVR2_TRACE_INIT,
1869 "Probe of device endpoint 1 succeeded");
1870 }
1871 return result == 0;
1872 }
1873
1874 struct pvr2_std_hack {
1875 v4l2_std_id pat; /* Pattern to match */
1876 v4l2_std_id msk; /* Which bits we care about */
1877 v4l2_std_id std; /* What additional standards or default to set */
1878 };
1879
1880 /* This data structure labels specific combinations of standards from
1881 tveeprom that we'll try to recognize. If we recognize one, then assume
1882 a specified default standard to use. This is here because tveeprom only
1883 tells us about available standards not the intended default standard (if
1884 any) for the device in question. We guess the default based on what has
1885 been reported as available. Note that this is only for guessing a
1886 default - which can always be overridden explicitly - and if the user
1887 has otherwise named a default then that default will always be used in
1888 place of this table. */
1889 static const struct pvr2_std_hack std_eeprom_maps[] = {
1890 { /* PAL(B/G) */
1891 .pat = V4L2_STD_B|V4L2_STD_GH,
1892 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1893 },
1894 { /* NTSC(M) */
1895 .pat = V4L2_STD_MN,
1896 .std = V4L2_STD_NTSC_M,
1897 },
1898 { /* PAL(I) */
1899 .pat = V4L2_STD_PAL_I,
1900 .std = V4L2_STD_PAL_I,
1901 },
1902 { /* SECAM(L/L') */
1903 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1904 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1905 },
1906 { /* PAL(D/D1/K) */
1907 .pat = V4L2_STD_DK,
1908 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1909 },
1910 };
1911
1912 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1913 {
1914 char buf[40];
1915 unsigned int bcnt;
1916 v4l2_std_id std1,std2,std3;
1917
1918 std1 = get_default_standard(hdw);
1919 std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1920
1921 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1922 pvr2_trace(PVR2_TRACE_STD,
1923 "Supported video standard(s) reported available"
1924 " in hardware: %.*s",
1925 bcnt,buf);
1926
1927 hdw->std_mask_avail = hdw->std_mask_eeprom;
1928
1929 std2 = (std1|std3) & ~hdw->std_mask_avail;
1930 if (std2) {
1931 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1932 pvr2_trace(PVR2_TRACE_STD,
1933 "Expanding supported video standards"
1934 " to include: %.*s",
1935 bcnt,buf);
1936 hdw->std_mask_avail |= std2;
1937 }
1938
1939 pvr2_hdw_internal_set_std_avail(hdw);
1940
1941 if (std1) {
1942 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1943 pvr2_trace(PVR2_TRACE_STD,
1944 "Initial video standard forced to %.*s",
1945 bcnt,buf);
1946 hdw->std_mask_cur = std1;
1947 hdw->std_dirty = !0;
1948 pvr2_hdw_internal_find_stdenum(hdw);
1949 return;
1950 }
1951 if (std3) {
1952 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1953 pvr2_trace(PVR2_TRACE_STD,
1954 "Initial video standard"
1955 " (determined by device type): %.*s",bcnt,buf);
1956 hdw->std_mask_cur = std3;
1957 hdw->std_dirty = !0;
1958 pvr2_hdw_internal_find_stdenum(hdw);
1959 return;
1960 }
1961
1962 {
1963 unsigned int idx;
1964 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1965 if (std_eeprom_maps[idx].msk ?
1966 ((std_eeprom_maps[idx].pat ^
1967 hdw->std_mask_eeprom) &
1968 std_eeprom_maps[idx].msk) :
1969 (std_eeprom_maps[idx].pat !=
1970 hdw->std_mask_eeprom)) continue;
1971 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1972 std_eeprom_maps[idx].std);
1973 pvr2_trace(PVR2_TRACE_STD,
1974 "Initial video standard guessed as %.*s",
1975 bcnt,buf);
1976 hdw->std_mask_cur = std_eeprom_maps[idx].std;
1977 hdw->std_dirty = !0;
1978 pvr2_hdw_internal_find_stdenum(hdw);
1979 return;
1980 }
1981 }
1982
1983 if (hdw->std_enum_cnt > 1) {
1984 // Autoselect the first listed standard
1985 hdw->std_enum_cur = 1;
1986 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1987 hdw->std_dirty = !0;
1988 pvr2_trace(PVR2_TRACE_STD,
1989 "Initial video standard auto-selected to %s",
1990 hdw->std_defs[hdw->std_enum_cur-1].name);
1991 return;
1992 }
1993
1994 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1995 "Unable to select a viable initial video standard");
1996 }
1997
1998
1999 static unsigned int pvr2_copy_i2c_addr_list(
2000 unsigned short *dst, const unsigned char *src,
2001 unsigned int dst_max)
2002 {
2003 unsigned int cnt = 0;
2004 if (!src) return 0;
2005 while (src[cnt] && (cnt + 1) < dst_max) {
2006 dst[cnt] = src[cnt];
2007 cnt++;
2008 }
2009 dst[cnt] = I2C_CLIENT_END;
2010 return cnt;
2011 }
2012
2013
2014 static void pvr2_hdw_cx25840_vbi_hack(struct pvr2_hdw *hdw)
2015 {
2016 /*
2017 Mike Isely <isely@pobox.com> 19-Nov-2006 - This bit of nuttiness
2018 for cx25840 causes that module to correctly set up its video
2019 scaling. This is really a problem in the cx25840 module itself,
2020 but we work around it here. The problem has not been seen in
2021 ivtv because there VBI is supported and set up. We don't do VBI
2022 here (at least not yet) and thus we never attempted to even set
2023 it up.
2024 */
2025 struct v4l2_format fmt;
2026 if (hdw->decoder_client_id != PVR2_CLIENT_ID_CX25840) {
2027 /* We're not using a cx25840 so don't enable the hack */
2028 return;
2029 }
2030
2031 pvr2_trace(PVR2_TRACE_INIT,
2032 "Module ID %u:"
2033 " Executing cx25840 VBI hack",
2034 hdw->decoder_client_id);
2035 memset(&fmt, 0, sizeof(fmt));
2036 fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
2037 fmt.fmt.sliced.service_lines[0][21] = V4L2_SLICED_CAPTION_525;
2038 fmt.fmt.sliced.service_lines[1][21] = V4L2_SLICED_CAPTION_525;
2039 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
2040 vbi, s_sliced_fmt, &fmt.fmt.sliced);
2041 }
2042
2043
2044 static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
2045 const struct pvr2_device_client_desc *cd)
2046 {
2047 const char *fname;
2048 unsigned char mid;
2049 struct v4l2_subdev *sd;
2050 unsigned int i2ccnt;
2051 const unsigned char *p;
2052 /* Arbitrary count - max # i2c addresses we will probe */
2053 unsigned short i2caddr[25];
2054
2055 mid = cd->module_id;
2056 fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
2057 if (!fname) {
2058 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2059 "Module ID %u for device %s has no name?"
2060 " The driver might have a configuration problem.",
2061 mid,
2062 hdw->hdw_desc->description);
2063 return -EINVAL;
2064 }
2065 pvr2_trace(PVR2_TRACE_INIT,
2066 "Module ID %u (%s) for device %s being loaded...",
2067 mid, fname,
2068 hdw->hdw_desc->description);
2069
2070 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
2071 ARRAY_SIZE(i2caddr));
2072 if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2073 module_i2c_addresses[mid] : NULL) != NULL)) {
2074 /* Second chance: Try default i2c address list */
2075 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2076 ARRAY_SIZE(i2caddr));
2077 if (i2ccnt) {
2078 pvr2_trace(PVR2_TRACE_INIT,
2079 "Module ID %u:"
2080 " Using default i2c address list",
2081 mid);
2082 }
2083 }
2084
2085 if (!i2ccnt) {
2086 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2087 "Module ID %u (%s) for device %s:"
2088 " No i2c addresses."
2089 " The driver might have a configuration problem.",
2090 mid, fname, hdw->hdw_desc->description);
2091 return -EINVAL;
2092 }
2093
2094 if (i2ccnt == 1) {
2095 pvr2_trace(PVR2_TRACE_INIT,
2096 "Module ID %u:"
2097 " Setting up with specified i2c address 0x%x",
2098 mid, i2caddr[0]);
2099 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
2100 fname, i2caddr[0], NULL);
2101 } else {
2102 pvr2_trace(PVR2_TRACE_INIT,
2103 "Module ID %u:"
2104 " Setting up with address probe list",
2105 mid);
2106 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
2107 fname, 0, i2caddr);
2108 }
2109
2110 if (!sd) {
2111 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2112 "Module ID %u (%s) for device %s failed to load."
2113 " Possible missing sub-device kernel module or"
2114 " initialization failure within module.",
2115 mid, fname, hdw->hdw_desc->description);
2116 return -EIO;
2117 }
2118
2119 /* Tag this sub-device instance with the module ID we know about.
2120 In other places we'll use that tag to determine if the instance
2121 requires special handling. */
2122 sd->grp_id = mid;
2123
2124 pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname);
2125
2126
2127 /* client-specific setup... */
2128 switch (mid) {
2129 case PVR2_CLIENT_ID_CX25840:
2130 case PVR2_CLIENT_ID_SAA7115:
2131 hdw->decoder_client_id = mid;
2132 break;
2133 default: break;
2134 }
2135
2136 return 0;
2137 }
2138
2139
2140 static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2141 {
2142 unsigned int idx;
2143 const struct pvr2_string_table *cm;
2144 const struct pvr2_device_client_table *ct;
2145 int okFl = !0;
2146
2147 cm = &hdw->hdw_desc->client_modules;
2148 for (idx = 0; idx < cm->cnt; idx++) {
2149 request_module(cm->lst[idx]);
2150 }
2151
2152 ct = &hdw->hdw_desc->client_table;
2153 for (idx = 0; idx < ct->cnt; idx++) {
2154 if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0;
2155 }
2156 if (!okFl) {
2157 hdw->flag_modulefail = !0;
2158 pvr2_hdw_render_useless(hdw);
2159 }
2160 }
2161
2162
2163 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2164 {
2165 int ret;
2166 unsigned int idx;
2167 struct pvr2_ctrl *cptr;
2168 int reloadFl = 0;
2169 if (hdw->hdw_desc->fx2_firmware.cnt) {
2170 if (!reloadFl) {
2171 reloadFl =
2172 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2173 == 0);
2174 if (reloadFl) {
2175 pvr2_trace(PVR2_TRACE_INIT,
2176 "USB endpoint config looks strange"
2177 "; possibly firmware needs to be"
2178 " loaded");
2179 }
2180 }
2181 if (!reloadFl) {
2182 reloadFl = !pvr2_hdw_check_firmware(hdw);
2183 if (reloadFl) {
2184 pvr2_trace(PVR2_TRACE_INIT,
2185 "Check for FX2 firmware failed"
2186 "; possibly firmware needs to be"
2187 " loaded");
2188 }
2189 }
2190 if (reloadFl) {
2191 if (pvr2_upload_firmware1(hdw) != 0) {
2192 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2193 "Failure uploading firmware1");
2194 }
2195 return;
2196 }
2197 }
2198 hdw->fw1_state = FW1_STATE_OK;
2199
2200 if (!pvr2_hdw_dev_ok(hdw)) return;
2201
2202 hdw->force_dirty = !0;
2203
2204 if (!hdw->hdw_desc->flag_no_powerup) {
2205 pvr2_hdw_cmd_powerup(hdw);
2206 if (!pvr2_hdw_dev_ok(hdw)) return;
2207 }
2208
2209 /* Take the IR chip out of reset, if appropriate */
2210 if (hdw->ir_scheme_active == PVR2_IR_SCHEME_ZILOG) {
2211 pvr2_issue_simple_cmd(hdw,
2212 FX2CMD_HCW_ZILOG_RESET |
2213 (1 << 8) |
2214 ((0) << 16));
2215 }
2216
2217 // This step MUST happen after the earlier powerup step.
2218 pvr2_i2c_core_init(hdw);
2219 if (!pvr2_hdw_dev_ok(hdw)) return;
2220
2221 pvr2_hdw_load_modules(hdw);
2222 if (!pvr2_hdw_dev_ok(hdw)) return;
2223
2224 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, load_fw);
2225
2226 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2227 cptr = hdw->controls + idx;
2228 if (cptr->info->skip_init) continue;
2229 if (!cptr->info->set_value) continue;
2230 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2231 }
2232
2233 pvr2_hdw_cx25840_vbi_hack(hdw);
2234
2235 /* Set up special default values for the television and radio
2236 frequencies here. It's not really important what these defaults
2237 are, but I set them to something usable in the Chicago area just
2238 to make driver testing a little easier. */
2239
2240 hdw->freqValTelevision = default_tv_freq;
2241 hdw->freqValRadio = default_radio_freq;
2242
2243 // Do not use pvr2_reset_ctl_endpoints() here. It is not
2244 // thread-safe against the normal pvr2_send_request() mechanism.
2245 // (We should make it thread safe).
2246
2247 if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2248 ret = pvr2_hdw_get_eeprom_addr(hdw);
2249 if (!pvr2_hdw_dev_ok(hdw)) return;
2250 if (ret < 0) {
2251 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2252 "Unable to determine location of eeprom,"
2253 " skipping");
2254 } else {
2255 hdw->eeprom_addr = ret;
2256 pvr2_eeprom_analyze(hdw);
2257 if (!pvr2_hdw_dev_ok(hdw)) return;
2258 }
2259 } else {
2260 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2261 hdw->tuner_updated = !0;
2262 hdw->std_mask_eeprom = V4L2_STD_ALL;
2263 }
2264
2265 if (hdw->serial_number) {
2266 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2267 "sn-%lu", hdw->serial_number);
2268 } else if (hdw->unit_number >= 0) {
2269 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2270 "unit-%c",
2271 hdw->unit_number + 'a');
2272 } else {
2273 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2274 "unit-??");
2275 }
2276 hdw->identifier[idx] = 0;
2277
2278 pvr2_hdw_setup_std(hdw);
2279
2280 if (!get_default_tuner_type(hdw)) {
2281 pvr2_trace(PVR2_TRACE_INIT,
2282 "pvr2_hdw_setup: Tuner type overridden to %d",
2283 hdw->tuner_type);
2284 }
2285
2286
2287 if (!pvr2_hdw_dev_ok(hdw)) return;
2288
2289 if (hdw->hdw_desc->signal_routing_scheme ==
2290 PVR2_ROUTING_SCHEME_GOTVIEW) {
2291 /* Ensure that GPIO 11 is set to output for GOTVIEW
2292 hardware. */
2293 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2294 }
2295
2296 pvr2_hdw_commit_setup(hdw);
2297
2298 hdw->vid_stream = pvr2_stream_create();
2299 if (!pvr2_hdw_dev_ok(hdw)) return;
2300 pvr2_trace(PVR2_TRACE_INIT,
2301 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2302 if (hdw->vid_stream) {
2303 idx = get_default_error_tolerance(hdw);
2304 if (idx) {
2305 pvr2_trace(PVR2_TRACE_INIT,
2306 "pvr2_hdw_setup: video stream %p"
2307 " setting tolerance %u",
2308 hdw->vid_stream,idx);
2309 }
2310 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2311 PVR2_VID_ENDPOINT,idx);
2312 }
2313
2314 if (!pvr2_hdw_dev_ok(hdw)) return;
2315
2316 hdw->flag_init_ok = !0;
2317
2318 pvr2_hdw_state_sched(hdw);
2319 }
2320
2321
2322 /* Set up the structure and attempt to put the device into a usable state.
2323 This can be a time-consuming operation, which is why it is not done
2324 internally as part of the create() step. */
2325 static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
2326 {
2327 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
2328 do {
2329 pvr2_hdw_setup_low(hdw);
2330 pvr2_trace(PVR2_TRACE_INIT,
2331 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
2332 hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
2333 if (pvr2_hdw_dev_ok(hdw)) {
2334 if (hdw->flag_init_ok) {
2335 pvr2_trace(
2336 PVR2_TRACE_INFO,
2337 "Device initialization"
2338 " completed successfully.");
2339 break;
2340 }
2341 if (hdw->fw1_state == FW1_STATE_RELOAD) {
2342 pvr2_trace(
2343 PVR2_TRACE_INFO,
2344 "Device microcontroller firmware"
2345 " (re)loaded; it should now reset"
2346 " and reconnect.");
2347 break;
2348 }
2349 pvr2_trace(
2350 PVR2_TRACE_ERROR_LEGS,
2351 "Device initialization was not successful.");
2352 if (hdw->fw1_state == FW1_STATE_MISSING) {
2353 pvr2_trace(
2354 PVR2_TRACE_ERROR_LEGS,
2355 "Giving up since device"
2356 " microcontroller firmware"
2357 " appears to be missing.");
2358 break;
2359 }
2360 }
2361 if (hdw->flag_modulefail) {
2362 pvr2_trace(
2363 PVR2_TRACE_ERROR_LEGS,
2364 "***WARNING*** pvrusb2 driver initialization"
2365 " failed due to the failure of one or more"
2366 " sub-device kernel modules.");
2367 pvr2_trace(
2368 PVR2_TRACE_ERROR_LEGS,
2369 "You need to resolve the failing condition"
2370 " before this driver can function. There"
2371 " should be some earlier messages giving more"
2372 " information about the problem.");
2373 break;
2374 }
2375 if (procreload) {
2376 pvr2_trace(
2377 PVR2_TRACE_ERROR_LEGS,
2378 "Attempting pvrusb2 recovery by reloading"
2379 " primary firmware.");
2380 pvr2_trace(
2381 PVR2_TRACE_ERROR_LEGS,
2382 "If this works, device should disconnect"
2383 " and reconnect in a sane state.");
2384 hdw->fw1_state = FW1_STATE_UNKNOWN;
2385 pvr2_upload_firmware1(hdw);
2386 } else {
2387 pvr2_trace(
2388 PVR2_TRACE_ERROR_LEGS,
2389 "***WARNING*** pvrusb2 device hardware"
2390 " appears to be jammed"
2391 " and I can't clear it.");
2392 pvr2_trace(
2393 PVR2_TRACE_ERROR_LEGS,
2394 "You might need to power cycle"
2395 " the pvrusb2 device"
2396 " in order to recover.");
2397 }
2398 } while (0);
2399 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
2400 }
2401
2402
2403 /* Perform second stage initialization. Set callback pointer first so that
2404 we can avoid a possible initialization race (if the kernel thread runs
2405 before the callback has been set). */
2406 int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2407 void (*callback_func)(void *),
2408 void *callback_data)
2409 {
2410 LOCK_TAKE(hdw->big_lock); do {
2411 if (hdw->flag_disconnected) {
2412 /* Handle a race here: If we're already
2413 disconnected by this point, then give up. If we
2414 get past this then we'll remain connected for
2415 the duration of initialization since the entire
2416 initialization sequence is now protected by the
2417 big_lock. */
2418 break;
2419 }
2420 hdw->state_data = callback_data;
2421 hdw->state_func = callback_func;
2422 pvr2_hdw_setup(hdw);
2423 } while (0); LOCK_GIVE(hdw->big_lock);
2424 return hdw->flag_init_ok;
2425 }
2426
2427
2428 /* Create, set up, and return a structure for interacting with the
2429 underlying hardware. */
2430 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2431 const struct usb_device_id *devid)
2432 {
2433 unsigned int idx,cnt1,cnt2,m;
2434 struct pvr2_hdw *hdw = NULL;
2435 int valid_std_mask;
2436 struct pvr2_ctrl *cptr;
2437 struct usb_device *usb_dev;
2438 const struct pvr2_device_desc *hdw_desc;
2439 __u8 ifnum;
2440 struct v4l2_queryctrl qctrl;
2441 struct pvr2_ctl_info *ciptr;
2442
2443 usb_dev = interface_to_usbdev(intf);
2444
2445 hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
2446
2447 if (hdw_desc == NULL) {
2448 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2449 " No device description pointer,"
2450 " unable to continue.");
2451 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2452 " please contact Mike Isely <isely@pobox.com>"
2453 " to get it included in the driver\n");
2454 goto fail;
2455 }
2456
2457 hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
2458 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
2459 hdw,hdw_desc->description);
2460 pvr2_trace(PVR2_TRACE_INFO, "Hardware description: %s",
2461 hdw_desc->description);
2462 if (hdw_desc->flag_is_experimental) {
2463 pvr2_trace(PVR2_TRACE_INFO, "**********");
2464 pvr2_trace(PVR2_TRACE_INFO,
2465 "WARNING: Support for this device (%s) is"
2466 " experimental.", hdw_desc->description);
2467 pvr2_trace(PVR2_TRACE_INFO,
2468 "Important functionality might not be"
2469 " entirely working.");
2470 pvr2_trace(PVR2_TRACE_INFO,
2471 "Please consider contacting the driver author to"
2472 " help with further stabilization of the driver.");
2473 pvr2_trace(PVR2_TRACE_INFO, "**********");
2474 }
2475 if (!hdw) goto fail;
2476
2477 init_timer(&hdw->quiescent_timer);
2478 hdw->quiescent_timer.data = (unsigned long)hdw;
2479 hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
2480
2481 init_timer(&hdw->decoder_stabilization_timer);
2482 hdw->decoder_stabilization_timer.data = (unsigned long)hdw;
2483 hdw->decoder_stabilization_timer.function =
2484 pvr2_hdw_decoder_stabilization_timeout;
2485
2486 init_timer(&hdw->encoder_wait_timer);
2487 hdw->encoder_wait_timer.data = (unsigned long)hdw;
2488 hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
2489
2490 init_timer(&hdw->encoder_run_timer);
2491 hdw->encoder_run_timer.data = (unsigned long)hdw;
2492 hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
2493
2494 hdw->master_state = PVR2_STATE_DEAD;
2495
2496 init_waitqueue_head(&hdw->state_wait_data);
2497
2498 hdw->tuner_signal_stale = !0;
2499 cx2341x_fill_defaults(&hdw->enc_ctl_state);
2500
2501 /* Calculate which inputs are OK */
2502 m = 0;
2503 if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
2504 if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2505 m |= 1 << PVR2_CVAL_INPUT_DTV;
2506 }
2507 if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2508 if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2509 if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2510 hdw->input_avail_mask = m;
2511 hdw->input_allowed_mask = hdw->input_avail_mask;
2512
2513 /* If not a hybrid device, pathway_state never changes. So
2514 initialize it here to what it should forever be. */
2515 if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2516 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2517 } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2518 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2519 }
2520
2521 hdw->control_cnt = CTRLDEF_COUNT;
2522 hdw->control_cnt += MPEGDEF_COUNT;
2523 hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
2524 GFP_KERNEL);
2525 if (!hdw->controls) goto fail;
2526 hdw->hdw_desc = hdw_desc;
2527 hdw->ir_scheme_active = hdw->hdw_desc->ir_scheme;
2528 for (idx = 0; idx < hdw->control_cnt; idx++) {
2529 cptr = hdw->controls + idx;
2530 cptr->hdw = hdw;
2531 }
2532 for (idx = 0; idx < 32; idx++) {
2533 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2534 }
2535 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2536 cptr = hdw->controls + idx;
2537 cptr->info = control_defs+idx;
2538 }
2539
2540 /* Ensure that default input choice is a valid one. */
2541 m = hdw->input_avail_mask;
2542 if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2543 if (!((1 << idx) & m)) continue;
2544 hdw->input_val = idx;
2545 break;
2546 }
2547
2548 /* Define and configure additional controls from cx2341x module. */
2549 hdw->mpeg_ctrl_info = kzalloc(
2550 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
2551 if (!hdw->mpeg_ctrl_info) goto fail;
2552 for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2553 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2554 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2555 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2556 ciptr->name = mpeg_ids[idx].strid;
2557 ciptr->v4l_id = mpeg_ids[idx].id;
2558 ciptr->skip_init = !0;
2559 ciptr->get_value = ctrl_cx2341x_get;
2560 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2561 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2562 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2563 qctrl.id = ciptr->v4l_id;
2564 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2565 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2566 ciptr->set_value = ctrl_cx2341x_set;
2567 }
2568 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2569 PVR2_CTLD_INFO_DESC_SIZE);
2570 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2571 ciptr->default_value = qctrl.default_value;
2572 switch (qctrl.type) {
2573 default:
2574 case V4L2_CTRL_TYPE_INTEGER:
2575 ciptr->type = pvr2_ctl_int;
2576 ciptr->def.type_int.min_value = qctrl.minimum;
2577 ciptr->def.type_int.max_value = qctrl.maximum;
2578 break;
2579 case V4L2_CTRL_TYPE_BOOLEAN:
2580 ciptr->type = pvr2_ctl_bool;
2581 break;
2582 case V4L2_CTRL_TYPE_MENU:
2583 ciptr->type = pvr2_ctl_enum;
2584 ciptr->def.type_enum.value_names =
2585 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2586 ciptr->v4l_id);
2587 for (cnt1 = 0;
2588 ciptr->def.type_enum.value_names[cnt1] != NULL;
2589 cnt1++) { }
2590 ciptr->def.type_enum.count = cnt1;
2591 break;
2592 }
2593 cptr->info = ciptr;
2594 }
2595
2596 // Initialize video standard enum dynamic control
2597 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2598 if (cptr) {
2599 memcpy(&hdw->std_info_enum,cptr->info,
2600 sizeof(hdw->std_info_enum));
2601 cptr->info = &hdw->std_info_enum;
2602
2603 }
2604 // Initialize control data regarding video standard masks
2605 valid_std_mask = pvr2_std_get_usable();
2606 for (idx = 0; idx < 32; idx++) {
2607 if (!(valid_std_mask & (1 << idx))) continue;
2608 cnt1 = pvr2_std_id_to_str(
2609 hdw->std_mask_names[idx],
2610 sizeof(hdw->std_mask_names[idx])-1,
2611 1 << idx);
2612 hdw->std_mask_names[idx][cnt1] = 0;
2613 }
2614 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2615 if (cptr) {
2616 memcpy(&hdw->std_info_avail,cptr->info,
2617 sizeof(hdw->std_info_avail));
2618 cptr->info = &hdw->std_info_avail;
2619 hdw->std_info_avail.def.type_bitmask.bit_names =
2620 hdw->std_mask_ptrs;
2621 hdw->std_info_avail.def.type_bitmask.valid_bits =
2622 valid_std_mask;
2623 }
2624 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2625 if (cptr) {
2626 memcpy(&hdw->std_info_cur,cptr->info,
2627 sizeof(hdw->std_info_cur));
2628 cptr->info = &hdw->std_info_cur;
2629 hdw->std_info_cur.def.type_bitmask.bit_names =
2630 hdw->std_mask_ptrs;
2631 hdw->std_info_avail.def.type_bitmask.valid_bits =
2632 valid_std_mask;
2633 }
2634
2635 hdw->cropcap_stale = !0;
2636 hdw->eeprom_addr = -1;
2637 hdw->unit_number = -1;
2638 hdw->v4l_minor_number_video = -1;
2639 hdw->v4l_minor_number_vbi = -1;
2640 hdw->v4l_minor_number_radio = -1;
2641 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2642 if (!hdw->ctl_write_buffer) goto fail;
2643 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2644 if (!hdw->ctl_read_buffer) goto fail;
2645 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2646 if (!hdw->ctl_write_urb) goto fail;
2647 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2648 if (!hdw->ctl_read_urb) goto fail;
2649
2650 if (v4l2_device_register(&intf->dev, &hdw->v4l2_dev) != 0) {
2651 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2652 "Error registering with v4l core, giving up");
2653 goto fail;
2654 }
2655 mutex_lock(&pvr2_unit_mtx); do {
2656 for (idx = 0; idx < PVR_NUM; idx++) {
2657 if (unit_pointers[idx]) continue;
2658 hdw->unit_number = idx;
2659 unit_pointers[idx] = hdw;
2660 break;
2661 }
2662 } while (0); mutex_unlock(&pvr2_unit_mtx);
2663
2664 cnt1 = 0;
2665 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2666 cnt1 += cnt2;
2667 if (hdw->unit_number >= 0) {
2668 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2669 ('a' + hdw->unit_number));
2670 cnt1 += cnt2;
2671 }
2672 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2673 hdw->name[cnt1] = 0;
2674
2675 hdw->workqueue = create_singlethread_workqueue(hdw->name);
2676 INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2677
2678 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2679 hdw->unit_number,hdw->name);
2680
2681 hdw->tuner_type = -1;
2682 hdw->flag_ok = !0;
2683
2684 hdw->usb_intf = intf;
2685 hdw->usb_dev = usb_dev;
2686
2687 usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
2688
2689 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2690 usb_set_interface(hdw->usb_dev,ifnum,0);
2691
2692 mutex_init(&hdw->ctl_lock_mutex);
2693 mutex_init(&hdw->big_lock_mutex);
2694
2695 return hdw;
2696 fail:
2697 if (hdw) {
2698 del_timer_sync(&hdw->quiescent_timer);
2699 del_timer_sync(&hdw->decoder_stabilization_timer);
2700 del_timer_sync(&hdw->encoder_run_timer);
2701 del_timer_sync(&hdw->encoder_wait_timer);
2702 if (hdw->workqueue) {
2703 flush_workqueue(hdw->workqueue);
2704 destroy_workqueue(hdw->workqueue);
2705 hdw->workqueue = NULL;
2706 }
2707 usb_free_urb(hdw->ctl_read_urb);
2708 usb_free_urb(hdw->ctl_write_urb);
2709 kfree(hdw->ctl_read_buffer);
2710 kfree(hdw->ctl_write_buffer);
2711 kfree(hdw->controls);
2712 kfree(hdw->mpeg_ctrl_info);
2713 kfree(hdw->std_defs);
2714 kfree(hdw->std_enum_names);
2715 kfree(hdw);
2716 }
2717 return NULL;
2718 }
2719
2720
2721 /* Remove _all_ associations between this driver and the underlying USB
2722 layer. */
2723 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2724 {
2725 if (hdw->flag_disconnected) return;
2726 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2727 if (hdw->ctl_read_urb) {
2728 usb_kill_urb(hdw->ctl_read_urb);
2729 usb_free_urb(hdw->ctl_read_urb);
2730 hdw->ctl_read_urb = NULL;
2731 }
2732 if (hdw->ctl_write_urb) {
2733 usb_kill_urb(hdw->ctl_write_urb);
2734 usb_free_urb(hdw->ctl_write_urb);
2735 hdw->ctl_write_urb = NULL;
2736 }
2737 if (hdw->ctl_read_buffer) {
2738 kfree(hdw->ctl_read_buffer);
2739 hdw->ctl_read_buffer = NULL;
2740 }
2741 if (hdw->ctl_write_buffer) {
2742 kfree(hdw->ctl_write_buffer);
2743 hdw->ctl_write_buffer = NULL;
2744 }
2745 hdw->flag_disconnected = !0;
2746 /* If we don't do this, then there will be a dangling struct device
2747 reference to our disappearing device persisting inside the V4L
2748 core... */
2749 v4l2_device_disconnect(&hdw->v4l2_dev);
2750 hdw->usb_dev = NULL;
2751 hdw->usb_intf = NULL;
2752 pvr2_hdw_render_useless(hdw);
2753 }
2754
2755
2756 /* Destroy hardware interaction structure */
2757 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2758 {
2759 if (!hdw) return;
2760 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2761 if (hdw->workqueue) {
2762 flush_workqueue(hdw->workqueue);
2763 destroy_workqueue(hdw->workqueue);
2764 hdw->workqueue = NULL;
2765 }
2766 del_timer_sync(&hdw->quiescent_timer);
2767 del_timer_sync(&hdw->decoder_stabilization_timer);
2768 del_timer_sync(&hdw->encoder_run_timer);
2769 del_timer_sync(&hdw->encoder_wait_timer);
2770 if (hdw->fw_buffer) {
2771 kfree(hdw->fw_buffer);
2772 hdw->fw_buffer = NULL;
2773 }
2774 if (hdw->vid_stream) {
2775 pvr2_stream_destroy(hdw->vid_stream);
2776 hdw->vid_stream = NULL;
2777 }
2778 pvr2_i2c_core_done(hdw);
2779 v4l2_device_unregister(&hdw->v4l2_dev);
2780 pvr2_hdw_remove_usb_stuff(hdw);
2781 mutex_lock(&pvr2_unit_mtx); do {
2782 if ((hdw->unit_number >= 0) &&
2783 (hdw->unit_number < PVR_NUM) &&
2784 (unit_pointers[hdw->unit_number] == hdw)) {
2785 unit_pointers[hdw->unit_number] = NULL;
2786 }
2787 } while (0); mutex_unlock(&pvr2_unit_mtx);
2788 kfree(hdw->controls);
2789 kfree(hdw->mpeg_ctrl_info);
2790 kfree(hdw->std_defs);
2791 kfree(hdw->std_enum_names);
2792 kfree(hdw);
2793 }
2794
2795
2796 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2797 {
2798 return (hdw && hdw->flag_ok);
2799 }
2800
2801
2802 /* Called when hardware has been unplugged */
2803 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2804 {
2805 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2806 LOCK_TAKE(hdw->big_lock);
2807 LOCK_TAKE(hdw->ctl_lock);
2808 pvr2_hdw_remove_usb_stuff(hdw);
2809 LOCK_GIVE(hdw->ctl_lock);
2810 LOCK_GIVE(hdw->big_lock);
2811 }
2812
2813
2814 // Attempt to autoselect an appropriate value for std_enum_cur given
2815 // whatever is currently in std_mask_cur
2816 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
2817 {
2818 unsigned int idx;
2819 for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2820 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2821 hdw->std_enum_cur = idx;
2822 return;
2823 }
2824 }
2825 hdw->std_enum_cur = 0;
2826 }
2827
2828
2829 // Calculate correct set of enumerated standards based on currently known
2830 // set of available standards bits.
2831 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
2832 {
2833 struct v4l2_standard *newstd;
2834 unsigned int std_cnt;
2835 unsigned int idx;
2836
2837 newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2838
2839 if (hdw->std_defs) {
2840 kfree(hdw->std_defs);
2841 hdw->std_defs = NULL;
2842 }
2843 hdw->std_enum_cnt = 0;
2844 if (hdw->std_enum_names) {
2845 kfree(hdw->std_enum_names);
2846 hdw->std_enum_names = NULL;
2847 }
2848
2849 if (!std_cnt) {
2850 pvr2_trace(
2851 PVR2_TRACE_ERROR_LEGS,
2852 "WARNING: Failed to identify any viable standards");
2853 }
2854
2855 /* Set up the dynamic control for this standard */
2856 hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2857 if (hdw->std_enum_names) {
2858 hdw->std_enum_names[0] = "none";
2859 for (idx = 0; idx < std_cnt; idx++)
2860 hdw->std_enum_names[idx+1] = newstd[idx].name;
2861 hdw->std_info_enum.def.type_enum.value_names =
2862 hdw->std_enum_names;
2863 hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2864 } else {
2865 pvr2_trace(
2866 PVR2_TRACE_ERROR_LEGS,
2867 "WARNING: Failed to alloc memory for names");
2868 hdw->std_info_enum.def.type_enum.value_names = NULL;
2869 hdw->std_info_enum.def.type_enum.count = 0;
2870 }
2871 hdw->std_defs = newstd;
2872 hdw->std_enum_cnt = std_cnt+1;
2873 hdw->std_enum_cur = 0;
2874 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2875 }
2876
2877
2878 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2879 struct v4l2_standard *std,
2880 unsigned int idx)
2881 {
2882 int ret = -EINVAL;
2883 if (!idx) return ret;
2884 LOCK_TAKE(hdw->big_lock); do {
2885 if (idx >= hdw->std_enum_cnt) break;
2886 idx--;
2887 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2888 ret = 0;
2889 } while (0); LOCK_GIVE(hdw->big_lock);
2890 return ret;
2891 }
2892
2893
2894 /* Get the number of defined controls */
2895 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2896 {
2897 return hdw->control_cnt;
2898 }
2899
2900
2901 /* Retrieve a control handle given its index (0..count-1) */
2902 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2903 unsigned int idx)
2904 {
2905 if (idx >= hdw->control_cnt) return NULL;
2906 return hdw->controls + idx;
2907 }
2908
2909
2910 /* Retrieve a control handle given its index (0..count-1) */
2911 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2912 unsigned int ctl_id)
2913 {
2914 struct pvr2_ctrl *cptr;
2915 unsigned int idx;
2916 int i;
2917
2918 /* This could be made a lot more efficient, but for now... */
2919 for (idx = 0; idx < hdw->control_cnt; idx++) {
2920 cptr = hdw->controls + idx;
2921 i = cptr->info->internal_id;
2922 if (i && (i == ctl_id)) return cptr;
2923 }
2924 return NULL;
2925 }
2926
2927
2928 /* Given a V4L ID, retrieve the control structure associated with it. */
2929 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2930 {
2931 struct pvr2_ctrl *cptr;
2932 unsigned int idx;
2933 int i;
2934
2935 /* This could be made a lot more efficient, but for now... */
2936 for (idx = 0; idx < hdw->control_cnt; idx++) {
2937 cptr = hdw->controls + idx;
2938 i = cptr->info->v4l_id;
2939 if (i && (i == ctl_id)) return cptr;
2940 }
2941 return NULL;
2942 }
2943
2944
2945 /* Given a V4L ID for its immediate predecessor, retrieve the control
2946 structure associated with it. */
2947 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2948 unsigned int ctl_id)
2949 {
2950 struct pvr2_ctrl *cptr,*cp2;
2951 unsigned int idx;
2952 int i;
2953
2954 /* This could be made a lot more efficient, but for now... */
2955 cp2 = NULL;
2956 for (idx = 0; idx < hdw->control_cnt; idx++) {
2957 cptr = hdw->controls + idx;
2958 i = cptr->info->v4l_id;
2959 if (!i) continue;
2960 if (i <= ctl_id) continue;
2961 if (cp2 && (cp2->info->v4l_id < i)) continue;
2962 cp2 = cptr;
2963 }
2964 return cp2;
2965 return NULL;
2966 }
2967
2968
2969 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2970 {
2971 switch (tp) {
2972 case pvr2_ctl_int: return "integer";
2973 case pvr2_ctl_enum: return "enum";
2974 case pvr2_ctl_bool: return "boolean";
2975 case pvr2_ctl_bitmask: return "bitmask";
2976 }
2977 return "";
2978 }
2979
2980
2981 static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2982 const char *name, int val)
2983 {
2984 struct v4l2_control ctrl;
2985 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2986 memset(&ctrl, 0, sizeof(ctrl));
2987 ctrl.id = id;
2988 ctrl.value = val;
2989 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, s_ctrl, &ctrl);
2990 }
2991
2992 #define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
2993 if ((hdw)->lab##_dirty || (hdw)->force_dirty) { \
2994 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2995 }
2996
2997 /* Execute whatever commands are required to update the state of all the
2998 sub-devices so that they match our current control values. */
2999 static void pvr2_subdev_update(struct pvr2_hdw *hdw)
3000 {
3001 struct v4l2_subdev *sd;
3002 unsigned int id;
3003 pvr2_subdev_update_func fp;
3004
3005 pvr2_trace(PVR2_TRACE_CHIPS, "subdev update...");
3006
3007 if (hdw->tuner_updated || hdw->force_dirty) {
3008 struct tuner_setup setup;
3009 pvr2_trace(PVR2_TRACE_CHIPS, "subdev tuner set_type(%d)",
3010 hdw->tuner_type);
3011 if (((int)(hdw->tuner_type)) >= 0) {
3012 memset(&setup, 0, sizeof(setup));
3013 setup.addr = ADDR_UNSET;
3014 setup.type = hdw->tuner_type;
3015 setup.mode_mask = T_RADIO | T_ANALOG_TV;
3016 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3017 tuner, s_type_addr, &setup);
3018 }
3019 }
3020
3021 if (hdw->input_dirty || hdw->std_dirty || hdw->force_dirty) {
3022 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_standard");
3023 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3024 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3025 tuner, s_radio);
3026 } else {
3027 v4l2_std_id vs;
3028 vs = hdw->std_mask_cur;
3029 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3030 core, s_std, vs);
3031 pvr2_hdw_cx25840_vbi_hack(hdw);
3032 }
3033 hdw->tuner_signal_stale = !0;
3034 hdw->cropcap_stale = !0;
3035 }
3036
3037 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
3038 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
3039 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
3040 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
3041 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
3042 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
3043 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
3044 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
3045 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
3046
3047 if (hdw->input_dirty || hdw->audiomode_dirty || hdw->force_dirty) {
3048 struct v4l2_tuner vt;
3049 memset(&vt, 0, sizeof(vt));
3050 vt.type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ?
3051 V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
3052 vt.audmode = hdw->audiomode_val;
3053 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
3054 }
3055
3056 if (hdw->freqDirty || hdw->force_dirty) {
3057 unsigned long fv;
3058 struct v4l2_frequency freq;
3059 fv = pvr2_hdw_get_cur_freq(hdw);
3060 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
3061 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
3062 memset(&freq, 0, sizeof(freq));
3063 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
3064 /* ((fv * 1000) / 62500) */
3065 freq.frequency = (fv * 2) / 125;
3066 } else {
3067 freq.frequency = fv / 62500;
3068 }
3069 /* tuner-core currently doesn't seem to care about this, but
3070 let's set it anyway for completeness. */
3071 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3072 freq.type = V4L2_TUNER_RADIO;
3073 } else {
3074 freq.type = V4L2_TUNER_ANALOG_TV;
3075 }
3076 freq.tuner = 0;
3077 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
3078 s_frequency, &freq);
3079 }
3080
3081 if (hdw->res_hor_dirty || hdw->res_ver_dirty || hdw->force_dirty) {
3082 struct v4l2_mbus_framefmt fmt;
3083 memset(&fmt, 0, sizeof(fmt));
3084 fmt.width = hdw->res_hor_val;
3085 fmt.height = hdw->res_ver_val;
3086 fmt.code = V4L2_MBUS_FMT_FIXED;
3087 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_size(%dx%d)",
3088 fmt.width, fmt.height);
3089 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_mbus_fmt, &fmt);
3090 }
3091
3092 if (hdw->srate_dirty || hdw->force_dirty) {
3093 u32 val;
3094 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
3095 hdw->srate_val);
3096 switch (hdw->srate_val) {
3097 default:
3098 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
3099 val = 48000;
3100 break;
3101 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
3102 val = 44100;
3103 break;
3104 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
3105 val = 32000;
3106 break;
3107 }
3108 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3109 audio, s_clock_freq, val);
3110 }
3111
3112 /* Unable to set crop parameters; there is apparently no equivalent
3113 for VIDIOC_S_CROP */
3114
3115 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
3116 id = sd->grp_id;
3117 if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
3118 fp = pvr2_module_update_functions[id];
3119 if (!fp) continue;
3120 (*fp)(hdw, sd);
3121 }
3122
3123 if (hdw->tuner_signal_stale || hdw->cropcap_stale) {
3124 pvr2_hdw_status_poll(hdw);
3125 }
3126 }
3127
3128
3129 /* Figure out if we need to commit control changes. If so, mark internal
3130 state flags to indicate this fact and return true. Otherwise do nothing
3131 else and return false. */
3132 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
3133 {
3134 unsigned int idx;
3135 struct pvr2_ctrl *cptr;
3136 int value;
3137 int commit_flag = hdw->force_dirty;
3138 char buf[100];
3139 unsigned int bcnt,ccnt;
3140
3141 for (idx = 0; idx < hdw->control_cnt; idx++) {
3142 cptr = hdw->controls + idx;
3143 if (!cptr->info->is_dirty) continue;
3144 if (!cptr->info->is_dirty(cptr)) continue;
3145 commit_flag = !0;
3146
3147 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
3148 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
3149 cptr->info->name);
3150 value = 0;
3151 cptr->info->get_value(cptr,&value);
3152 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
3153 buf+bcnt,
3154 sizeof(buf)-bcnt,&ccnt);
3155 bcnt += ccnt;
3156 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
3157 get_ctrl_typename(cptr->info->type));
3158 pvr2_trace(PVR2_TRACE_CTL,
3159 "/*--TRACE_COMMIT--*/ %.*s",
3160 bcnt,buf);
3161 }
3162
3163 if (!commit_flag) {
3164 /* Nothing has changed */
3165 return 0;
3166 }
3167
3168 hdw->state_pipeline_config = 0;
3169 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3170 pvr2_hdw_state_sched(hdw);
3171
3172 return !0;
3173 }
3174
3175
3176 /* Perform all operations needed to commit all control changes. This must
3177 be performed in synchronization with the pipeline state and is thus
3178 expected to be called as part of the driver's worker thread. Return
3179 true if commit successful, otherwise return false to indicate that
3180 commit isn't possible at this time. */
3181 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3182 {
3183 unsigned int idx;
3184 struct pvr2_ctrl *cptr;
3185 int disruptive_change;
3186
3187 if (hdw->input_dirty && hdw->state_pathway_ok &&
3188 (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3189 PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3190 hdw->pathway_state)) {
3191 /* Change of mode being asked for... */
3192 hdw->state_pathway_ok = 0;
3193 trace_stbit("state_pathway_ok", hdw->state_pathway_ok);
3194 }
3195 if (!hdw->state_pathway_ok) {
3196 /* Can't commit anything until pathway is ok. */
3197 return 0;
3198 }
3199
3200 /* Handle some required side effects when the video standard is
3201 changed.... */
3202 if (hdw->std_dirty) {
3203 int nvres;
3204 int gop_size;
3205 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3206 nvres = 480;
3207 gop_size = 15;
3208 } else {
3209 nvres = 576;
3210 gop_size = 12;
3211 }
3212 /* Rewrite the vertical resolution to be appropriate to the
3213 video standard that has been selected. */
3214 if (nvres != hdw->res_ver_val) {
3215 hdw->res_ver_val = nvres;
3216 hdw->res_ver_dirty = !0;
3217 }
3218 /* Rewrite the GOP size to be appropriate to the video
3219 standard that has been selected. */
3220 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3221 struct v4l2_ext_controls cs;
3222 struct v4l2_ext_control c1;
3223 memset(&cs, 0, sizeof(cs));
3224 memset(&c1, 0, sizeof(c1));
3225 cs.controls = &c1;
3226 cs.count = 1;
3227 c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3228 c1.value = gop_size;
3229 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3230 VIDIOC_S_EXT_CTRLS);
3231 }
3232 }
3233
3234 /* The broadcast decoder can only scale down, so if
3235 * res_*_dirty && crop window < output format ==> enlarge crop.
3236 *
3237 * The mpeg encoder receives fields of res_hor_val dots and
3238 * res_ver_val halflines. Limits: hor<=720, ver<=576.
3239 */
3240 if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3241 hdw->cropw_val = hdw->res_hor_val;
3242 hdw->cropw_dirty = !0;
3243 } else if (hdw->cropw_dirty) {
3244 hdw->res_hor_dirty = !0; /* must rescale */
3245 hdw->res_hor_val = min(720, hdw->cropw_val);
3246 }
3247 if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3248 hdw->croph_val = hdw->res_ver_val;
3249 hdw->croph_dirty = !0;
3250 } else if (hdw->croph_dirty) {
3251 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3252 hdw->res_ver_dirty = !0;
3253 hdw->res_ver_val = min(nvres, hdw->croph_val);
3254 }
3255
3256 /* If any of the below has changed, then we can't do the update
3257 while the pipeline is running. Pipeline must be paused first
3258 and decoder -> encoder connection be made quiescent before we
3259 can proceed. */
3260 disruptive_change =
3261 (hdw->std_dirty ||
3262 hdw->enc_unsafe_stale ||
3263 hdw->srate_dirty ||
3264 hdw->res_ver_dirty ||
3265 hdw->res_hor_dirty ||
3266 hdw->cropw_dirty ||
3267 hdw->croph_dirty ||
3268 hdw->input_dirty ||
3269 (hdw->active_stream_type != hdw->desired_stream_type));
3270 if (disruptive_change && !hdw->state_pipeline_idle) {
3271 /* Pipeline is not idle; we can't proceed. Arrange to
3272 cause pipeline to stop so that we can try this again
3273 later.... */
3274 hdw->state_pipeline_pause = !0;
3275 return 0;
3276 }
3277
3278 if (hdw->srate_dirty) {
3279 /* Write new sample rate into control structure since
3280 * the master copy is stale. We must track srate
3281 * separate from the mpeg control structure because
3282 * other logic also uses this value. */
3283 struct v4l2_ext_controls cs;
3284 struct v4l2_ext_control c1;
3285 memset(&cs,0,sizeof(cs));
3286 memset(&c1,0,sizeof(c1));
3287 cs.controls = &c1;
3288 cs.count = 1;
3289 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3290 c1.value = hdw->srate_val;
3291 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
3292 }
3293
3294 if (hdw->active_stream_type != hdw->desired_stream_type) {
3295 /* Handle any side effects of stream config here */
3296 hdw->active_stream_type = hdw->desired_stream_type;
3297 }
3298
3299 if (hdw->hdw_desc->signal_routing_scheme ==
3300 PVR2_ROUTING_SCHEME_GOTVIEW) {
3301 u32 b;
3302 /* Handle GOTVIEW audio switching */
3303 pvr2_hdw_gpio_get_out(hdw,&b);
3304 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3305 /* Set GPIO 11 */
3306 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3307 } else {
3308 /* Clear GPIO 11 */
3309 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3310 }
3311 }
3312
3313 /* Check and update state for all sub-devices. */
3314 pvr2_subdev_update(hdw);
3315
3316 hdw->tuner_updated = 0;
3317 hdw->force_dirty = 0;
3318 for (idx = 0; idx < hdw->control_cnt; idx++) {
3319 cptr = hdw->controls + idx;
3320 if (!cptr->info->clear_dirty) continue;
3321 cptr->info->clear_dirty(cptr);
3322 }
3323
3324 if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3325 hdw->state_encoder_run) {
3326 /* If encoder isn't running or it can't be touched, then
3327 this will get worked out later when we start the
3328 encoder. */
3329 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3330 }
3331
3332 hdw->state_pipeline_config = !0;
3333 /* Hardware state may have changed in a way to cause the cropping
3334 capabilities to have changed. So mark it stale, which will
3335 cause a later re-fetch. */
3336 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3337 return !0;
3338 }
3339
3340
3341 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3342 {
3343 int fl;
3344 LOCK_TAKE(hdw->big_lock);
3345 fl = pvr2_hdw_commit_setup(hdw);
3346 LOCK_GIVE(hdw->big_lock);
3347 if (!fl) return 0;
3348 return pvr2_hdw_wait(hdw,0);
3349 }
3350
3351
3352 static void pvr2_hdw_worker_poll(struct work_struct *work)
3353 {
3354 int fl = 0;
3355 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
3356 LOCK_TAKE(hdw->big_lock); do {
3357 fl = pvr2_hdw_state_eval(hdw);
3358 } while (0); LOCK_GIVE(hdw->big_lock);
3359 if (fl && hdw->state_func) {
3360 hdw->state_func(hdw->state_data);
3361 }
3362 }
3363
3364
3365 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
3366 {
3367 return wait_event_interruptible(
3368 hdw->state_wait_data,
3369 (hdw->state_stale == 0) &&
3370 (!state || (hdw->master_state != state)));
3371 }
3372
3373
3374 /* Return name for this driver instance */
3375 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3376 {
3377 return hdw->name;
3378 }
3379
3380
3381 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3382 {
3383 return hdw->hdw_desc->description;
3384 }
3385
3386
3387 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3388 {
3389 return hdw->hdw_desc->shortname;
3390 }
3391
3392
3393 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3394 {
3395 int result;
3396 LOCK_TAKE(hdw->ctl_lock); do {
3397 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
3398 result = pvr2_send_request(hdw,
3399 hdw->cmd_buffer,1,
3400 hdw->cmd_buffer,1);
3401 if (result < 0) break;
3402 result = (hdw->cmd_buffer[0] != 0);
3403 } while(0); LOCK_GIVE(hdw->ctl_lock);
3404 return result;
3405 }
3406
3407
3408 /* Execute poll of tuner status */
3409 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
3410 {
3411 LOCK_TAKE(hdw->big_lock); do {
3412 pvr2_hdw_status_poll(hdw);
3413 } while (0); LOCK_GIVE(hdw->big_lock);
3414 }
3415
3416
3417 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3418 {
3419 if (!hdw->cropcap_stale) {
3420 return 0;
3421 }
3422 pvr2_hdw_status_poll(hdw);
3423 if (hdw->cropcap_stale) {
3424 return -EIO;
3425 }
3426 return 0;
3427 }
3428
3429
3430 /* Return information about cropping capabilities */
3431 int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3432 {
3433 int stat = 0;
3434 LOCK_TAKE(hdw->big_lock);
3435 stat = pvr2_hdw_check_cropcap(hdw);
3436 if (!stat) {
3437 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3438 }
3439 LOCK_GIVE(hdw->big_lock);
3440 return stat;
3441 }
3442
3443
3444 /* Return information about the tuner */
3445 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3446 {
3447 LOCK_TAKE(hdw->big_lock); do {
3448 if (hdw->tuner_signal_stale) {
3449 pvr2_hdw_status_poll(hdw);
3450 }
3451 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3452 } while (0); LOCK_GIVE(hdw->big_lock);
3453 return 0;
3454 }
3455
3456
3457 /* Get handle to video output stream */
3458 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3459 {
3460 return hp->vid_stream;
3461 }
3462
3463
3464 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3465 {
3466 int nr = pvr2_hdw_get_unit_number(hdw);
3467 LOCK_TAKE(hdw->big_lock); do {
3468 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
3469 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
3470 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
3471 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
3472 pvr2_hdw_state_log_state(hdw);
3473 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
3474 } while (0); LOCK_GIVE(hdw->big_lock);
3475 }
3476
3477
3478 /* Grab EEPROM contents, needed for direct method. */
3479 #define EEPROM_SIZE 8192
3480 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3481 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3482 {
3483 struct i2c_msg msg[2];
3484 u8 *eeprom;
3485 u8 iadd[2];
3486 u8 addr;
3487 u16 eepromSize;
3488 unsigned int offs;
3489 int ret;
3490 int mode16 = 0;
3491 unsigned pcnt,tcnt;
3492 eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3493 if (!eeprom) {
3494 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3495 "Failed to allocate memory"
3496 " required to read eeprom");
3497 return NULL;
3498 }
3499
3500 trace_eeprom("Value for eeprom addr from controller was 0x%x",
3501 hdw->eeprom_addr);
3502 addr = hdw->eeprom_addr;
3503 /* Seems that if the high bit is set, then the *real* eeprom
3504 address is shifted right now bit position (noticed this in
3505 newer PVR USB2 hardware) */
3506 if (addr & 0x80) addr >>= 1;
3507
3508 /* FX2 documentation states that a 16bit-addressed eeprom is
3509 expected if the I2C address is an odd number (yeah, this is
3510 strange but it's what they do) */
3511 mode16 = (addr & 1);
3512 eepromSize = (mode16 ? EEPROM_SIZE : 256);
3513 trace_eeprom("Examining %d byte eeprom at location 0x%x"
3514 " using %d bit addressing",eepromSize,addr,
3515 mode16 ? 16 : 8);
3516
3517 msg[0].addr = addr;
3518 msg[0].flags = 0;
3519 msg[0].len = mode16 ? 2 : 1;
3520 msg[0].buf = iadd;
3521 msg[1].addr = addr;
3522 msg[1].flags = I2C_M_RD;
3523
3524 /* We have to do the actual eeprom data fetch ourselves, because
3525 (1) we're only fetching part of the eeprom, and (2) if we were
3526 getting the whole thing our I2C driver can't grab it in one
3527 pass - which is what tveeprom is otherwise going to attempt */
3528 memset(eeprom,0,EEPROM_SIZE);
3529 for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3530 pcnt = 16;
3531 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3532 offs = tcnt + (eepromSize - EEPROM_SIZE);
3533 if (mode16) {
3534 iadd[0] = offs >> 8;
3535 iadd[1] = offs;
3536 } else {
3537 iadd[0] = offs;
3538 }
3539 msg[1].len = pcnt;
3540 msg[1].buf = eeprom+tcnt;
3541 if ((ret = i2c_transfer(&hdw->i2c_adap,
3542 msg,ARRAY_SIZE(msg))) != 2) {
3543 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3544 "eeprom fetch set offs err=%d",ret);
3545 kfree(eeprom);
3546 return NULL;
3547 }
3548 }
3549 return eeprom;
3550 }
3551
3552
3553 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3554 int mode,
3555 int enable_flag)
3556 {
3557 int ret;
3558 u16 address;
3559 unsigned int pipe;
3560 LOCK_TAKE(hdw->big_lock); do {
3561 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
3562
3563 if (!enable_flag) {
3564 pvr2_trace(PVR2_TRACE_FIRMWARE,
3565 "Cleaning up after CPU firmware fetch");
3566 kfree(hdw->fw_buffer);
3567 hdw->fw_buffer = NULL;
3568 hdw->fw_size = 0;
3569 if (hdw->fw_cpu_flag) {
3570 /* Now release the CPU. It will disconnect
3571 and reconnect later. */
3572 pvr2_hdw_cpureset_assert(hdw,0);
3573 }
3574 break;
3575 }
3576
3577 hdw->fw_cpu_flag = (mode != 2);
3578 if (hdw->fw_cpu_flag) {
3579 hdw->fw_size = (mode == 1) ? 0x4000 : 0x2000;
3580 pvr2_trace(PVR2_TRACE_FIRMWARE,
3581 "Preparing to suck out CPU firmware"
3582 " (size=%u)", hdw->fw_size);
3583 hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3584 if (!hdw->fw_buffer) {
3585 hdw->fw_size = 0;
3586 break;
3587 }
3588
3589 /* We have to hold the CPU during firmware upload. */
3590 pvr2_hdw_cpureset_assert(hdw,1);
3591
3592 /* download the firmware from address 0000-1fff in 2048
3593 (=0x800) bytes chunk. */
3594
3595 pvr2_trace(PVR2_TRACE_FIRMWARE,
3596 "Grabbing CPU firmware");
3597 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3598 for(address = 0; address < hdw->fw_size;
3599 address += 0x800) {
3600 ret = usb_control_msg(hdw->usb_dev,pipe,
3601 0xa0,0xc0,
3602 address,0,
3603 hdw->fw_buffer+address,
3604 0x800,HZ);
3605 if (ret < 0) break;
3606 }
3607
3608 pvr2_trace(PVR2_TRACE_FIRMWARE,
3609 "Done grabbing CPU firmware");
3610 } else {
3611 pvr2_trace(PVR2_TRACE_FIRMWARE,
3612 "Sucking down EEPROM contents");
3613 hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3614 if (!hdw->fw_buffer) {
3615 pvr2_trace(PVR2_TRACE_FIRMWARE,
3616 "EEPROM content suck failed.");
3617 break;
3618 }
3619 hdw->fw_size = EEPROM_SIZE;
3620 pvr2_trace(PVR2_TRACE_FIRMWARE,
3621 "Done sucking down EEPROM contents");
3622 }
3623
3624 } while (0); LOCK_GIVE(hdw->big_lock);
3625 }
3626
3627
3628 /* Return true if we're in a mode for retrieval CPU firmware */
3629 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3630 {
3631 return hdw->fw_buffer != NULL;
3632 }
3633
3634
3635 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3636 char *buf,unsigned int cnt)
3637 {
3638 int ret = -EINVAL;
3639 LOCK_TAKE(hdw->big_lock); do {
3640 if (!buf) break;
3641 if (!cnt) break;
3642
3643 if (!hdw->fw_buffer) {
3644 ret = -EIO;
3645 break;
3646 }
3647
3648 if (offs >= hdw->fw_size) {
3649 pvr2_trace(PVR2_TRACE_FIRMWARE,
3650 "Read firmware data offs=%d EOF",
3651 offs);
3652 ret = 0;
3653 break;
3654 }
3655
3656 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3657
3658 memcpy(buf,hdw->fw_buffer+offs,cnt);
3659
3660 pvr2_trace(PVR2_TRACE_FIRMWARE,
3661 "Read firmware data offs=%d cnt=%d",
3662 offs,cnt);
3663 ret = cnt;
3664 } while (0); LOCK_GIVE(hdw->big_lock);
3665
3666 return ret;
3667 }
3668
3669
3670 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
3671 enum pvr2_v4l_type index)
3672 {
3673 switch (index) {
3674 case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3675 case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3676 case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
3677 default: return -1;
3678 }
3679 }
3680
3681
3682 /* Store a v4l minor device number */
3683 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
3684 enum pvr2_v4l_type index,int v)
3685 {
3686 switch (index) {
3687 case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
3688 case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
3689 case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
3690 default: break;
3691 }
3692 }
3693
3694
3695 static void pvr2_ctl_write_complete(struct urb *urb)
3696 {
3697 struct pvr2_hdw *hdw = urb->context;
3698 hdw->ctl_write_pend_flag = 0;
3699 if (hdw->ctl_read_pend_flag) return;
3700 complete(&hdw->ctl_done);
3701 }
3702
3703
3704 static void pvr2_ctl_read_complete(struct urb *urb)
3705 {
3706 struct pvr2_hdw *hdw = urb->context;
3707 hdw->ctl_read_pend_flag = 0;
3708 if (hdw->ctl_write_pend_flag) return;
3709 complete(&hdw->ctl_done);
3710 }
3711
3712
3713 static void pvr2_ctl_timeout(unsigned long data)
3714 {
3715 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3716 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3717 hdw->ctl_timeout_flag = !0;
3718 if (hdw->ctl_write_pend_flag)
3719 usb_unlink_urb(hdw->ctl_write_urb);
3720 if (hdw->ctl_read_pend_flag)
3721 usb_unlink_urb(hdw->ctl_read_urb);
3722 }
3723 }
3724
3725
3726 /* Issue a command and get a response from the device. This extended
3727 version includes a probe flag (which if set means that device errors
3728 should not be logged or treated as fatal) and a timeout in jiffies.
3729 This can be used to non-lethally probe the health of endpoint 1. */
3730 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3731 unsigned int timeout,int probe_fl,
3732 void *write_data,unsigned int write_len,
3733 void *read_data,unsigned int read_len)
3734 {
3735 unsigned int idx;
3736 int status = 0;
3737 struct timer_list timer;
3738 if (!hdw->ctl_lock_held) {
3739 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3740 "Attempted to execute control transfer"
3741 " without lock!!");
3742 return -EDEADLK;
3743 }
3744 if (!hdw->flag_ok && !probe_fl) {
3745 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3746 "Attempted to execute control transfer"
3747 " when device not ok");
3748 return -EIO;
3749 }
3750 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3751 if (!probe_fl) {
3752 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3753 "Attempted to execute control transfer"
3754 " when USB is disconnected");
3755 }
3756 return -ENOTTY;
3757 }
3758
3759 /* Ensure that we have sane parameters */
3760 if (!write_data) write_len = 0;
3761 if (!read_data) read_len = 0;
3762 if (write_len > PVR2_CTL_BUFFSIZE) {
3763 pvr2_trace(
3764 PVR2_TRACE_ERROR_LEGS,
3765 "Attempted to execute %d byte"
3766 " control-write transfer (limit=%d)",
3767 write_len,PVR2_CTL_BUFFSIZE);
3768 return -EINVAL;
3769 }
3770 if (read_len > PVR2_CTL_BUFFSIZE) {
3771 pvr2_trace(
3772 PVR2_TRACE_ERROR_LEGS,
3773 "Attempted to execute %d byte"
3774 " control-read transfer (limit=%d)",
3775 write_len,PVR2_CTL_BUFFSIZE);
3776 return -EINVAL;
3777 }
3778 if ((!write_len) && (!read_len)) {
3779 pvr2_trace(
3780 PVR2_TRACE_ERROR_LEGS,
3781 "Attempted to execute null control transfer?");
3782 return -EINVAL;
3783 }
3784
3785
3786 hdw->cmd_debug_state = 1;
3787 if (write_len) {
3788 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3789 } else {
3790 hdw->cmd_debug_code = 0;
3791 }
3792 hdw->cmd_debug_write_len = write_len;
3793 hdw->cmd_debug_read_len = read_len;
3794
3795 /* Initialize common stuff */
3796 init_completion(&hdw->ctl_done);
3797 hdw->ctl_timeout_flag = 0;
3798 hdw->ctl_write_pend_flag = 0;
3799 hdw->ctl_read_pend_flag = 0;
3800 init_timer(&timer);
3801 timer.expires = jiffies + timeout;
3802 timer.data = (unsigned long)hdw;
3803 timer.function = pvr2_ctl_timeout;
3804
3805 if (write_len) {
3806 hdw->cmd_debug_state = 2;
3807 /* Transfer write data to internal buffer */
3808 for (idx = 0; idx < write_len; idx++) {
3809 hdw->ctl_write_buffer[idx] =
3810 ((unsigned char *)write_data)[idx];
3811 }
3812 /* Initiate a write request */
3813 usb_fill_bulk_urb(hdw->ctl_write_urb,
3814 hdw->usb_dev,
3815 usb_sndbulkpipe(hdw->usb_dev,
3816 PVR2_CTL_WRITE_ENDPOINT),
3817 hdw->ctl_write_buffer,
3818 write_len,
3819 pvr2_ctl_write_complete,
3820 hdw);
3821 hdw->ctl_write_urb->actual_length = 0;
3822 hdw->ctl_write_pend_flag = !0;
3823 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3824 if (status < 0) {
3825 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3826 "Failed to submit write-control"
3827 " URB status=%d",status);
3828 hdw->ctl_write_pend_flag = 0;
3829 goto done;
3830 }
3831 }
3832
3833 if (read_len) {
3834 hdw->cmd_debug_state = 3;
3835 memset(hdw->ctl_read_buffer,0x43,read_len);
3836 /* Initiate a read request */
3837 usb_fill_bulk_urb(hdw->ctl_read_urb,
3838 hdw->usb_dev,
3839 usb_rcvbulkpipe(hdw->usb_dev,
3840 PVR2_CTL_READ_ENDPOINT),
3841 hdw->ctl_read_buffer,
3842 read_len,
3843 pvr2_ctl_read_complete,
3844 hdw);
3845 hdw->ctl_read_urb->actual_length = 0;
3846 hdw->ctl_read_pend_flag = !0;
3847 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3848 if (status < 0) {
3849 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3850 "Failed to submit read-control"
3851 " URB status=%d",status);
3852 hdw->ctl_read_pend_flag = 0;
3853 goto done;
3854 }
3855 }
3856
3857 /* Start timer */
3858 add_timer(&timer);
3859
3860 /* Now wait for all I/O to complete */
3861 hdw->cmd_debug_state = 4;
3862 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3863 wait_for_completion(&hdw->ctl_done);
3864 }
3865 hdw->cmd_debug_state = 5;
3866
3867 /* Stop timer */
3868 del_timer_sync(&timer);
3869
3870 hdw->cmd_debug_state = 6;
3871 status = 0;
3872
3873 if (hdw->ctl_timeout_flag) {
3874 status = -ETIMEDOUT;
3875 if (!probe_fl) {
3876 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3877 "Timed out control-write");
3878 }
3879 goto done;
3880 }
3881
3882 if (write_len) {
3883 /* Validate results of write request */
3884 if ((hdw->ctl_write_urb->status != 0) &&
3885 (hdw->ctl_write_urb->status != -ENOENT) &&
3886 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3887 (hdw->ctl_write_urb->status != -ECONNRESET)) {
3888 /* USB subsystem is reporting some kind of failure
3889 on the write */
3890 status = hdw->ctl_write_urb->status;
3891 if (!probe_fl) {
3892 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3893 "control-write URB failure,"
3894 " status=%d",
3895 status);
3896 }
3897 goto done;
3898 }
3899 if (hdw->ctl_write_urb->actual_length < write_len) {
3900 /* Failed to write enough data */
3901 status = -EIO;
3902 if (!probe_fl) {
3903 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3904 "control-write URB short,"
3905 " expected=%d got=%d",
3906 write_len,
3907 hdw->ctl_write_urb->actual_length);
3908 }
3909 goto done;
3910 }
3911 }
3912 if (read_len) {
3913 /* Validate results of read request */
3914 if ((hdw->ctl_read_urb->status != 0) &&
3915 (hdw->ctl_read_urb->status != -ENOENT) &&
3916 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3917 (hdw->ctl_read_urb->status != -ECONNRESET)) {
3918 /* USB subsystem is reporting some kind of failure
3919 on the read */
3920 status = hdw->ctl_read_urb->status;
3921 if (!probe_fl) {
3922 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3923 "control-read URB failure,"
3924 " status=%d",
3925 status);
3926 }
3927 goto done;
3928 }
3929 if (hdw->ctl_read_urb->actual_length < read_len) {
3930 /* Failed to read enough data */
3931 status = -EIO;
3932 if (!probe_fl) {
3933 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3934 "control-read URB short,"
3935 " expected=%d got=%d",
3936 read_len,
3937 hdw->ctl_read_urb->actual_length);
3938 }
3939 goto done;
3940 }
3941 /* Transfer retrieved data out from internal buffer */
3942 for (idx = 0; idx < read_len; idx++) {
3943 ((unsigned char *)read_data)[idx] =
3944 hdw->ctl_read_buffer[idx];
3945 }
3946 }
3947
3948 done:
3949
3950 hdw->cmd_debug_state = 0;
3951 if ((status < 0) && (!probe_fl)) {
3952 pvr2_hdw_render_useless(hdw);
3953 }
3954 return status;
3955 }
3956
3957
3958 int pvr2_send_request(struct pvr2_hdw *hdw,
3959 void *write_data,unsigned int write_len,
3960 void *read_data,unsigned int read_len)
3961 {
3962 return pvr2_send_request_ex(hdw,HZ*4,0,
3963 write_data,write_len,
3964 read_data,read_len);
3965 }
3966
3967
3968 static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3969 {
3970 int ret;
3971 unsigned int cnt = 1;
3972 unsigned int args = 0;
3973 LOCK_TAKE(hdw->ctl_lock);
3974 hdw->cmd_buffer[0] = cmdcode & 0xffu;
3975 args = (cmdcode >> 8) & 0xffu;
3976 args = (args > 2) ? 2 : args;
3977 if (args) {
3978 cnt += args;
3979 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3980 if (args > 1) {
3981 hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3982 }
3983 }
3984 if (pvrusb2_debug & PVR2_TRACE_INIT) {
3985 unsigned int idx;
3986 unsigned int ccnt,bcnt;
3987 char tbuf[50];
3988 cmdcode &= 0xffu;
3989 bcnt = 0;
3990 ccnt = scnprintf(tbuf+bcnt,
3991 sizeof(tbuf)-bcnt,
3992 "Sending FX2 command 0x%x",cmdcode);
3993 bcnt += ccnt;
3994 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3995 if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3996 ccnt = scnprintf(tbuf+bcnt,
3997 sizeof(tbuf)-bcnt,
3998 " \"%s\"",
3999 pvr2_fx2cmd_desc[idx].desc);
4000 bcnt += ccnt;
4001 break;
4002 }
4003 }
4004 if (args) {
4005 ccnt = scnprintf(tbuf+bcnt,
4006 sizeof(tbuf)-bcnt,
4007 " (%u",hdw->cmd_buffer[1]);
4008 bcnt += ccnt;
4009 if (args > 1) {
4010 ccnt = scnprintf(tbuf+bcnt,
4011 sizeof(tbuf)-bcnt,
4012 ",%u",hdw->cmd_buffer[2]);
4013 bcnt += ccnt;
4014 }
4015 ccnt = scnprintf(tbuf+bcnt,
4016 sizeof(tbuf)-bcnt,
4017 ")");
4018 bcnt += ccnt;
4019 }
4020 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
4021 }
4022 ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
4023 LOCK_GIVE(hdw->ctl_lock);
4024 return ret;
4025 }
4026
4027
4028 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
4029 {
4030 int ret;
4031
4032 LOCK_TAKE(hdw->ctl_lock);
4033
4034 hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */
4035 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
4036 hdw->cmd_buffer[5] = 0;
4037 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
4038 hdw->cmd_buffer[7] = reg & 0xff;
4039
4040
4041 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
4042
4043 LOCK_GIVE(hdw->ctl_lock);
4044
4045 return ret;
4046 }
4047
4048
4049 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
4050 {
4051 int ret = 0;
4052
4053 LOCK_TAKE(hdw->ctl_lock);
4054
4055 hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */
4056 hdw->cmd_buffer[1] = 0;
4057 hdw->cmd_buffer[2] = 0;
4058 hdw->cmd_buffer[3] = 0;
4059 hdw->cmd_buffer[4] = 0;
4060 hdw->cmd_buffer[5] = 0;
4061 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
4062 hdw->cmd_buffer[7] = reg & 0xff;
4063
4064 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
4065 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
4066
4067 LOCK_GIVE(hdw->ctl_lock);
4068
4069 return ret;
4070 }
4071
4072
4073 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
4074 {
4075 if (!hdw->flag_ok) return;
4076 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4077 "Device being rendered inoperable");
4078 if (hdw->vid_stream) {
4079 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
4080 }
4081 hdw->flag_ok = 0;
4082 trace_stbit("flag_ok",hdw->flag_ok);
4083 pvr2_hdw_state_sched(hdw);
4084 }
4085
4086
4087 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
4088 {
4089 int ret;
4090 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
4091 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
4092 if (ret == 0) {
4093 ret = usb_reset_device(hdw->usb_dev);
4094 usb_unlock_device(hdw->usb_dev);
4095 } else {
4096 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4097 "Failed to lock USB device ret=%d",ret);
4098 }
4099 if (init_pause_msec) {
4100 pvr2_trace(PVR2_TRACE_INFO,
4101 "Waiting %u msec for hardware to settle",
4102 init_pause_msec);
4103 msleep(init_pause_msec);
4104 }
4105
4106 }
4107
4108
4109 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
4110 {
4111 char *da;
4112 unsigned int pipe;
4113 int ret;
4114
4115 if (!hdw->usb_dev) return;
4116
4117 da = kmalloc(16, GFP_KERNEL);
4118
4119 if (da == NULL) {
4120 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4121 "Unable to allocate memory to control CPU reset");
4122 return;
4123 }
4124
4125 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
4126
4127 da[0] = val ? 0x01 : 0x00;
4128
4129 /* Write the CPUCS register on the 8051. The lsb of the register
4130 is the reset bit; a 1 asserts reset while a 0 clears it. */
4131 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
4132 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
4133 if (ret < 0) {
4134 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4135 "cpureset_assert(%d) error=%d",val,ret);
4136 pvr2_hdw_render_useless(hdw);
4137 }
4138
4139 kfree(da);
4140 }
4141
4142
4143 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
4144 {
4145 return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
4146 }
4147
4148
4149 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
4150 {
4151 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
4152 }
4153
4154
4155 int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
4156 {
4157 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
4158 }
4159
4160
4161 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4162 {
4163 pvr2_trace(PVR2_TRACE_INIT,
4164 "Requesting decoder reset");
4165 if (hdw->decoder_client_id) {
4166 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4167 core, reset, 0);
4168 pvr2_hdw_cx25840_vbi_hack(hdw);
4169 return 0;
4170 }
4171 pvr2_trace(PVR2_TRACE_INIT,
4172 "Unable to reset decoder: nothing attached");
4173 return -ENOTTY;
4174 }
4175
4176
4177 static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
4178 {
4179 hdw->flag_ok = !0;
4180 return pvr2_issue_simple_cmd(hdw,
4181 FX2CMD_HCW_DEMOD_RESETIN |
4182 (1 << 8) |
4183 ((onoff ? 1 : 0) << 16));
4184 }
4185
4186
4187 static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
4188 {
4189 hdw->flag_ok = !0;
4190 return pvr2_issue_simple_cmd(hdw,(onoff ?
4191 FX2CMD_ONAIR_DTV_POWER_ON :
4192 FX2CMD_ONAIR_DTV_POWER_OFF));
4193 }
4194
4195
4196 static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4197 int onoff)
4198 {
4199 return pvr2_issue_simple_cmd(hdw,(onoff ?
4200 FX2CMD_ONAIR_DTV_STREAMING_ON :
4201 FX2CMD_ONAIR_DTV_STREAMING_OFF));
4202 }
4203
4204
4205 static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4206 {
4207 int cmode;
4208 /* Compare digital/analog desired setting with current setting. If
4209 they don't match, fix it... */
4210 cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4211 if (cmode == hdw->pathway_state) {
4212 /* They match; nothing to do */
4213 return;
4214 }
4215
4216 switch (hdw->hdw_desc->digital_control_scheme) {
4217 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4218 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4219 if (cmode == PVR2_PATHWAY_ANALOG) {
4220 /* If moving to analog mode, also force the decoder
4221 to reset. If no decoder is attached, then it's
4222 ok to ignore this because if/when the decoder
4223 attaches, it will reset itself at that time. */
4224 pvr2_hdw_cmd_decoder_reset(hdw);
4225 }
4226 break;
4227 case PVR2_DIGITAL_SCHEME_ONAIR:
4228 /* Supposedly we should always have the power on whether in
4229 digital or analog mode. But for now do what appears to
4230 work... */
4231 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
4232 break;
4233 default: break;
4234 }
4235
4236 pvr2_hdw_untrip_unlocked(hdw);
4237 hdw->pathway_state = cmode;
4238 }
4239
4240
4241 static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
4242 {
4243 /* change some GPIO data
4244 *
4245 * note: bit d7 of dir appears to control the LED,
4246 * so we shut it off here.
4247 *
4248 */
4249 if (onoff) {
4250 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
4251 } else {
4252 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
4253 }
4254 pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
4255 }
4256
4257
4258 typedef void (*led_method_func)(struct pvr2_hdw *,int);
4259
4260 static led_method_func led_methods[] = {
4261 [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4262 };
4263
4264
4265 /* Toggle LED */
4266 static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4267 {
4268 unsigned int scheme_id;
4269 led_method_func fp;
4270
4271 if ((!onoff) == (!hdw->led_on)) return;
4272
4273 hdw->led_on = onoff != 0;
4274
4275 scheme_id = hdw->hdw_desc->led_scheme;
4276 if (scheme_id < ARRAY_SIZE(led_methods)) {
4277 fp = led_methods[scheme_id];
4278 } else {
4279 fp = NULL;
4280 }
4281
4282 if (fp) (*fp)(hdw,onoff);
4283 }
4284
4285
4286 /* Stop / start video stream transport */
4287 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
4288 {
4289 int ret;
4290
4291 /* If we're in analog mode, then just issue the usual analog
4292 command. */
4293 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4294 return pvr2_issue_simple_cmd(hdw,
4295 (runFl ?
4296 FX2CMD_STREAMING_ON :
4297 FX2CMD_STREAMING_OFF));
4298 /*Note: Not reached */
4299 }
4300
4301 if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4302 /* Whoops, we don't know what mode we're in... */
4303 return -EINVAL;
4304 }
4305
4306 /* To get here we have to be in digital mode. The mechanism here
4307 is unfortunately different for different vendors. So we switch
4308 on the device's digital scheme attribute in order to figure out
4309 what to do. */
4310 switch (hdw->hdw_desc->digital_control_scheme) {
4311 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4312 return pvr2_issue_simple_cmd(hdw,
4313 (runFl ?
4314 FX2CMD_HCW_DTV_STREAMING_ON :
4315 FX2CMD_HCW_DTV_STREAMING_OFF));
4316 case PVR2_DIGITAL_SCHEME_ONAIR:
4317 ret = pvr2_issue_simple_cmd(hdw,
4318 (runFl ?
4319 FX2CMD_STREAMING_ON :
4320 FX2CMD_STREAMING_OFF));
4321 if (ret) return ret;
4322 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4323 default:
4324 return -EINVAL;
4325 }
4326 }
4327
4328
4329 /* Evaluate whether or not state_pathway_ok can change */
4330 static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4331 {
4332 if (hdw->state_pathway_ok) {
4333 /* Nothing to do if pathway is already ok */
4334 return 0;
4335 }
4336 if (!hdw->state_pipeline_idle) {
4337 /* Not allowed to change anything if pipeline is not idle */
4338 return 0;
4339 }
4340 pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4341 hdw->state_pathway_ok = !0;
4342 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
4343 return !0;
4344 }
4345
4346
4347 /* Evaluate whether or not state_encoder_ok can change */
4348 static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4349 {
4350 if (hdw->state_encoder_ok) return 0;
4351 if (hdw->flag_tripped) return 0;
4352 if (hdw->state_encoder_run) return 0;
4353 if (hdw->state_encoder_config) return 0;
4354 if (hdw->state_decoder_run) return 0;
4355 if (hdw->state_usbstream_run) return 0;
4356 if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4357 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4358 } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4359 return 0;
4360 }
4361
4362 if (pvr2_upload_firmware2(hdw) < 0) {
4363 hdw->flag_tripped = !0;
4364 trace_stbit("flag_tripped",hdw->flag_tripped);
4365 return !0;
4366 }
4367 hdw->state_encoder_ok = !0;
4368 trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4369 return !0;
4370 }
4371
4372
4373 /* Evaluate whether or not state_encoder_config can change */
4374 static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4375 {
4376 if (hdw->state_encoder_config) {
4377 if (hdw->state_encoder_ok) {
4378 if (hdw->state_pipeline_req &&
4379 !hdw->state_pipeline_pause) return 0;
4380 }
4381 hdw->state_encoder_config = 0;
4382 hdw->state_encoder_waitok = 0;
4383 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4384 /* paranoia - solve race if timer just completed */
4385 del_timer_sync(&hdw->encoder_wait_timer);
4386 } else {
4387 if (!hdw->state_pathway_ok ||
4388 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4389 !hdw->state_encoder_ok ||
4390 !hdw->state_pipeline_idle ||
4391 hdw->state_pipeline_pause ||
4392 !hdw->state_pipeline_req ||
4393 !hdw->state_pipeline_config) {
4394 /* We must reset the enforced wait interval if
4395 anything has happened that might have disturbed
4396 the encoder. This should be a rare case. */
4397 if (timer_pending(&hdw->encoder_wait_timer)) {
4398 del_timer_sync(&hdw->encoder_wait_timer);
4399 }
4400 if (hdw->state_encoder_waitok) {
4401 /* Must clear the state - therefore we did
4402 something to a state bit and must also
4403 return true. */
4404 hdw->state_encoder_waitok = 0;
4405 trace_stbit("state_encoder_waitok",
4406 hdw->state_encoder_waitok);
4407 return !0;
4408 }
4409 return 0;
4410 }
4411 if (!hdw->state_encoder_waitok) {
4412 if (!timer_pending(&hdw->encoder_wait_timer)) {
4413 /* waitok flag wasn't set and timer isn't
4414 running. Check flag once more to avoid
4415 a race then start the timer. This is
4416 the point when we measure out a minimal
4417 quiet interval before doing something to
4418 the encoder. */
4419 if (!hdw->state_encoder_waitok) {
4420 hdw->encoder_wait_timer.expires =
4421 jiffies +
4422 (HZ * TIME_MSEC_ENCODER_WAIT
4423 / 1000);
4424 add_timer(&hdw->encoder_wait_timer);
4425 }
4426 }
4427 /* We can't continue until we know we have been
4428 quiet for the interval measured by this
4429 timer. */
4430 return 0;
4431 }
4432 pvr2_encoder_configure(hdw);
4433 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4434 }
4435 trace_stbit("state_encoder_config",hdw->state_encoder_config);
4436 return !0;
4437 }
4438
4439
4440 /* Return true if the encoder should not be running. */
4441 static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4442 {
4443 if (!hdw->state_encoder_ok) {
4444 /* Encoder isn't healthy at the moment, so stop it. */
4445 return !0;
4446 }
4447 if (!hdw->state_pathway_ok) {
4448 /* Mode is not understood at the moment (i.e. it wants to
4449 change), so encoder must be stopped. */
4450 return !0;
4451 }
4452
4453 switch (hdw->pathway_state) {
4454 case PVR2_PATHWAY_ANALOG:
4455 if (!hdw->state_decoder_run) {
4456 /* We're in analog mode and the decoder is not
4457 running; thus the encoder should be stopped as
4458 well. */
4459 return !0;
4460 }
4461 break;
4462 case PVR2_PATHWAY_DIGITAL:
4463 if (hdw->state_encoder_runok) {
4464 /* This is a funny case. We're in digital mode so
4465 really the encoder should be stopped. However
4466 if it really is running, only kill it after
4467 runok has been set. This gives a chance for the
4468 onair quirk to function (encoder must run
4469 briefly first, at least once, before onair
4470 digital streaming can work). */
4471 return !0;
4472 }
4473 break;
4474 default:
4475 /* Unknown mode; so encoder should be stopped. */
4476 return !0;
4477 }
4478
4479 /* If we get here, we haven't found a reason to stop the
4480 encoder. */
4481 return 0;
4482 }
4483
4484
4485 /* Return true if the encoder should be running. */
4486 static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4487 {
4488 if (!hdw->state_encoder_ok) {
4489 /* Don't run the encoder if it isn't healthy... */
4490 return 0;
4491 }
4492 if (!hdw->state_pathway_ok) {
4493 /* Don't run the encoder if we don't (yet) know what mode
4494 we need to be in... */
4495 return 0;
4496 }
4497
4498 switch (hdw->pathway_state) {
4499 case PVR2_PATHWAY_ANALOG:
4500 if (hdw->state_decoder_run && hdw->state_decoder_ready) {
4501 /* In analog mode, if the decoder is running, then
4502 run the encoder. */
4503 return !0;
4504 }
4505 break;
4506 case PVR2_PATHWAY_DIGITAL:
4507 if ((hdw->hdw_desc->digital_control_scheme ==
4508 PVR2_DIGITAL_SCHEME_ONAIR) &&
4509 !hdw->state_encoder_runok) {
4510 /* This is a quirk. OnAir hardware won't stream
4511 digital until the encoder has been run at least
4512 once, for a minimal period of time (empiricially
4513 measured to be 1/4 second). So if we're on
4514 OnAir hardware and the encoder has never been
4515 run at all, then start the encoder. Normal
4516 state machine logic in the driver will
4517 automatically handle the remaining bits. */
4518 return !0;
4519 }
4520 break;
4521 default:
4522 /* For completeness (unknown mode; encoder won't run ever) */
4523 break;
4524 }
4525 /* If we get here, then we haven't found any reason to run the
4526 encoder, so don't run it. */
4527 return 0;
4528 }
4529
4530
4531 /* Evaluate whether or not state_encoder_run can change */
4532 static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4533 {
4534 if (hdw->state_encoder_run) {
4535 if (!state_check_disable_encoder_run(hdw)) return 0;
4536 if (hdw->state_encoder_ok) {
4537 del_timer_sync(&hdw->encoder_run_timer);
4538 if (pvr2_encoder_stop(hdw) < 0) return !0;
4539 }
4540 hdw->state_encoder_run = 0;
4541 } else {
4542 if (!state_check_enable_encoder_run(hdw)) return 0;
4543 if (pvr2_encoder_start(hdw) < 0) return !0;
4544 hdw->state_encoder_run = !0;
4545 if (!hdw->state_encoder_runok) {
4546 hdw->encoder_run_timer.expires =
4547 jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
4548 add_timer(&hdw->encoder_run_timer);
4549 }
4550 }
4551 trace_stbit("state_encoder_run",hdw->state_encoder_run);
4552 return !0;
4553 }
4554
4555
4556 /* Timeout function for quiescent timer. */
4557 static void pvr2_hdw_quiescent_timeout(unsigned long data)
4558 {
4559 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4560 hdw->state_decoder_quiescent = !0;
4561 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4562 hdw->state_stale = !0;
4563 queue_work(hdw->workqueue,&hdw->workpoll);
4564 }
4565
4566
4567 /* Timeout function for decoder stabilization timer. */
4568 static void pvr2_hdw_decoder_stabilization_timeout(unsigned long data)
4569 {
4570 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4571 hdw->state_decoder_ready = !0;
4572 trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
4573 hdw->state_stale = !0;
4574 queue_work(hdw->workqueue, &hdw->workpoll);
4575 }
4576
4577
4578 /* Timeout function for encoder wait timer. */
4579 static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4580 {
4581 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4582 hdw->state_encoder_waitok = !0;
4583 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4584 hdw->state_stale = !0;
4585 queue_work(hdw->workqueue,&hdw->workpoll);
4586 }
4587
4588
4589 /* Timeout function for encoder run timer. */
4590 static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4591 {
4592 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4593 if (!hdw->state_encoder_runok) {
4594 hdw->state_encoder_runok = !0;
4595 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4596 hdw->state_stale = !0;
4597 queue_work(hdw->workqueue,&hdw->workpoll);
4598 }
4599 }
4600
4601
4602 /* Evaluate whether or not state_decoder_run can change */
4603 static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4604 {
4605 if (hdw->state_decoder_run) {
4606 if (hdw->state_encoder_ok) {
4607 if (hdw->state_pipeline_req &&
4608 !hdw->state_pipeline_pause &&
4609 hdw->state_pathway_ok) return 0;
4610 }
4611 if (!hdw->flag_decoder_missed) {
4612 pvr2_decoder_enable(hdw,0);
4613 }
4614 hdw->state_decoder_quiescent = 0;
4615 hdw->state_decoder_run = 0;
4616 /* paranoia - solve race if timer(s) just completed */
4617 del_timer_sync(&hdw->quiescent_timer);
4618 /* Kill the stabilization timer, in case we're killing the
4619 encoder before the previous stabilization interval has
4620 been properly timed. */
4621 del_timer_sync(&hdw->decoder_stabilization_timer);
4622 hdw->state_decoder_ready = 0;
4623 } else {
4624 if (!hdw->state_decoder_quiescent) {
4625 if (!timer_pending(&hdw->quiescent_timer)) {
4626 /* We don't do something about the
4627 quiescent timer until right here because
4628 we also want to catch cases where the
4629 decoder was already not running (like
4630 after initialization) as opposed to
4631 knowing that we had just stopped it.
4632 The second flag check is here to cover a
4633 race - the timer could have run and set
4634 this flag just after the previous check
4635 but before we did the pending check. */
4636 if (!hdw->state_decoder_quiescent) {
4637 hdw->quiescent_timer.expires =
4638 jiffies +
4639 (HZ * TIME_MSEC_DECODER_WAIT
4640 / 1000);
4641 add_timer(&hdw->quiescent_timer);
4642 }
4643 }
4644 /* Don't allow decoder to start again until it has
4645 been quiesced first. This little detail should
4646 hopefully further stabilize the encoder. */
4647 return 0;
4648 }
4649 if (!hdw->state_pathway_ok ||
4650 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4651 !hdw->state_pipeline_req ||
4652 hdw->state_pipeline_pause ||
4653 !hdw->state_pipeline_config ||
4654 !hdw->state_encoder_config ||
4655 !hdw->state_encoder_ok) return 0;
4656 del_timer_sync(&hdw->quiescent_timer);
4657 if (hdw->flag_decoder_missed) return 0;
4658 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4659 hdw->state_decoder_quiescent = 0;
4660 hdw->state_decoder_ready = 0;
4661 hdw->state_decoder_run = !0;
4662 if (hdw->decoder_client_id == PVR2_CLIENT_ID_SAA7115) {
4663 hdw->decoder_stabilization_timer.expires =
4664 jiffies +
4665 (HZ * TIME_MSEC_DECODER_STABILIZATION_WAIT /
4666 1000);
4667 add_timer(&hdw->decoder_stabilization_timer);
4668 } else {
4669 hdw->state_decoder_ready = !0;
4670 }
4671 }
4672 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4673 trace_stbit("state_decoder_run",hdw->state_decoder_run);
4674 trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
4675 return !0;
4676 }
4677
4678
4679 /* Evaluate whether or not state_usbstream_run can change */
4680 static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4681 {
4682 if (hdw->state_usbstream_run) {
4683 int fl = !0;
4684 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4685 fl = (hdw->state_encoder_ok &&
4686 hdw->state_encoder_run);
4687 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4688 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4689 fl = hdw->state_encoder_ok;
4690 }
4691 if (fl &&
4692 hdw->state_pipeline_req &&
4693 !hdw->state_pipeline_pause &&
4694 hdw->state_pathway_ok) {
4695 return 0;
4696 }
4697 pvr2_hdw_cmd_usbstream(hdw,0);
4698 hdw->state_usbstream_run = 0;
4699 } else {
4700 if (!hdw->state_pipeline_req ||
4701 hdw->state_pipeline_pause ||
4702 !hdw->state_pathway_ok) return 0;
4703 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4704 if (!hdw->state_encoder_ok ||
4705 !hdw->state_encoder_run) return 0;
4706 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4707 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4708 if (!hdw->state_encoder_ok) return 0;
4709 if (hdw->state_encoder_run) return 0;
4710 if (hdw->hdw_desc->digital_control_scheme ==
4711 PVR2_DIGITAL_SCHEME_ONAIR) {
4712 /* OnAir digital receivers won't stream
4713 unless the analog encoder has run first.
4714 Why? I have no idea. But don't even
4715 try until we know the analog side is
4716 known to have run. */
4717 if (!hdw->state_encoder_runok) return 0;
4718 }
4719 }
4720 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4721 hdw->state_usbstream_run = !0;
4722 }
4723 trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4724 return !0;
4725 }
4726
4727
4728 /* Attempt to configure pipeline, if needed */
4729 static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4730 {
4731 if (hdw->state_pipeline_config ||
4732 hdw->state_pipeline_pause) return 0;
4733 pvr2_hdw_commit_execute(hdw);
4734 return !0;
4735 }
4736
4737
4738 /* Update pipeline idle and pipeline pause tracking states based on other
4739 inputs. This must be called whenever the other relevant inputs have
4740 changed. */
4741 static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4742 {
4743 unsigned int st;
4744 int updatedFl = 0;
4745 /* Update pipeline state */
4746 st = !(hdw->state_encoder_run ||
4747 hdw->state_decoder_run ||
4748 hdw->state_usbstream_run ||
4749 (!hdw->state_decoder_quiescent));
4750 if (!st != !hdw->state_pipeline_idle) {
4751 hdw->state_pipeline_idle = st;
4752 updatedFl = !0;
4753 }
4754 if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4755 hdw->state_pipeline_pause = 0;
4756 updatedFl = !0;
4757 }
4758 return updatedFl;
4759 }
4760
4761
4762 typedef int (*state_eval_func)(struct pvr2_hdw *);
4763
4764 /* Set of functions to be run to evaluate various states in the driver. */
4765 static const state_eval_func eval_funcs[] = {
4766 state_eval_pathway_ok,
4767 state_eval_pipeline_config,
4768 state_eval_encoder_ok,
4769 state_eval_encoder_config,
4770 state_eval_decoder_run,
4771 state_eval_encoder_run,
4772 state_eval_usbstream_run,
4773 };
4774
4775
4776 /* Process various states and return true if we did anything interesting. */
4777 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4778 {
4779 unsigned int i;
4780 int state_updated = 0;
4781 int check_flag;
4782
4783 if (!hdw->state_stale) return 0;
4784 if ((hdw->fw1_state != FW1_STATE_OK) ||
4785 !hdw->flag_ok) {
4786 hdw->state_stale = 0;
4787 return !0;
4788 }
4789 /* This loop is the heart of the entire driver. It keeps trying to
4790 evaluate various bits of driver state until nothing changes for
4791 one full iteration. Each "bit of state" tracks some global
4792 aspect of the driver, e.g. whether decoder should run, if
4793 pipeline is configured, usb streaming is on, etc. We separately
4794 evaluate each of those questions based on other driver state to
4795 arrive at the correct running configuration. */
4796 do {
4797 check_flag = 0;
4798 state_update_pipeline_state(hdw);
4799 /* Iterate over each bit of state */
4800 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4801 if ((*eval_funcs[i])(hdw)) {
4802 check_flag = !0;
4803 state_updated = !0;
4804 state_update_pipeline_state(hdw);
4805 }
4806 }
4807 } while (check_flag && hdw->flag_ok);
4808 hdw->state_stale = 0;
4809 trace_stbit("state_stale",hdw->state_stale);
4810 return state_updated;
4811 }
4812
4813
4814 static unsigned int print_input_mask(unsigned int msk,
4815 char *buf,unsigned int acnt)
4816 {
4817 unsigned int idx,ccnt;
4818 unsigned int tcnt = 0;
4819 for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4820 if (!((1 << idx) & msk)) continue;
4821 ccnt = scnprintf(buf+tcnt,
4822 acnt-tcnt,
4823 "%s%s",
4824 (tcnt ? ", " : ""),
4825 control_values_input[idx]);
4826 tcnt += ccnt;
4827 }
4828 return tcnt;
4829 }
4830
4831
4832 static const char *pvr2_pathway_state_name(int id)
4833 {
4834 switch (id) {
4835 case PVR2_PATHWAY_ANALOG: return "analog";
4836 case PVR2_PATHWAY_DIGITAL: return "digital";
4837 default: return "unknown";
4838 }
4839 }
4840
4841
4842 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4843 char *buf,unsigned int acnt)
4844 {
4845 switch (which) {
4846 case 0:
4847 return scnprintf(
4848 buf,acnt,
4849 "driver:%s%s%s%s%s <mode=%s>",
4850 (hdw->flag_ok ? " <ok>" : " <fail>"),
4851 (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4852 (hdw->flag_disconnected ? " <disconnected>" :
4853 " <connected>"),
4854 (hdw->flag_tripped ? " <tripped>" : ""),
4855 (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4856 pvr2_pathway_state_name(hdw->pathway_state));
4857
4858 case 1:
4859 return scnprintf(
4860 buf,acnt,
4861 "pipeline:%s%s%s%s",
4862 (hdw->state_pipeline_idle ? " <idle>" : ""),
4863 (hdw->state_pipeline_config ?
4864 " <configok>" : " <stale>"),
4865 (hdw->state_pipeline_req ? " <req>" : ""),
4866 (hdw->state_pipeline_pause ? " <pause>" : ""));
4867 case 2:
4868 return scnprintf(
4869 buf,acnt,
4870 "worker:%s%s%s%s%s%s%s",
4871 (hdw->state_decoder_run ?
4872 (hdw->state_decoder_ready ?
4873 "<decode:run>" : " <decode:start>") :
4874 (hdw->state_decoder_quiescent ?
4875 "" : " <decode:stop>")),
4876 (hdw->state_decoder_quiescent ?
4877 " <decode:quiescent>" : ""),
4878 (hdw->state_encoder_ok ?
4879 "" : " <encode:init>"),
4880 (hdw->state_encoder_run ?
4881 (hdw->state_encoder_runok ?
4882 " <encode:run>" :
4883 " <encode:firstrun>") :
4884 (hdw->state_encoder_runok ?
4885 " <encode:stop>" :
4886 " <encode:virgin>")),
4887 (hdw->state_encoder_config ?
4888 " <encode:configok>" :
4889 (hdw->state_encoder_waitok ?
4890 "" : " <encode:waitok>")),
4891 (hdw->state_usbstream_run ?
4892 " <usb:run>" : " <usb:stop>"),
4893 (hdw->state_pathway_ok ?
4894 " <pathway:ok>" : ""));
4895 case 3:
4896 return scnprintf(
4897 buf,acnt,
4898 "state: %s",
4899 pvr2_get_state_name(hdw->master_state));
4900 case 4: {
4901 unsigned int tcnt = 0;
4902 unsigned int ccnt;
4903
4904 ccnt = scnprintf(buf,
4905 acnt,
4906 "Hardware supported inputs: ");
4907 tcnt += ccnt;
4908 tcnt += print_input_mask(hdw->input_avail_mask,
4909 buf+tcnt,
4910 acnt-tcnt);
4911 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4912 ccnt = scnprintf(buf+tcnt,
4913 acnt-tcnt,
4914 "; allowed inputs: ");
4915 tcnt += ccnt;
4916 tcnt += print_input_mask(hdw->input_allowed_mask,
4917 buf+tcnt,
4918 acnt-tcnt);
4919 }
4920 return tcnt;
4921 }
4922 case 5: {
4923 struct pvr2_stream_stats stats;
4924 if (!hdw->vid_stream) break;
4925 pvr2_stream_get_stats(hdw->vid_stream,
4926 &stats,
4927 0);
4928 return scnprintf(
4929 buf,acnt,
4930 "Bytes streamed=%u"
4931 " URBs: queued=%u idle=%u ready=%u"
4932 " processed=%u failed=%u",
4933 stats.bytes_processed,
4934 stats.buffers_in_queue,
4935 stats.buffers_in_idle,
4936 stats.buffers_in_ready,
4937 stats.buffers_processed,
4938 stats.buffers_failed);
4939 }
4940 case 6: {
4941 unsigned int id = hdw->ir_scheme_active;
4942 return scnprintf(buf, acnt, "ir scheme: id=%d %s", id,
4943 (id >= ARRAY_SIZE(ir_scheme_names) ?
4944 "?" : ir_scheme_names[id]));
4945 }
4946 default: break;
4947 }
4948 return 0;
4949 }
4950
4951
4952 /* Generate report containing info about attached sub-devices and attached
4953 i2c clients, including an indication of which attached i2c clients are
4954 actually sub-devices. */
4955 static unsigned int pvr2_hdw_report_clients(struct pvr2_hdw *hdw,
4956 char *buf, unsigned int acnt)
4957 {
4958 struct v4l2_subdev *sd;
4959 unsigned int tcnt = 0;
4960 unsigned int ccnt;
4961 struct i2c_client *client;
4962 const char *p;
4963 unsigned int id;
4964
4965 ccnt = scnprintf(buf, acnt, "Associated v4l2-subdev drivers and I2C clients:\n");
4966 tcnt += ccnt;
4967 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4968 id = sd->grp_id;
4969 p = NULL;
4970 if (id < ARRAY_SIZE(module_names)) p = module_names[id];
4971 if (p) {
4972 ccnt = scnprintf(buf + tcnt, acnt - tcnt, " %s:", p);
4973 tcnt += ccnt;
4974 } else {
4975 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4976 " (unknown id=%u):", id);
4977 tcnt += ccnt;
4978 }
4979 client = v4l2_get_subdevdata(sd);
4980 if (client) {
4981 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4982 " %s @ %02x\n", client->name,
4983 client->addr);
4984 tcnt += ccnt;
4985 } else {
4986 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4987 " no i2c client\n");
4988 tcnt += ccnt;
4989 }
4990 }
4991 return tcnt;
4992 }
4993
4994
4995 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4996 char *buf,unsigned int acnt)
4997 {
4998 unsigned int bcnt,ccnt,idx;
4999 bcnt = 0;
5000 LOCK_TAKE(hdw->big_lock);
5001 for (idx = 0; ; idx++) {
5002 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
5003 if (!ccnt) break;
5004 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
5005 if (!acnt) break;
5006 buf[0] = '\n'; ccnt = 1;
5007 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
5008 }
5009 ccnt = pvr2_hdw_report_clients(hdw, buf, acnt);
5010 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
5011 LOCK_GIVE(hdw->big_lock);
5012 return bcnt;
5013 }
5014
5015
5016 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
5017 {
5018 char buf[256];
5019 unsigned int idx, ccnt;
5020 unsigned int lcnt, ucnt;
5021
5022 for (idx = 0; ; idx++) {
5023 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
5024 if (!ccnt) break;
5025 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
5026 }
5027 ccnt = pvr2_hdw_report_clients(hdw, buf, sizeof(buf));
5028 ucnt = 0;
5029 while (ucnt < ccnt) {
5030 lcnt = 0;
5031 while ((lcnt + ucnt < ccnt) && (buf[lcnt + ucnt] != '\n')) {
5032 lcnt++;
5033 }
5034 printk(KERN_INFO "%s %.*s\n", hdw->name, lcnt, buf + ucnt);
5035 ucnt += lcnt + 1;
5036 }
5037 }
5038
5039
5040 /* Evaluate and update the driver's current state, taking various actions
5041 as appropriate for the update. */
5042 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
5043 {
5044 unsigned int st;
5045 int state_updated = 0;
5046 int callback_flag = 0;
5047 int analog_mode;
5048
5049 pvr2_trace(PVR2_TRACE_STBITS,
5050 "Drive state check START");
5051 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
5052 pvr2_hdw_state_log_state(hdw);
5053 }
5054
5055 /* Process all state and get back over disposition */
5056 state_updated = pvr2_hdw_state_update(hdw);
5057
5058 analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
5059
5060 /* Update master state based upon all other states. */
5061 if (!hdw->flag_ok) {
5062 st = PVR2_STATE_DEAD;
5063 } else if (hdw->fw1_state != FW1_STATE_OK) {
5064 st = PVR2_STATE_COLD;
5065 } else if ((analog_mode ||
5066 hdw->hdw_desc->flag_digital_requires_cx23416) &&
5067 !hdw->state_encoder_ok) {
5068 st = PVR2_STATE_WARM;
5069 } else if (hdw->flag_tripped ||
5070 (analog_mode && hdw->flag_decoder_missed)) {
5071 st = PVR2_STATE_ERROR;
5072 } else if (hdw->state_usbstream_run &&
5073 (!analog_mode ||
5074 (hdw->state_encoder_run && hdw->state_decoder_run))) {
5075 st = PVR2_STATE_RUN;
5076 } else {
5077 st = PVR2_STATE_READY;
5078 }
5079 if (hdw->master_state != st) {
5080 pvr2_trace(PVR2_TRACE_STATE,
5081 "Device state change from %s to %s",
5082 pvr2_get_state_name(hdw->master_state),
5083 pvr2_get_state_name(st));
5084 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
5085 hdw->master_state = st;
5086 state_updated = !0;
5087 callback_flag = !0;
5088 }
5089 if (state_updated) {
5090 /* Trigger anyone waiting on any state changes here. */
5091 wake_up(&hdw->state_wait_data);
5092 }
5093
5094 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
5095 pvr2_hdw_state_log_state(hdw);
5096 }
5097 pvr2_trace(PVR2_TRACE_STBITS,
5098 "Drive state check DONE callback=%d",callback_flag);
5099
5100 return callback_flag;
5101 }
5102
5103
5104 /* Cause kernel thread to check / update driver state */
5105 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
5106 {
5107 if (hdw->state_stale) return;
5108 hdw->state_stale = !0;
5109 trace_stbit("state_stale",hdw->state_stale);
5110 queue_work(hdw->workqueue,&hdw->workpoll);
5111 }
5112
5113
5114 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
5115 {
5116 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
5117 }
5118
5119
5120 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
5121 {
5122 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
5123 }
5124
5125
5126 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
5127 {
5128 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
5129 }
5130
5131
5132 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
5133 {
5134 u32 cval,nval;
5135 int ret;
5136 if (~msk) {
5137 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
5138 if (ret) return ret;
5139 nval = (cval & ~msk) | (val & msk);
5140 pvr2_trace(PVR2_TRACE_GPIO,
5141 "GPIO direction changing 0x%x:0x%x"
5142 " from 0x%x to 0x%x",
5143 msk,val,cval,nval);
5144 } else {
5145 nval = val;
5146 pvr2_trace(PVR2_TRACE_GPIO,
5147 "GPIO direction changing to 0x%x",nval);
5148 }
5149 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
5150 }
5151
5152
5153 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
5154 {
5155 u32 cval,nval;
5156 int ret;
5157 if (~msk) {
5158 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
5159 if (ret) return ret;
5160 nval = (cval & ~msk) | (val & msk);
5161 pvr2_trace(PVR2_TRACE_GPIO,
5162 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
5163 msk,val,cval,nval);
5164 } else {
5165 nval = val;
5166 pvr2_trace(PVR2_TRACE_GPIO,
5167 "GPIO output changing to 0x%x",nval);
5168 }
5169 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
5170 }
5171
5172
5173 void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
5174 {
5175 struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
5176 memset(vtp, 0, sizeof(*vtp));
5177 vtp->type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ?
5178 V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
5179 hdw->tuner_signal_stale = 0;
5180 /* Note: There apparently is no replacement for VIDIOC_CROPCAP
5181 using v4l2-subdev - therefore we can't support that AT ALL right
5182 now. (Of course, no sub-drivers seem to implement it either.
5183 But now it's a a chicken and egg problem...) */
5184 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner, vtp);
5185 pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll"
5186 " type=%u strength=%u audio=0x%x cap=0x%x"
5187 " low=%u hi=%u",
5188 vtp->type,
5189 vtp->signal, vtp->rxsubchans, vtp->capability,
5190 vtp->rangelow, vtp->rangehigh);
5191
5192 /* We have to do this to avoid getting into constant polling if
5193 there's nobody to answer a poll of cropcap info. */
5194 hdw->cropcap_stale = 0;
5195 }
5196
5197
5198 unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5199 {
5200 return hdw->input_avail_mask;
5201 }
5202
5203
5204 unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5205 {
5206 return hdw->input_allowed_mask;
5207 }
5208
5209
5210 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5211 {
5212 if (hdw->input_val != v) {
5213 hdw->input_val = v;
5214 hdw->input_dirty = !0;
5215 }
5216
5217 /* Handle side effects - if we switch to a mode that needs the RF
5218 tuner, then select the right frequency choice as well and mark
5219 it dirty. */
5220 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5221 hdw->freqSelector = 0;
5222 hdw->freqDirty = !0;
5223 } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5224 (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5225 hdw->freqSelector = 1;
5226 hdw->freqDirty = !0;
5227 }
5228 return 0;
5229 }
5230
5231
5232 int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5233 unsigned int change_mask,
5234 unsigned int change_val)
5235 {
5236 int ret = 0;
5237 unsigned int nv,m,idx;
5238 LOCK_TAKE(hdw->big_lock);
5239 do {
5240 nv = hdw->input_allowed_mask & ~change_mask;
5241 nv |= (change_val & change_mask);
5242 nv &= hdw->input_avail_mask;
5243 if (!nv) {
5244 /* No legal modes left; return error instead. */
5245 ret = -EPERM;
5246 break;
5247 }
5248 hdw->input_allowed_mask = nv;
5249 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5250 /* Current mode is still in the allowed mask, so
5251 we're done. */
5252 break;
5253 }
5254 /* Select and switch to a mode that is still in the allowed
5255 mask */
5256 if (!hdw->input_allowed_mask) {
5257 /* Nothing legal; give up */
5258 break;
5259 }
5260 m = hdw->input_allowed_mask;
5261 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5262 if (!((1 << idx) & m)) continue;
5263 pvr2_hdw_set_input(hdw,idx);
5264 break;
5265 }
5266 } while (0);
5267 LOCK_GIVE(hdw->big_lock);
5268 return ret;
5269 }
5270
5271
5272 /* Find I2C address of eeprom */
5273 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
5274 {
5275 int result;
5276 LOCK_TAKE(hdw->ctl_lock); do {
5277 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
5278 result = pvr2_send_request(hdw,
5279 hdw->cmd_buffer,1,
5280 hdw->cmd_buffer,1);
5281 if (result < 0) break;
5282 result = hdw->cmd_buffer[0];
5283 } while(0); LOCK_GIVE(hdw->ctl_lock);
5284 return result;
5285 }
5286
5287
5288 int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
5289 struct v4l2_dbg_match *match, u64 reg_id,
5290 int setFl, u64 *val_ptr)
5291 {
5292 #ifdef CONFIG_VIDEO_ADV_DEBUG
5293 struct v4l2_dbg_register req;
5294 int stat = 0;
5295 int okFl = 0;
5296
5297 if (!capable(CAP_SYS_ADMIN)) return -EPERM;
5298
5299 req.match = *match;
5300 req.reg = reg_id;
5301 if (setFl) req.val = *val_ptr;
5302 /* It would be nice to know if a sub-device answered the request */
5303 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, g_register, &req);
5304 if (!setFl) *val_ptr = req.val;
5305 if (okFl) {
5306 return stat;
5307 }
5308 return -EINVAL;
5309 #else
5310 return -ENOSYS;
5311 #endif
5312 }
5313
5314
5315 /*
5316 Stuff for Emacs to see, in order to encourage consistent editing style:
5317 *** Local Variables: ***
5318 *** mode: c ***
5319 *** fill-column: 75 ***
5320 *** tab-width: 8 ***
5321 *** c-basic-offset: 8 ***
5322 *** End: ***
5323 */
linux-next