2 * Copyright (C) 2010 Marvell International Ltd.
3 * Zhangfei Gao <zhangfei.gao@marvell.com>
4 * Kevin Wang <dwang4@marvell.com>
5 * Mingwei Wang <mwwang@marvell.com>
6 * Philip Rakity <prakity@marvell.com>
7 * Mark Brown <markb@marvell.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
22 #include <linux/clk.h>
24 #include <linux/gpio.h>
25 #include <linux/mmc/card.h>
26 #include <linux/mmc/host.h>
27 #include <linux/platform_data/pxa_sdhci.h>
28 #include <linux/slab.h>
29 #include <linux/delay.h>
30 #include <linux/module.h>
32 #include "sdhci-pltfm.h"
34 #define SD_CLOCK_BURST_SIZE_SETUP 0x10A
35 #define SDCLK_SEL 0x100
36 #define SDCLK_DELAY_SHIFT 9
37 #define SDCLK_DELAY_MASK 0x1f
39 #define SD_CFG_FIFO_PARAM 0x100
40 #define SDCFG_GEN_PAD_CLK_ON (1<<6)
41 #define SDCFG_GEN_PAD_CLK_CNT_MASK 0xFF
42 #define SDCFG_GEN_PAD_CLK_CNT_SHIFT 24
44 #define SD_SPI_MODE 0x108
45 #define SD_CE_ATA_1 0x10C
47 #define SD_CE_ATA_2 0x10E
48 #define SDCE_MISC_INT (1<<2)
49 #define SDCE_MISC_INT_EN (1<<1)
51 static void pxav3_set_private_registers(struct sdhci_host
*host
, u8 mask
)
53 struct platform_device
*pdev
= to_platform_device(mmc_dev(host
->mmc
));
54 struct sdhci_pxa_platdata
*pdata
= pdev
->dev
.platform_data
;
56 if (mask
== SDHCI_RESET_ALL
) {
58 * tune timing of read data/command when crc error happen
59 * no performance impact
61 if (pdata
&& 0 != pdata
->clk_delay_cycles
) {
64 tmp
= readw(host
->ioaddr
+ SD_CLOCK_BURST_SIZE_SETUP
);
65 tmp
|= (pdata
->clk_delay_cycles
& SDCLK_DELAY_MASK
)
68 writew(tmp
, host
->ioaddr
+ SD_CLOCK_BURST_SIZE_SETUP
);
73 #define MAX_WAIT_COUNT 5
74 static void pxav3_gen_init_74_clocks(struct sdhci_host
*host
, u8 power_mode
)
76 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
77 struct sdhci_pxa
*pxa
= pltfm_host
->priv
;
81 if (pxa
->power_mode
== MMC_POWER_UP
82 && power_mode
== MMC_POWER_ON
) {
84 dev_dbg(mmc_dev(host
->mmc
),
85 "%s: slot->power_mode = %d,"
86 "ios->power_mode = %d\n",
91 /* set we want notice of when 74 clocks are sent */
92 tmp
= readw(host
->ioaddr
+ SD_CE_ATA_2
);
93 tmp
|= SDCE_MISC_INT_EN
;
94 writew(tmp
, host
->ioaddr
+ SD_CE_ATA_2
);
96 /* start sending the 74 clocks */
97 tmp
= readw(host
->ioaddr
+ SD_CFG_FIFO_PARAM
);
98 tmp
|= SDCFG_GEN_PAD_CLK_ON
;
99 writew(tmp
, host
->ioaddr
+ SD_CFG_FIFO_PARAM
);
101 /* slowest speed is about 100KHz or 10usec per clock */
105 while (count
++ < MAX_WAIT_COUNT
) {
106 if ((readw(host
->ioaddr
+ SD_CE_ATA_2
)
107 & SDCE_MISC_INT
) == 0)
112 if (count
== MAX_WAIT_COUNT
)
113 dev_warn(mmc_dev(host
->mmc
), "74 clock interrupt not cleared\n");
115 /* clear the interrupt bit if posted */
116 tmp
= readw(host
->ioaddr
+ SD_CE_ATA_2
);
117 tmp
|= SDCE_MISC_INT
;
118 writew(tmp
, host
->ioaddr
+ SD_CE_ATA_2
);
120 pxa
->power_mode
= power_mode
;
123 static int pxav3_set_uhs_signaling(struct sdhci_host
*host
, unsigned int uhs
)
128 * Set V18_EN -- UHS modes do not work without this.
129 * does not change signaling voltage
131 ctrl_2
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
133 /* Select Bus Speed Mode for host */
134 ctrl_2
&= ~SDHCI_CTRL_UHS_MASK
;
136 case MMC_TIMING_UHS_SDR12
:
137 ctrl_2
|= SDHCI_CTRL_UHS_SDR12
;
139 case MMC_TIMING_UHS_SDR25
:
140 ctrl_2
|= SDHCI_CTRL_UHS_SDR25
;
142 case MMC_TIMING_UHS_SDR50
:
143 ctrl_2
|= SDHCI_CTRL_UHS_SDR50
| SDHCI_CTRL_VDD_180
;
145 case MMC_TIMING_UHS_SDR104
:
146 ctrl_2
|= SDHCI_CTRL_UHS_SDR104
| SDHCI_CTRL_VDD_180
;
148 case MMC_TIMING_UHS_DDR50
:
149 ctrl_2
|= SDHCI_CTRL_UHS_DDR50
| SDHCI_CTRL_VDD_180
;
153 sdhci_writew(host
, ctrl_2
, SDHCI_HOST_CONTROL2
);
154 dev_dbg(mmc_dev(host
->mmc
),
155 "%s uhs = %d, ctrl_2 = %04X\n",
156 __func__
, uhs
, ctrl_2
);
161 static struct sdhci_ops pxav3_sdhci_ops
= {
162 .platform_reset_exit
= pxav3_set_private_registers
,
163 .set_uhs_signaling
= pxav3_set_uhs_signaling
,
164 .platform_send_init_74_clocks
= pxav3_gen_init_74_clocks
,
167 static int __devinit
sdhci_pxav3_probe(struct platform_device
*pdev
)
169 struct sdhci_pltfm_host
*pltfm_host
;
170 struct sdhci_pxa_platdata
*pdata
= pdev
->dev
.platform_data
;
171 struct device
*dev
= &pdev
->dev
;
172 struct sdhci_host
*host
= NULL
;
173 struct sdhci_pxa
*pxa
= NULL
;
177 pxa
= kzalloc(sizeof(struct sdhci_pxa
), GFP_KERNEL
);
181 host
= sdhci_pltfm_init(pdev
, NULL
);
184 return PTR_ERR(host
);
186 pltfm_host
= sdhci_priv(host
);
187 pltfm_host
->priv
= pxa
;
189 clk
= clk_get(dev
, "PXA-SDHCLK");
191 dev_err(dev
, "failed to get io clock\n");
195 pltfm_host
->clk
= clk
;
198 host
->quirks
= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
199 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
200 | SDHCI_QUIRK_32BIT_ADMA_SIZE
;
202 /* enable 1/8V DDR capable */
203 host
->mmc
->caps
|= MMC_CAP_1_8V_DDR
;
206 if (pdata
->flags
& PXA_FLAG_CARD_PERMANENT
) {
208 host
->quirks
|= SDHCI_QUIRK_BROKEN_CARD_DETECTION
;
209 host
->mmc
->caps
|= MMC_CAP_NONREMOVABLE
;
212 /* If slot design supports 8 bit data, indicate this to MMC. */
213 if (pdata
->flags
& PXA_FLAG_SD_8_BIT_CAPABLE_SLOT
)
214 host
->mmc
->caps
|= MMC_CAP_8_BIT_DATA
;
217 host
->quirks
|= pdata
->quirks
;
218 if (pdata
->host_caps
)
219 host
->mmc
->caps
|= pdata
->host_caps
;
221 host
->mmc
->pm_caps
|= pdata
->pm_caps
;
224 host
->ops
= &pxav3_sdhci_ops
;
226 ret
= sdhci_add_host(host
);
228 dev_err(&pdev
->dev
, "failed to add host\n");
232 platform_set_drvdata(pdev
, host
);
240 sdhci_pltfm_free(pdev
);
245 static int __devexit
sdhci_pxav3_remove(struct platform_device
*pdev
)
247 struct sdhci_host
*host
= platform_get_drvdata(pdev
);
248 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
249 struct sdhci_pxa
*pxa
= pltfm_host
->priv
;
251 sdhci_remove_host(host
, 1);
253 clk_disable(pltfm_host
->clk
);
254 clk_put(pltfm_host
->clk
);
255 sdhci_pltfm_free(pdev
);
258 platform_set_drvdata(pdev
, NULL
);
263 static struct platform_driver sdhci_pxav3_driver
= {
265 .name
= "sdhci-pxav3",
266 .owner
= THIS_MODULE
,
268 .probe
= sdhci_pxav3_probe
,
269 .remove
= __devexit_p(sdhci_pxav3_remove
),
271 .suspend
= sdhci_pltfm_suspend
,
272 .resume
= sdhci_pltfm_resume
,
275 static int __init
sdhci_pxav3_init(void)
277 return platform_driver_register(&sdhci_pxav3_driver
);
280 static void __exit
sdhci_pxav3_exit(void)
282 platform_driver_unregister(&sdhci_pxav3_driver
);
285 module_init(sdhci_pxav3_init
);
286 module_exit(sdhci_pxav3_exit
);
288 MODULE_DESCRIPTION("SDHCI driver for pxav3");
289 MODULE_AUTHOR("Marvell International Ltd.");
290 MODULE_LICENSE("GPL v2");