2 This program is free software; you can redistribute it and/or
3 modify it under the terms of the GNU General Public License
4 as published by the Free Software Foundation; either version 2
5 of the License, or (at your option) any later version.
7 This program is distributed in the hope that it will be useful,
8 but WITHOUT ANY WARRANTY; without even the implied warranty of
9 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 GNU General Public License for more details.
15 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
17 #define DRV_NAME "uli526x"
18 #define DRV_VERSION "0.9.3"
19 #define DRV_RELDATE "2005-7-29"
21 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/string.h>
25 #include <linux/timer.h>
26 #include <linux/errno.h>
27 #include <linux/ioport.h>
28 #include <linux/interrupt.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/skbuff.h>
35 #include <linux/delay.h>
36 #include <linux/spinlock.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/bitops.h>
40 #include <asm/processor.h>
43 #include <asm/uaccess.h>
46 /* Board/System/Debug information/definition ---------------- */
47 #define PCI_ULI5261_ID 0x526110B9 /* ULi M5261 ID*/
48 #define PCI_ULI5263_ID 0x526310B9 /* ULi M5263 ID*/
50 #define ULI526X_IO_SIZE 0x100
51 #define TX_DESC_CNT 0x20 /* Allocated Tx descriptors */
52 #define RX_DESC_CNT 0x30 /* Allocated Rx descriptors */
53 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
54 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
55 #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
56 #define TX_BUF_ALLOC 0x600
57 #define RX_ALLOC_SIZE 0x620
58 #define ULI526X_RESET 1
60 #define CR6_DEFAULT 0x22200000
61 #define CR7_DEFAULT 0x180c1
62 #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
63 #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
64 #define MAX_PACKET_SIZE 1514
65 #define ULI5261_MAX_MULTICAST 14
66 #define RX_COPY_SIZE 100
67 #define MAX_CHECK_PACKET 0x8000
69 #define ULI526X_10MHF 0
70 #define ULI526X_100MHF 1
71 #define ULI526X_10MFD 4
72 #define ULI526X_100MFD 5
73 #define ULI526X_AUTO 8
75 #define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */
76 #define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */
77 #define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */
78 #define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */
79 #define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */
80 #define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */
82 #define ULI526X_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
83 #define ULI526X_TX_TIMEOUT ((16*HZ)/2) /* tx packet time-out time 8 s" */
84 #define ULI526X_TX_KICK (4*HZ/2) /* tx packet Kick-out time 2 s" */
86 #define ULI526X_DBUG(dbug_now, msg, value) \
88 if (uli526x_debug || (dbug_now)) \
89 pr_err("%s %lx\n", (msg), (long) (value)); \
92 #define SHOW_MEDIA_TYPE(mode) \
93 pr_err("Change Speed to %sMhz %s duplex\n", \
94 mode & 1 ? "100" : "10", \
95 mode & 4 ? "full" : "half");
98 /* CR9 definition: SROM/MII */
99 #define CR9_SROM_READ 0x4800
101 #define CR9_SRCLK 0x2
102 #define CR9_CRDOUT 0x8
103 #define SROM_DATA_0 0x0
104 #define SROM_DATA_1 0x4
105 #define PHY_DATA_1 0x20000
106 #define PHY_DATA_0 0x00000
107 #define MDCLKH 0x10000
109 #define PHY_POWER_DOWN 0x800
111 #define SROM_V41_CODE 0x14
113 #define SROM_CLK_WRITE(data, ioaddr) \
114 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
116 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \
118 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
121 /* Structure/enum declaration ------------------------------- */
123 __le32 tdes0
, tdes1
, tdes2
, tdes3
; /* Data for the card */
124 char *tx_buf_ptr
; /* Data for us */
125 struct tx_desc
*next_tx_desc
;
126 } __attribute__(( aligned(32) ));
129 __le32 rdes0
, rdes1
, rdes2
, rdes3
; /* Data for the card */
130 struct sk_buff
*rx_skb_ptr
; /* Data for us */
131 struct rx_desc
*next_rx_desc
;
132 } __attribute__(( aligned(32) ));
134 struct uli526x_board_info
{
135 u32 chip_id
; /* Chip vendor/Device ID */
136 struct net_device
*next_dev
; /* next device */
137 struct pci_dev
*pdev
; /* PCI device */
140 long ioaddr
; /* I/O base address */
147 /* pointer for memory physical address */
148 dma_addr_t buf_pool_dma_ptr
; /* Tx buffer pool memory */
149 dma_addr_t buf_pool_dma_start
; /* Tx buffer pool align dword */
150 dma_addr_t desc_pool_dma_ptr
; /* descriptor pool memory */
151 dma_addr_t first_tx_desc_dma
;
152 dma_addr_t first_rx_desc_dma
;
154 /* descriptor pointer */
155 unsigned char *buf_pool_ptr
; /* Tx buffer pool memory */
156 unsigned char *buf_pool_start
; /* Tx buffer pool align dword */
157 unsigned char *desc_pool_ptr
; /* descriptor pool memory */
158 struct tx_desc
*first_tx_desc
;
159 struct tx_desc
*tx_insert_ptr
;
160 struct tx_desc
*tx_remove_ptr
;
161 struct rx_desc
*first_rx_desc
;
162 struct rx_desc
*rx_insert_ptr
;
163 struct rx_desc
*rx_ready_ptr
; /* packet come pointer */
164 unsigned long tx_packet_cnt
; /* transmitted packet count */
165 unsigned long rx_avail_cnt
; /* available rx descriptor count */
166 unsigned long interval_rx_cnt
; /* rx packet count a callback time */
169 u16 NIC_capability
; /* NIC media capability */
170 u16 PHY_reg4
; /* Saved Phyxcer register 4 value */
172 u8 media_mode
; /* user specify media mode */
173 u8 op_mode
; /* real work media mode */
175 u8 link_failed
; /* Ever link failed */
176 u8 wait_reset
; /* Hardware failed, need to reset */
177 struct timer_list timer
;
179 /* Driver defined statistic counter */
180 unsigned long tx_fifo_underrun
;
181 unsigned long tx_loss_carrier
;
182 unsigned long tx_no_carrier
;
183 unsigned long tx_late_collision
;
184 unsigned long tx_excessive_collision
;
185 unsigned long tx_jabber_timeout
;
186 unsigned long reset_count
;
187 unsigned long reset_cr8
;
188 unsigned long reset_fatal
;
189 unsigned long reset_TXtimeout
;
192 unsigned char srom
[128];
196 enum uli526x_offsets
{
197 DCR0
= 0x00, DCR1
= 0x08, DCR2
= 0x10, DCR3
= 0x18, DCR4
= 0x20,
198 DCR5
= 0x28, DCR6
= 0x30, DCR7
= 0x38, DCR8
= 0x40, DCR9
= 0x48,
199 DCR10
= 0x50, DCR11
= 0x58, DCR12
= 0x60, DCR13
= 0x68, DCR14
= 0x70,
203 enum uli526x_CR6_bits
{
204 CR6_RXSC
= 0x2, CR6_PBF
= 0x8, CR6_PM
= 0x40, CR6_PAM
= 0x80,
205 CR6_FDM
= 0x200, CR6_TXSC
= 0x2000, CR6_STI
= 0x100000,
206 CR6_SFT
= 0x200000, CR6_RXA
= 0x40000000, CR6_NO_PURGE
= 0x20000000
209 /* Global variable declaration ----------------------------- */
210 static int __devinitdata printed_version
;
211 static const char version
[] __devinitconst
=
212 "ULi M5261/M5263 net driver, version " DRV_VERSION
" (" DRV_RELDATE
")";
214 static int uli526x_debug
;
215 static unsigned char uli526x_media_mode
= ULI526X_AUTO
;
216 static u32 uli526x_cr6_user_set
;
218 /* For module input parameter */
223 /* function declaration ------------------------------------- */
224 static int uli526x_open(struct net_device
*);
225 static netdev_tx_t
uli526x_start_xmit(struct sk_buff
*,
226 struct net_device
*);
227 static int uli526x_stop(struct net_device
*);
228 static void uli526x_set_filter_mode(struct net_device
*);
229 static const struct ethtool_ops netdev_ethtool_ops
;
230 static u16
read_srom_word(long, int);
231 static irqreturn_t
uli526x_interrupt(int, void *);
232 #ifdef CONFIG_NET_POLL_CONTROLLER
233 static void uli526x_poll(struct net_device
*dev
);
235 static void uli526x_descriptor_init(struct uli526x_board_info
*, unsigned long);
236 static void allocate_rx_buffer(struct uli526x_board_info
*);
237 static void update_cr6(u32
, unsigned long);
238 static void send_filter_frame(struct net_device
*, int);
239 static u16
phy_read(unsigned long, u8
, u8
, u32
);
240 static u16
phy_readby_cr10(unsigned long, u8
, u8
);
241 static void phy_write(unsigned long, u8
, u8
, u16
, u32
);
242 static void phy_writeby_cr10(unsigned long, u8
, u8
, u16
);
243 static void phy_write_1bit(unsigned long, u32
, u32
);
244 static u16
phy_read_1bit(unsigned long, u32
);
245 static u8
uli526x_sense_speed(struct uli526x_board_info
*);
246 static void uli526x_process_mode(struct uli526x_board_info
*);
247 static void uli526x_timer(unsigned long);
248 static void uli526x_rx_packet(struct net_device
*, struct uli526x_board_info
*);
249 static void uli526x_free_tx_pkt(struct net_device
*, struct uli526x_board_info
*);
250 static void uli526x_reuse_skb(struct uli526x_board_info
*, struct sk_buff
*);
251 static void uli526x_dynamic_reset(struct net_device
*);
252 static void uli526x_free_rxbuffer(struct uli526x_board_info
*);
253 static void uli526x_init(struct net_device
*);
254 static void uli526x_set_phyxcer(struct uli526x_board_info
*);
256 /* ULI526X network board routine ---------------------------- */
258 static const struct net_device_ops netdev_ops
= {
259 .ndo_open
= uli526x_open
,
260 .ndo_stop
= uli526x_stop
,
261 .ndo_start_xmit
= uli526x_start_xmit
,
262 .ndo_set_rx_mode
= uli526x_set_filter_mode
,
263 .ndo_change_mtu
= eth_change_mtu
,
264 .ndo_set_mac_address
= eth_mac_addr
,
265 .ndo_validate_addr
= eth_validate_addr
,
266 #ifdef CONFIG_NET_POLL_CONTROLLER
267 .ndo_poll_controller
= uli526x_poll
,
272 * Search ULI526X board, allocate space and register it
275 static int __devinit
uli526x_init_one (struct pci_dev
*pdev
,
276 const struct pci_device_id
*ent
)
278 struct uli526x_board_info
*db
; /* board information structure */
279 struct net_device
*dev
;
282 ULI526X_DBUG(0, "uli526x_init_one()", 0);
284 if (!printed_version
++)
285 pr_info("%s\n", version
);
287 /* Init network device */
288 dev
= alloc_etherdev(sizeof(*db
));
291 SET_NETDEV_DEV(dev
, &pdev
->dev
);
293 if (pci_set_dma_mask(pdev
, DMA_BIT_MASK(32))) {
294 pr_warn("32-bit PCI DMA not available\n");
299 /* Enable Master/IO access, Disable memory access */
300 err
= pci_enable_device(pdev
);
304 if (!pci_resource_start(pdev
, 0)) {
305 pr_err("I/O base is zero\n");
307 goto err_out_disable
;
310 if (pci_resource_len(pdev
, 0) < (ULI526X_IO_SIZE
) ) {
311 pr_err("Allocated I/O size too small\n");
313 goto err_out_disable
;
316 if (pci_request_regions(pdev
, DRV_NAME
)) {
317 pr_err("Failed to request PCI regions\n");
319 goto err_out_disable
;
322 /* Init system & device */
323 db
= netdev_priv(dev
);
325 /* Allocate Tx/Rx descriptor memory */
326 db
->desc_pool_ptr
= pci_alloc_consistent(pdev
, sizeof(struct tx_desc
) * DESC_ALL_CNT
+ 0x20, &db
->desc_pool_dma_ptr
);
327 if(db
->desc_pool_ptr
== NULL
)
332 db
->buf_pool_ptr
= pci_alloc_consistent(pdev
, TX_BUF_ALLOC
* TX_DESC_CNT
+ 4, &db
->buf_pool_dma_ptr
);
333 if(db
->buf_pool_ptr
== NULL
)
339 db
->first_tx_desc
= (struct tx_desc
*) db
->desc_pool_ptr
;
340 db
->first_tx_desc_dma
= db
->desc_pool_dma_ptr
;
341 db
->buf_pool_start
= db
->buf_pool_ptr
;
342 db
->buf_pool_dma_start
= db
->buf_pool_dma_ptr
;
344 db
->chip_id
= ent
->driver_data
;
345 db
->ioaddr
= pci_resource_start(pdev
, 0);
350 dev
->base_addr
= db
->ioaddr
;
351 dev
->irq
= pdev
->irq
;
352 pci_set_drvdata(pdev
, dev
);
354 /* Register some necessary functions */
355 dev
->netdev_ops
= &netdev_ops
;
356 dev
->ethtool_ops
= &netdev_ethtool_ops
;
358 spin_lock_init(&db
->lock
);
361 /* read 64 word srom data */
362 for (i
= 0; i
< 64; i
++)
363 ((__le16
*) db
->srom
)[i
] = cpu_to_le16(read_srom_word(db
->ioaddr
, i
));
365 /* Set Node address */
366 if(((u16
*) db
->srom
)[0] == 0xffff || ((u16
*) db
->srom
)[0] == 0) /* SROM absent, so read MAC address from ID Table */
368 outl(0x10000, db
->ioaddr
+ DCR0
); //Diagnosis mode
369 outl(0x1c0, db
->ioaddr
+ DCR13
); //Reset dianostic pointer port
370 outl(0, db
->ioaddr
+ DCR14
); //Clear reset port
371 outl(0x10, db
->ioaddr
+ DCR14
); //Reset ID Table pointer
372 outl(0, db
->ioaddr
+ DCR14
); //Clear reset port
373 outl(0, db
->ioaddr
+ DCR13
); //Clear CR13
374 outl(0x1b0, db
->ioaddr
+ DCR13
); //Select ID Table access port
375 //Read MAC address from CR14
376 for (i
= 0; i
< 6; i
++)
377 dev
->dev_addr
[i
] = inl(db
->ioaddr
+ DCR14
);
379 outl(0, db
->ioaddr
+ DCR13
); //Clear CR13
380 outl(0, db
->ioaddr
+ DCR0
); //Clear CR0
385 for (i
= 0; i
< 6; i
++)
386 dev
->dev_addr
[i
] = db
->srom
[20 + i
];
388 err
= register_netdev (dev
);
392 netdev_info(dev
, "ULi M%04lx at pci%s, %pM, irq %d\n",
393 ent
->driver_data
>> 16, pci_name(pdev
),
394 dev
->dev_addr
, dev
->irq
);
396 pci_set_master(pdev
);
401 pci_release_regions(pdev
);
403 if(db
->desc_pool_ptr
)
404 pci_free_consistent(pdev
, sizeof(struct tx_desc
) * DESC_ALL_CNT
+ 0x20,
405 db
->desc_pool_ptr
, db
->desc_pool_dma_ptr
);
407 if(db
->buf_pool_ptr
!= NULL
)
408 pci_free_consistent(pdev
, TX_BUF_ALLOC
* TX_DESC_CNT
+ 4,
409 db
->buf_pool_ptr
, db
->buf_pool_dma_ptr
);
411 pci_disable_device(pdev
);
413 pci_set_drvdata(pdev
, NULL
);
420 static void __devexit
uli526x_remove_one (struct pci_dev
*pdev
)
422 struct net_device
*dev
= pci_get_drvdata(pdev
);
423 struct uli526x_board_info
*db
= netdev_priv(dev
);
425 ULI526X_DBUG(0, "uli526x_remove_one()", 0);
427 pci_free_consistent(db
->pdev
, sizeof(struct tx_desc
) *
428 DESC_ALL_CNT
+ 0x20, db
->desc_pool_ptr
,
429 db
->desc_pool_dma_ptr
);
430 pci_free_consistent(db
->pdev
, TX_BUF_ALLOC
* TX_DESC_CNT
+ 4,
431 db
->buf_pool_ptr
, db
->buf_pool_dma_ptr
);
432 unregister_netdev(dev
);
433 pci_release_regions(pdev
);
434 free_netdev(dev
); /* free board information */
435 pci_set_drvdata(pdev
, NULL
);
436 pci_disable_device(pdev
);
437 ULI526X_DBUG(0, "uli526x_remove_one() exit", 0);
442 * Open the interface.
443 * The interface is opened whenever "ifconfig" activates it.
446 static int uli526x_open(struct net_device
*dev
)
449 struct uli526x_board_info
*db
= netdev_priv(dev
);
451 ULI526X_DBUG(0, "uli526x_open", 0);
453 /* system variable init */
454 db
->cr6_data
= CR6_DEFAULT
| uli526x_cr6_user_set
;
455 db
->tx_packet_cnt
= 0;
456 db
->rx_avail_cnt
= 0;
458 netif_carrier_off(dev
);
461 db
->NIC_capability
= 0xf; /* All capability*/
462 db
->PHY_reg4
= 0x1e0;
464 /* CR6 operation mode decision */
465 db
->cr6_data
|= ULI526X_TXTH_256
;
466 db
->cr0_data
= CR0_DEFAULT
;
468 /* Initialize ULI526X board */
471 ret
= request_irq(dev
->irq
, uli526x_interrupt
, IRQF_SHARED
, dev
->name
, dev
);
475 /* Active System Interface */
476 netif_wake_queue(dev
);
478 /* set and active a timer process */
479 init_timer(&db
->timer
);
480 db
->timer
.expires
= ULI526X_TIMER_WUT
+ HZ
* 2;
481 db
->timer
.data
= (unsigned long)dev
;
482 db
->timer
.function
= uli526x_timer
;
483 add_timer(&db
->timer
);
489 /* Initialize ULI526X board
490 * Reset ULI526X board
491 * Initialize TX/Rx descriptor chain structure
492 * Send the set-up frame
493 * Enable Tx/Rx machine
496 static void uli526x_init(struct net_device
*dev
)
498 struct uli526x_board_info
*db
= netdev_priv(dev
);
499 unsigned long ioaddr
= db
->ioaddr
;
506 ULI526X_DBUG(0, "uli526x_init()", 0);
508 /* Reset M526x MAC controller */
509 outl(ULI526X_RESET
, ioaddr
+ DCR0
); /* RESET MAC */
511 outl(db
->cr0_data
, ioaddr
+ DCR0
);
514 /* Phy addr : In some boards,M5261/M5263 phy address != 1 */
516 for(phy_tmp
=0;phy_tmp
<32;phy_tmp
++)
518 phy_value
=phy_read(db
->ioaddr
,phy_tmp
,3,db
->chip_id
);//peer add
519 if(phy_value
!= 0xffff&&phy_value
!=0)
521 db
->phy_addr
= phy_tmp
;
526 pr_warn("Can not find the phy address!!!\n");
527 /* Parser SROM and media mode */
528 db
->media_mode
= uli526x_media_mode
;
530 /* phyxcer capability setting */
531 phy_reg_reset
= phy_read(db
->ioaddr
, db
->phy_addr
, 0, db
->chip_id
);
532 phy_reg_reset
= (phy_reg_reset
| 0x8000);
533 phy_write(db
->ioaddr
, db
->phy_addr
, 0, phy_reg_reset
, db
->chip_id
);
535 /* See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management
536 * functions") or phy data sheet for details on phy reset
541 phy_read(db
->ioaddr
, db
->phy_addr
, 0, db
->chip_id
) & 0x8000)
544 /* Process Phyxcer Media Mode */
545 uli526x_set_phyxcer(db
);
547 /* Media Mode Process */
548 if ( !(db
->media_mode
& ULI526X_AUTO
) )
549 db
->op_mode
= db
->media_mode
; /* Force Mode */
551 /* Initialize Transmit/Receive decriptor and CR3/4 */
552 uli526x_descriptor_init(db
, ioaddr
);
554 /* Init CR6 to program M526X operation */
555 update_cr6(db
->cr6_data
, ioaddr
);
557 /* Send setup frame */
558 send_filter_frame(dev
, netdev_mc_count(dev
)); /* M5261/M5263 */
560 /* Init CR7, interrupt active bit */
561 db
->cr7_data
= CR7_DEFAULT
;
562 outl(db
->cr7_data
, ioaddr
+ DCR7
);
564 /* Init CR15, Tx jabber and Rx watchdog timer */
565 outl(db
->cr15_data
, ioaddr
+ DCR15
);
567 /* Enable ULI526X Tx/Rx function */
568 db
->cr6_data
|= CR6_RXSC
| CR6_TXSC
;
569 update_cr6(db
->cr6_data
, ioaddr
);
574 * Hardware start transmission.
575 * Send a packet to media from the upper layer.
578 static netdev_tx_t
uli526x_start_xmit(struct sk_buff
*skb
,
579 struct net_device
*dev
)
581 struct uli526x_board_info
*db
= netdev_priv(dev
);
582 struct tx_desc
*txptr
;
585 ULI526X_DBUG(0, "uli526x_start_xmit", 0);
587 /* Resource flag check */
588 netif_stop_queue(dev
);
590 /* Too large packet check */
591 if (skb
->len
> MAX_PACKET_SIZE
) {
592 netdev_err(dev
, "big packet = %d\n", (u16
)skb
->len
);
597 spin_lock_irqsave(&db
->lock
, flags
);
599 /* No Tx resource check, it never happen nromally */
600 if (db
->tx_packet_cnt
>= TX_FREE_DESC_CNT
) {
601 spin_unlock_irqrestore(&db
->lock
, flags
);
602 netdev_err(dev
, "No Tx resource %ld\n", db
->tx_packet_cnt
);
603 return NETDEV_TX_BUSY
;
606 /* Disable NIC interrupt */
607 outl(0, dev
->base_addr
+ DCR7
);
609 /* transmit this packet */
610 txptr
= db
->tx_insert_ptr
;
611 skb_copy_from_linear_data(skb
, txptr
->tx_buf_ptr
, skb
->len
);
612 txptr
->tdes1
= cpu_to_le32(0xe1000000 | skb
->len
);
614 /* Point to next transmit free descriptor */
615 db
->tx_insert_ptr
= txptr
->next_tx_desc
;
617 /* Transmit Packet Process */
618 if ( (db
->tx_packet_cnt
< TX_DESC_CNT
) ) {
619 txptr
->tdes0
= cpu_to_le32(0x80000000); /* Set owner bit */
620 db
->tx_packet_cnt
++; /* Ready to send */
621 outl(0x1, dev
->base_addr
+ DCR1
); /* Issue Tx polling */
622 dev
->trans_start
= jiffies
; /* saved time stamp */
625 /* Tx resource check */
626 if ( db
->tx_packet_cnt
< TX_FREE_DESC_CNT
)
627 netif_wake_queue(dev
);
629 /* Restore CR7 to enable interrupt */
630 spin_unlock_irqrestore(&db
->lock
, flags
);
631 outl(db
->cr7_data
, dev
->base_addr
+ DCR7
);
641 * Stop the interface.
642 * The interface is stopped when it is brought.
645 static int uli526x_stop(struct net_device
*dev
)
647 struct uli526x_board_info
*db
= netdev_priv(dev
);
648 unsigned long ioaddr
= dev
->base_addr
;
650 ULI526X_DBUG(0, "uli526x_stop", 0);
653 netif_stop_queue(dev
);
656 del_timer_sync(&db
->timer
);
658 /* Reset & stop ULI526X board */
659 outl(ULI526X_RESET
, ioaddr
+ DCR0
);
661 phy_write(db
->ioaddr
, db
->phy_addr
, 0, 0x8000, db
->chip_id
);
664 free_irq(dev
->irq
, dev
);
666 /* free allocated rx buffer */
667 uli526x_free_rxbuffer(db
);
674 * M5261/M5263 insterrupt handler
675 * receive the packet to upper layer, free the transmitted packet
678 static irqreturn_t
uli526x_interrupt(int irq
, void *dev_id
)
680 struct net_device
*dev
= dev_id
;
681 struct uli526x_board_info
*db
= netdev_priv(dev
);
682 unsigned long ioaddr
= dev
->base_addr
;
685 spin_lock_irqsave(&db
->lock
, flags
);
686 outl(0, ioaddr
+ DCR7
);
688 /* Got ULI526X status */
689 db
->cr5_data
= inl(ioaddr
+ DCR5
);
690 outl(db
->cr5_data
, ioaddr
+ DCR5
);
691 if ( !(db
->cr5_data
& 0x180c1) ) {
692 /* Restore CR7 to enable interrupt mask */
693 outl(db
->cr7_data
, ioaddr
+ DCR7
);
694 spin_unlock_irqrestore(&db
->lock
, flags
);
698 /* Check system status */
699 if (db
->cr5_data
& 0x2000) {
700 /* system bus error happen */
701 ULI526X_DBUG(1, "System bus error happen. CR5=", db
->cr5_data
);
703 db
->wait_reset
= 1; /* Need to RESET */
704 spin_unlock_irqrestore(&db
->lock
, flags
);
708 /* Received the coming packet */
709 if ( (db
->cr5_data
& 0x40) && db
->rx_avail_cnt
)
710 uli526x_rx_packet(dev
, db
);
712 /* reallocate rx descriptor buffer */
713 if (db
->rx_avail_cnt
<RX_DESC_CNT
)
714 allocate_rx_buffer(db
);
716 /* Free the transmitted descriptor */
717 if ( db
->cr5_data
& 0x01)
718 uli526x_free_tx_pkt(dev
, db
);
720 /* Restore CR7 to enable interrupt mask */
721 outl(db
->cr7_data
, ioaddr
+ DCR7
);
723 spin_unlock_irqrestore(&db
->lock
, flags
);
727 #ifdef CONFIG_NET_POLL_CONTROLLER
728 static void uli526x_poll(struct net_device
*dev
)
730 /* ISR grabs the irqsave lock, so this should be safe */
731 uli526x_interrupt(dev
->irq
, dev
);
736 * Free TX resource after TX complete
739 static void uli526x_free_tx_pkt(struct net_device
*dev
,
740 struct uli526x_board_info
* db
)
742 struct tx_desc
*txptr
;
745 txptr
= db
->tx_remove_ptr
;
746 while(db
->tx_packet_cnt
) {
747 tdes0
= le32_to_cpu(txptr
->tdes0
);
748 if (tdes0
& 0x80000000)
751 /* A packet sent completed */
753 dev
->stats
.tx_packets
++;
755 /* Transmit statistic counter */
756 if ( tdes0
!= 0x7fffffff ) {
757 dev
->stats
.collisions
+= (tdes0
>> 3) & 0xf;
758 dev
->stats
.tx_bytes
+= le32_to_cpu(txptr
->tdes1
) & 0x7ff;
759 if (tdes0
& TDES0_ERR_MASK
) {
760 dev
->stats
.tx_errors
++;
761 if (tdes0
& 0x0002) { /* UnderRun */
762 db
->tx_fifo_underrun
++;
763 if ( !(db
->cr6_data
& CR6_SFT
) ) {
764 db
->cr6_data
= db
->cr6_data
| CR6_SFT
;
765 update_cr6(db
->cr6_data
, db
->ioaddr
);
769 db
->tx_excessive_collision
++;
771 db
->tx_late_collision
++;
775 db
->tx_loss_carrier
++;
777 db
->tx_jabber_timeout
++;
781 txptr
= txptr
->next_tx_desc
;
784 /* Update TX remove pointer to next */
785 db
->tx_remove_ptr
= txptr
;
787 /* Resource available check */
788 if ( db
->tx_packet_cnt
< TX_WAKE_DESC_CNT
)
789 netif_wake_queue(dev
); /* Active upper layer, send again */
794 * Receive the come packet and pass to upper layer
797 static void uli526x_rx_packet(struct net_device
*dev
, struct uli526x_board_info
* db
)
799 struct rx_desc
*rxptr
;
804 rxptr
= db
->rx_ready_ptr
;
806 while(db
->rx_avail_cnt
) {
807 rdes0
= le32_to_cpu(rxptr
->rdes0
);
808 if (rdes0
& 0x80000000) /* packet owner check */
814 db
->interval_rx_cnt
++;
816 pci_unmap_single(db
->pdev
, le32_to_cpu(rxptr
->rdes2
), RX_ALLOC_SIZE
, PCI_DMA_FROMDEVICE
);
817 if ( (rdes0
& 0x300) != 0x300) {
818 /* A packet without First/Last flag */
820 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0
);
821 uli526x_reuse_skb(db
, rxptr
->rx_skb_ptr
);
823 /* A packet with First/Last flag */
824 rxlen
= ( (rdes0
>> 16) & 0x3fff) - 4;
826 /* error summary bit check */
827 if (rdes0
& 0x8000) {
828 /* This is a error packet */
829 dev
->stats
.rx_errors
++;
831 dev
->stats
.rx_fifo_errors
++;
833 dev
->stats
.rx_crc_errors
++;
835 dev
->stats
.rx_length_errors
++;
838 if ( !(rdes0
& 0x8000) ||
839 ((db
->cr6_data
& CR6_PM
) && (rxlen
>6)) ) {
840 struct sk_buff
*new_skb
= NULL
;
842 skb
= rxptr
->rx_skb_ptr
;
844 /* Good packet, send to upper layer */
845 /* Shorst packet used new SKB */
846 if ((rxlen
< RX_COPY_SIZE
) &&
847 (((new_skb
= dev_alloc_skb(rxlen
+ 2)) != NULL
))) {
849 /* size less than COPY_SIZE, allocate a rxlen SKB */
850 skb_reserve(skb
, 2); /* 16byte align */
851 memcpy(skb_put(skb
, rxlen
),
852 skb_tail_pointer(rxptr
->rx_skb_ptr
),
854 uli526x_reuse_skb(db
, rxptr
->rx_skb_ptr
);
858 skb
->protocol
= eth_type_trans(skb
, dev
);
860 dev
->stats
.rx_packets
++;
861 dev
->stats
.rx_bytes
+= rxlen
;
864 /* Reuse SKB buffer when the packet is error */
865 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0
);
866 uli526x_reuse_skb(db
, rxptr
->rx_skb_ptr
);
870 rxptr
= rxptr
->next_rx_desc
;
873 db
->rx_ready_ptr
= rxptr
;
878 * Set ULI526X multicast address
881 static void uli526x_set_filter_mode(struct net_device
* dev
)
883 struct uli526x_board_info
*db
= netdev_priv(dev
);
886 ULI526X_DBUG(0, "uli526x_set_filter_mode()", 0);
887 spin_lock_irqsave(&db
->lock
, flags
);
889 if (dev
->flags
& IFF_PROMISC
) {
890 ULI526X_DBUG(0, "Enable PROM Mode", 0);
891 db
->cr6_data
|= CR6_PM
| CR6_PBF
;
892 update_cr6(db
->cr6_data
, db
->ioaddr
);
893 spin_unlock_irqrestore(&db
->lock
, flags
);
897 if (dev
->flags
& IFF_ALLMULTI
||
898 netdev_mc_count(dev
) > ULI5261_MAX_MULTICAST
) {
899 ULI526X_DBUG(0, "Pass all multicast address",
900 netdev_mc_count(dev
));
901 db
->cr6_data
&= ~(CR6_PM
| CR6_PBF
);
902 db
->cr6_data
|= CR6_PAM
;
903 spin_unlock_irqrestore(&db
->lock
, flags
);
907 ULI526X_DBUG(0, "Set multicast address", netdev_mc_count(dev
));
908 send_filter_frame(dev
, netdev_mc_count(dev
)); /* M5261/M5263 */
909 spin_unlock_irqrestore(&db
->lock
, flags
);
913 ULi_ethtool_gset(struct uli526x_board_info
*db
, struct ethtool_cmd
*ecmd
)
915 ecmd
->supported
= (SUPPORTED_10baseT_Half
|
916 SUPPORTED_10baseT_Full
|
917 SUPPORTED_100baseT_Half
|
918 SUPPORTED_100baseT_Full
|
922 ecmd
->advertising
= (ADVERTISED_10baseT_Half
|
923 ADVERTISED_10baseT_Full
|
924 ADVERTISED_100baseT_Half
|
925 ADVERTISED_100baseT_Full
|
930 ecmd
->port
= PORT_MII
;
931 ecmd
->phy_address
= db
->phy_addr
;
933 ecmd
->transceiver
= XCVR_EXTERNAL
;
935 ethtool_cmd_speed_set(ecmd
, SPEED_10
);
936 ecmd
->duplex
= DUPLEX_HALF
;
938 if(db
->op_mode
==ULI526X_100MHF
|| db
->op_mode
==ULI526X_100MFD
)
940 ethtool_cmd_speed_set(ecmd
, SPEED_100
);
942 if(db
->op_mode
==ULI526X_10MFD
|| db
->op_mode
==ULI526X_100MFD
)
944 ecmd
->duplex
= DUPLEX_FULL
;
948 ethtool_cmd_speed_set(ecmd
, -1);
952 if (db
->media_mode
& ULI526X_AUTO
)
954 ecmd
->autoneg
= AUTONEG_ENABLE
;
958 static void netdev_get_drvinfo(struct net_device
*dev
,
959 struct ethtool_drvinfo
*info
)
961 struct uli526x_board_info
*np
= netdev_priv(dev
);
963 strcpy(info
->driver
, DRV_NAME
);
964 strcpy(info
->version
, DRV_VERSION
);
966 strcpy(info
->bus_info
, pci_name(np
->pdev
));
968 sprintf(info
->bus_info
, "EISA 0x%lx %d",
969 dev
->base_addr
, dev
->irq
);
972 static int netdev_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
) {
973 struct uli526x_board_info
*np
= netdev_priv(dev
);
975 ULi_ethtool_gset(np
, cmd
);
980 static u32
netdev_get_link(struct net_device
*dev
) {
981 struct uli526x_board_info
*np
= netdev_priv(dev
);
989 static void uli526x_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
991 wol
->supported
= WAKE_PHY
| WAKE_MAGIC
;
995 static const struct ethtool_ops netdev_ethtool_ops
= {
996 .get_drvinfo
= netdev_get_drvinfo
,
997 .get_settings
= netdev_get_settings
,
998 .get_link
= netdev_get_link
,
999 .get_wol
= uli526x_get_wol
,
1003 * A periodic timer routine
1004 * Dynamic media sense, allocate Rx buffer...
1007 static void uli526x_timer(unsigned long data
)
1010 unsigned char tmp_cr12
=0;
1011 struct net_device
*dev
= (struct net_device
*) data
;
1012 struct uli526x_board_info
*db
= netdev_priv(dev
);
1013 unsigned long flags
;
1015 //ULI526X_DBUG(0, "uli526x_timer()", 0);
1016 spin_lock_irqsave(&db
->lock
, flags
);
1019 /* Dynamic reset ULI526X : system error or transmit time-out */
1020 tmp_cr8
= inl(db
->ioaddr
+ DCR8
);
1021 if ( (db
->interval_rx_cnt
==0) && (tmp_cr8
) ) {
1025 db
->interval_rx_cnt
= 0;
1027 /* TX polling kick monitor */
1028 if ( db
->tx_packet_cnt
&&
1029 time_after(jiffies
, dev_trans_start(dev
) + ULI526X_TX_KICK
) ) {
1030 outl(0x1, dev
->base_addr
+ DCR1
); // Tx polling again
1033 if ( time_after(jiffies
, dev_trans_start(dev
) + ULI526X_TX_TIMEOUT
) ) {
1034 db
->reset_TXtimeout
++;
1036 netdev_err(dev
, " Tx timeout - resetting\n");
1040 if (db
->wait_reset
) {
1041 ULI526X_DBUG(0, "Dynamic Reset device", db
->tx_packet_cnt
);
1043 uli526x_dynamic_reset(dev
);
1044 db
->timer
.expires
= ULI526X_TIMER_WUT
;
1045 add_timer(&db
->timer
);
1046 spin_unlock_irqrestore(&db
->lock
, flags
);
1050 /* Link status check, Dynamic media type change */
1051 if((phy_read(db
->ioaddr
, db
->phy_addr
, 5, db
->chip_id
) & 0x01e0)!=0)
1054 if ( !(tmp_cr12
& 0x3) && !db
->link_failed
) {
1056 ULI526X_DBUG(0, "Link Failed", tmp_cr12
);
1057 netif_carrier_off(dev
);
1058 netdev_info(dev
, "NIC Link is Down\n");
1059 db
->link_failed
= 1;
1061 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1062 /* AUTO don't need */
1063 if ( !(db
->media_mode
& 0x8) )
1064 phy_write(db
->ioaddr
, db
->phy_addr
, 0, 0x1000, db
->chip_id
);
1066 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1067 if (db
->media_mode
& ULI526X_AUTO
) {
1068 db
->cr6_data
&=~0x00000200; /* bit9=0, HD mode */
1069 update_cr6(db
->cr6_data
, db
->ioaddr
);
1072 if ((tmp_cr12
& 0x3) && db
->link_failed
) {
1073 ULI526X_DBUG(0, "Link link OK", tmp_cr12
);
1074 db
->link_failed
= 0;
1076 /* Auto Sense Speed */
1077 if ( (db
->media_mode
& ULI526X_AUTO
) &&
1078 uli526x_sense_speed(db
) )
1079 db
->link_failed
= 1;
1080 uli526x_process_mode(db
);
1082 if(db
->link_failed
==0)
1084 netdev_info(dev
, "NIC Link is Up %d Mbps %s duplex\n",
1085 (db
->op_mode
== ULI526X_100MHF
||
1086 db
->op_mode
== ULI526X_100MFD
)
1088 (db
->op_mode
== ULI526X_10MFD
||
1089 db
->op_mode
== ULI526X_100MFD
)
1091 netif_carrier_on(dev
);
1093 /* SHOW_MEDIA_TYPE(db->op_mode); */
1095 else if(!(tmp_cr12
& 0x3) && db
->link_failed
)
1099 netdev_info(dev
, "NIC Link is Down\n");
1100 netif_carrier_off(dev
);
1105 /* Timer active again */
1106 db
->timer
.expires
= ULI526X_TIMER_WUT
;
1107 add_timer(&db
->timer
);
1108 spin_unlock_irqrestore(&db
->lock
, flags
);
1113 * Stop ULI526X board
1114 * Free Tx/Rx allocated memory
1115 * Init system variable
1118 static void uli526x_reset_prepare(struct net_device
*dev
)
1120 struct uli526x_board_info
*db
= netdev_priv(dev
);
1122 /* Sopt MAC controller */
1123 db
->cr6_data
&= ~(CR6_RXSC
| CR6_TXSC
); /* Disable Tx/Rx */
1124 update_cr6(db
->cr6_data
, dev
->base_addr
);
1125 outl(0, dev
->base_addr
+ DCR7
); /* Disable Interrupt */
1126 outl(inl(dev
->base_addr
+ DCR5
), dev
->base_addr
+ DCR5
);
1128 /* Disable upper layer interface */
1129 netif_stop_queue(dev
);
1131 /* Free Rx Allocate buffer */
1132 uli526x_free_rxbuffer(db
);
1134 /* system variable init */
1135 db
->tx_packet_cnt
= 0;
1136 db
->rx_avail_cnt
= 0;
1137 db
->link_failed
= 1;
1144 * Dynamic reset the ULI526X board
1145 * Stop ULI526X board
1146 * Free Tx/Rx allocated memory
1147 * Reset ULI526X board
1148 * Re-initialize ULI526X board
1151 static void uli526x_dynamic_reset(struct net_device
*dev
)
1153 ULI526X_DBUG(0, "uli526x_dynamic_reset()", 0);
1155 uli526x_reset_prepare(dev
);
1157 /* Re-initialize ULI526X board */
1160 /* Restart upper layer interface */
1161 netif_wake_queue(dev
);
1168 * Suspend the interface.
1171 static int uli526x_suspend(struct pci_dev
*pdev
, pm_message_t state
)
1173 struct net_device
*dev
= pci_get_drvdata(pdev
);
1174 pci_power_t power_state
;
1177 ULI526X_DBUG(0, "uli526x_suspend", 0);
1179 if (!netdev_priv(dev
))
1182 pci_save_state(pdev
);
1184 if (!netif_running(dev
))
1187 netif_device_detach(dev
);
1188 uli526x_reset_prepare(dev
);
1190 power_state
= pci_choose_state(pdev
, state
);
1191 pci_enable_wake(pdev
, power_state
, 0);
1192 err
= pci_set_power_state(pdev
, power_state
);
1194 netif_device_attach(dev
);
1195 /* Re-initialize ULI526X board */
1197 /* Restart upper layer interface */
1198 netif_wake_queue(dev
);
1205 * Resume the interface.
1208 static int uli526x_resume(struct pci_dev
*pdev
)
1210 struct net_device
*dev
= pci_get_drvdata(pdev
);
1213 ULI526X_DBUG(0, "uli526x_resume", 0);
1215 if (!netdev_priv(dev
))
1218 pci_restore_state(pdev
);
1220 if (!netif_running(dev
))
1223 err
= pci_set_power_state(pdev
, PCI_D0
);
1225 netdev_warn(dev
, "Could not put device into D0\n");
1229 netif_device_attach(dev
);
1230 /* Re-initialize ULI526X board */
1232 /* Restart upper layer interface */
1233 netif_wake_queue(dev
);
1238 #else /* !CONFIG_PM */
1240 #define uli526x_suspend NULL
1241 #define uli526x_resume NULL
1243 #endif /* !CONFIG_PM */
1247 * free all allocated rx buffer
1250 static void uli526x_free_rxbuffer(struct uli526x_board_info
* db
)
1252 ULI526X_DBUG(0, "uli526x_free_rxbuffer()", 0);
1254 /* free allocated rx buffer */
1255 while (db
->rx_avail_cnt
) {
1256 dev_kfree_skb(db
->rx_ready_ptr
->rx_skb_ptr
);
1257 db
->rx_ready_ptr
= db
->rx_ready_ptr
->next_rx_desc
;
1264 * Reuse the SK buffer
1267 static void uli526x_reuse_skb(struct uli526x_board_info
*db
, struct sk_buff
* skb
)
1269 struct rx_desc
*rxptr
= db
->rx_insert_ptr
;
1271 if (!(rxptr
->rdes0
& cpu_to_le32(0x80000000))) {
1272 rxptr
->rx_skb_ptr
= skb
;
1273 rxptr
->rdes2
= cpu_to_le32(pci_map_single(db
->pdev
,
1274 skb_tail_pointer(skb
),
1276 PCI_DMA_FROMDEVICE
));
1278 rxptr
->rdes0
= cpu_to_le32(0x80000000);
1280 db
->rx_insert_ptr
= rxptr
->next_rx_desc
;
1282 ULI526X_DBUG(0, "SK Buffer reuse method error", db
->rx_avail_cnt
);
1287 * Initialize transmit/Receive descriptor
1288 * Using Chain structure, and allocate Tx/Rx buffer
1291 static void uli526x_descriptor_init(struct uli526x_board_info
*db
, unsigned long ioaddr
)
1293 struct tx_desc
*tmp_tx
;
1294 struct rx_desc
*tmp_rx
;
1295 unsigned char *tmp_buf
;
1296 dma_addr_t tmp_tx_dma
, tmp_rx_dma
;
1297 dma_addr_t tmp_buf_dma
;
1300 ULI526X_DBUG(0, "uli526x_descriptor_init()", 0);
1302 /* tx descriptor start pointer */
1303 db
->tx_insert_ptr
= db
->first_tx_desc
;
1304 db
->tx_remove_ptr
= db
->first_tx_desc
;
1305 outl(db
->first_tx_desc_dma
, ioaddr
+ DCR4
); /* TX DESC address */
1307 /* rx descriptor start pointer */
1308 db
->first_rx_desc
= (void *)db
->first_tx_desc
+ sizeof(struct tx_desc
) * TX_DESC_CNT
;
1309 db
->first_rx_desc_dma
= db
->first_tx_desc_dma
+ sizeof(struct tx_desc
) * TX_DESC_CNT
;
1310 db
->rx_insert_ptr
= db
->first_rx_desc
;
1311 db
->rx_ready_ptr
= db
->first_rx_desc
;
1312 outl(db
->first_rx_desc_dma
, ioaddr
+ DCR3
); /* RX DESC address */
1314 /* Init Transmit chain */
1315 tmp_buf
= db
->buf_pool_start
;
1316 tmp_buf_dma
= db
->buf_pool_dma_start
;
1317 tmp_tx_dma
= db
->first_tx_desc_dma
;
1318 for (tmp_tx
= db
->first_tx_desc
, i
= 0; i
< TX_DESC_CNT
; i
++, tmp_tx
++) {
1319 tmp_tx
->tx_buf_ptr
= tmp_buf
;
1320 tmp_tx
->tdes0
= cpu_to_le32(0);
1321 tmp_tx
->tdes1
= cpu_to_le32(0x81000000); /* IC, chain */
1322 tmp_tx
->tdes2
= cpu_to_le32(tmp_buf_dma
);
1323 tmp_tx_dma
+= sizeof(struct tx_desc
);
1324 tmp_tx
->tdes3
= cpu_to_le32(tmp_tx_dma
);
1325 tmp_tx
->next_tx_desc
= tmp_tx
+ 1;
1326 tmp_buf
= tmp_buf
+ TX_BUF_ALLOC
;
1327 tmp_buf_dma
= tmp_buf_dma
+ TX_BUF_ALLOC
;
1329 (--tmp_tx
)->tdes3
= cpu_to_le32(db
->first_tx_desc_dma
);
1330 tmp_tx
->next_tx_desc
= db
->first_tx_desc
;
1332 /* Init Receive descriptor chain */
1333 tmp_rx_dma
=db
->first_rx_desc_dma
;
1334 for (tmp_rx
= db
->first_rx_desc
, i
= 0; i
< RX_DESC_CNT
; i
++, tmp_rx
++) {
1335 tmp_rx
->rdes0
= cpu_to_le32(0);
1336 tmp_rx
->rdes1
= cpu_to_le32(0x01000600);
1337 tmp_rx_dma
+= sizeof(struct rx_desc
);
1338 tmp_rx
->rdes3
= cpu_to_le32(tmp_rx_dma
);
1339 tmp_rx
->next_rx_desc
= tmp_rx
+ 1;
1341 (--tmp_rx
)->rdes3
= cpu_to_le32(db
->first_rx_desc_dma
);
1342 tmp_rx
->next_rx_desc
= db
->first_rx_desc
;
1344 /* pre-allocate Rx buffer */
1345 allocate_rx_buffer(db
);
1351 * Firstly stop ULI526X, then written value and start
1354 static void update_cr6(u32 cr6_data
, unsigned long ioaddr
)
1357 outl(cr6_data
, ioaddr
+ DCR6
);
1363 * Send a setup frame for M5261/M5263
1364 * This setup frame initialize ULI526X address filter mode
1368 #define FLT_SHIFT 16
1373 static void send_filter_frame(struct net_device
*dev
, int mc_cnt
)
1375 struct uli526x_board_info
*db
= netdev_priv(dev
);
1376 struct netdev_hw_addr
*ha
;
1377 struct tx_desc
*txptr
;
1382 ULI526X_DBUG(0, "send_filter_frame()", 0);
1384 txptr
= db
->tx_insert_ptr
;
1385 suptr
= (u32
*) txptr
->tx_buf_ptr
;
1388 addrptr
= (u16
*) dev
->dev_addr
;
1389 *suptr
++ = addrptr
[0] << FLT_SHIFT
;
1390 *suptr
++ = addrptr
[1] << FLT_SHIFT
;
1391 *suptr
++ = addrptr
[2] << FLT_SHIFT
;
1393 /* broadcast address */
1394 *suptr
++ = 0xffff << FLT_SHIFT
;
1395 *suptr
++ = 0xffff << FLT_SHIFT
;
1396 *suptr
++ = 0xffff << FLT_SHIFT
;
1398 /* fit the multicast address */
1399 netdev_for_each_mc_addr(ha
, dev
) {
1400 addrptr
= (u16
*) ha
->addr
;
1401 *suptr
++ = addrptr
[0] << FLT_SHIFT
;
1402 *suptr
++ = addrptr
[1] << FLT_SHIFT
;
1403 *suptr
++ = addrptr
[2] << FLT_SHIFT
;
1406 for (i
= netdev_mc_count(dev
); i
< 14; i
++) {
1407 *suptr
++ = 0xffff << FLT_SHIFT
;
1408 *suptr
++ = 0xffff << FLT_SHIFT
;
1409 *suptr
++ = 0xffff << FLT_SHIFT
;
1412 /* prepare the setup frame */
1413 db
->tx_insert_ptr
= txptr
->next_tx_desc
;
1414 txptr
->tdes1
= cpu_to_le32(0x890000c0);
1416 /* Resource Check and Send the setup packet */
1417 if (db
->tx_packet_cnt
< TX_DESC_CNT
) {
1418 /* Resource Empty */
1419 db
->tx_packet_cnt
++;
1420 txptr
->tdes0
= cpu_to_le32(0x80000000);
1421 update_cr6(db
->cr6_data
| 0x2000, dev
->base_addr
);
1422 outl(0x1, dev
->base_addr
+ DCR1
); /* Issue Tx polling */
1423 update_cr6(db
->cr6_data
, dev
->base_addr
);
1424 dev
->trans_start
= jiffies
;
1426 netdev_err(dev
, "No Tx resource - Send_filter_frame!\n");
1431 * Allocate rx buffer,
1432 * As possible as allocate maxiumn Rx buffer
1435 static void allocate_rx_buffer(struct uli526x_board_info
*db
)
1437 struct rx_desc
*rxptr
;
1438 struct sk_buff
*skb
;
1440 rxptr
= db
->rx_insert_ptr
;
1442 while(db
->rx_avail_cnt
< RX_DESC_CNT
) {
1443 if ( ( skb
= dev_alloc_skb(RX_ALLOC_SIZE
) ) == NULL
)
1445 rxptr
->rx_skb_ptr
= skb
; /* FIXME (?) */
1446 rxptr
->rdes2
= cpu_to_le32(pci_map_single(db
->pdev
,
1447 skb_tail_pointer(skb
),
1449 PCI_DMA_FROMDEVICE
));
1451 rxptr
->rdes0
= cpu_to_le32(0x80000000);
1452 rxptr
= rxptr
->next_rx_desc
;
1456 db
->rx_insert_ptr
= rxptr
;
1461 * Read one word data from the serial ROM
1464 static u16
read_srom_word(long ioaddr
, int offset
)
1468 long cr9_ioaddr
= ioaddr
+ DCR9
;
1470 outl(CR9_SROM_READ
, cr9_ioaddr
);
1471 outl(CR9_SROM_READ
| CR9_SRCS
, cr9_ioaddr
);
1473 /* Send the Read Command 110b */
1474 SROM_CLK_WRITE(SROM_DATA_1
, cr9_ioaddr
);
1475 SROM_CLK_WRITE(SROM_DATA_1
, cr9_ioaddr
);
1476 SROM_CLK_WRITE(SROM_DATA_0
, cr9_ioaddr
);
1478 /* Send the offset */
1479 for (i
= 5; i
>= 0; i
--) {
1480 srom_data
= (offset
& (1 << i
)) ? SROM_DATA_1
: SROM_DATA_0
;
1481 SROM_CLK_WRITE(srom_data
, cr9_ioaddr
);
1484 outl(CR9_SROM_READ
| CR9_SRCS
, cr9_ioaddr
);
1486 for (i
= 16; i
> 0; i
--) {
1487 outl(CR9_SROM_READ
| CR9_SRCS
| CR9_SRCLK
, cr9_ioaddr
);
1489 srom_data
= (srom_data
<< 1) | ((inl(cr9_ioaddr
) & CR9_CRDOUT
) ? 1 : 0);
1490 outl(CR9_SROM_READ
| CR9_SRCS
, cr9_ioaddr
);
1494 outl(CR9_SROM_READ
, cr9_ioaddr
);
1500 * Auto sense the media mode
1503 static u8
uli526x_sense_speed(struct uli526x_board_info
* db
)
1508 phy_mode
= phy_read(db
->ioaddr
, db
->phy_addr
, 1, db
->chip_id
);
1509 phy_mode
= phy_read(db
->ioaddr
, db
->phy_addr
, 1, db
->chip_id
);
1511 if ( (phy_mode
& 0x24) == 0x24 ) {
1513 phy_mode
= ((phy_read(db
->ioaddr
, db
->phy_addr
, 5, db
->chip_id
) & 0x01e0)<<7);
1516 else if(phy_mode
&0x4000)
1518 else if(phy_mode
&0x2000)
1524 case 0x1000: db
->op_mode
= ULI526X_10MHF
; break;
1525 case 0x2000: db
->op_mode
= ULI526X_10MFD
; break;
1526 case 0x4000: db
->op_mode
= ULI526X_100MHF
; break;
1527 case 0x8000: db
->op_mode
= ULI526X_100MFD
; break;
1528 default: db
->op_mode
= ULI526X_10MHF
; ErrFlag
= 1; break;
1531 db
->op_mode
= ULI526X_10MHF
;
1532 ULI526X_DBUG(0, "Link Failed :", phy_mode
);
1541 * Set 10/100 phyxcer capability
1542 * AUTO mode : phyxcer register4 is NIC capability
1543 * Force mode: phyxcer register4 is the force media
1546 static void uli526x_set_phyxcer(struct uli526x_board_info
*db
)
1550 /* Phyxcer capability setting */
1551 phy_reg
= phy_read(db
->ioaddr
, db
->phy_addr
, 4, db
->chip_id
) & ~0x01e0;
1553 if (db
->media_mode
& ULI526X_AUTO
) {
1555 phy_reg
|= db
->PHY_reg4
;
1558 switch(db
->media_mode
) {
1559 case ULI526X_10MHF
: phy_reg
|= 0x20; break;
1560 case ULI526X_10MFD
: phy_reg
|= 0x40; break;
1561 case ULI526X_100MHF
: phy_reg
|= 0x80; break;
1562 case ULI526X_100MFD
: phy_reg
|= 0x100; break;
1567 /* Write new capability to Phyxcer Reg4 */
1568 if ( !(phy_reg
& 0x01e0)) {
1569 phy_reg
|=db
->PHY_reg4
;
1570 db
->media_mode
|=ULI526X_AUTO
;
1572 phy_write(db
->ioaddr
, db
->phy_addr
, 4, phy_reg
, db
->chip_id
);
1574 /* Restart Auto-Negotiation */
1575 phy_write(db
->ioaddr
, db
->phy_addr
, 0, 0x1200, db
->chip_id
);
1582 AUTO mode : PHY controller in Auto-negotiation Mode
1583 * Force mode: PHY controller in force mode with HUB
1584 * N-way force capability with SWITCH
1587 static void uli526x_process_mode(struct uli526x_board_info
*db
)
1591 /* Full Duplex Mode Check */
1592 if (db
->op_mode
& 0x4)
1593 db
->cr6_data
|= CR6_FDM
; /* Set Full Duplex Bit */
1595 db
->cr6_data
&= ~CR6_FDM
; /* Clear Full Duplex Bit */
1597 update_cr6(db
->cr6_data
, db
->ioaddr
);
1599 /* 10/100M phyxcer force mode need */
1600 if ( !(db
->media_mode
& 0x8)) {
1602 phy_reg
= phy_read(db
->ioaddr
, db
->phy_addr
, 6, db
->chip_id
);
1603 if ( !(phy_reg
& 0x1) ) {
1604 /* parter without N-Way capability */
1606 switch(db
->op_mode
) {
1607 case ULI526X_10MHF
: phy_reg
= 0x0; break;
1608 case ULI526X_10MFD
: phy_reg
= 0x100; break;
1609 case ULI526X_100MHF
: phy_reg
= 0x2000; break;
1610 case ULI526X_100MFD
: phy_reg
= 0x2100; break;
1612 phy_write(db
->ioaddr
, db
->phy_addr
, 0, phy_reg
, db
->chip_id
);
1619 * Write a word to Phy register
1622 static void phy_write(unsigned long iobase
, u8 phy_addr
, u8 offset
, u16 phy_data
, u32 chip_id
)
1625 unsigned long ioaddr
;
1627 if(chip_id
== PCI_ULI5263_ID
)
1629 phy_writeby_cr10(iobase
, phy_addr
, offset
, phy_data
);
1632 /* M5261/M5263 Chip */
1633 ioaddr
= iobase
+ DCR9
;
1635 /* Send 33 synchronization clock to Phy controller */
1636 for (i
= 0; i
< 35; i
++)
1637 phy_write_1bit(ioaddr
, PHY_DATA_1
, chip_id
);
1639 /* Send start command(01) to Phy */
1640 phy_write_1bit(ioaddr
, PHY_DATA_0
, chip_id
);
1641 phy_write_1bit(ioaddr
, PHY_DATA_1
, chip_id
);
1643 /* Send write command(01) to Phy */
1644 phy_write_1bit(ioaddr
, PHY_DATA_0
, chip_id
);
1645 phy_write_1bit(ioaddr
, PHY_DATA_1
, chip_id
);
1647 /* Send Phy address */
1648 for (i
= 0x10; i
> 0; i
= i
>> 1)
1649 phy_write_1bit(ioaddr
, phy_addr
& i
? PHY_DATA_1
: PHY_DATA_0
, chip_id
);
1651 /* Send register address */
1652 for (i
= 0x10; i
> 0; i
= i
>> 1)
1653 phy_write_1bit(ioaddr
, offset
& i
? PHY_DATA_1
: PHY_DATA_0
, chip_id
);
1655 /* written trasnition */
1656 phy_write_1bit(ioaddr
, PHY_DATA_1
, chip_id
);
1657 phy_write_1bit(ioaddr
, PHY_DATA_0
, chip_id
);
1659 /* Write a word data to PHY controller */
1660 for ( i
= 0x8000; i
> 0; i
>>= 1)
1661 phy_write_1bit(ioaddr
, phy_data
& i
? PHY_DATA_1
: PHY_DATA_0
, chip_id
);
1667 * Read a word data from phy register
1670 static u16
phy_read(unsigned long iobase
, u8 phy_addr
, u8 offset
, u32 chip_id
)
1674 unsigned long ioaddr
;
1676 if(chip_id
== PCI_ULI5263_ID
)
1677 return phy_readby_cr10(iobase
, phy_addr
, offset
);
1678 /* M5261/M5263 Chip */
1679 ioaddr
= iobase
+ DCR9
;
1681 /* Send 33 synchronization clock to Phy controller */
1682 for (i
= 0; i
< 35; i
++)
1683 phy_write_1bit(ioaddr
, PHY_DATA_1
, chip_id
);
1685 /* Send start command(01) to Phy */
1686 phy_write_1bit(ioaddr
, PHY_DATA_0
, chip_id
);
1687 phy_write_1bit(ioaddr
, PHY_DATA_1
, chip_id
);
1689 /* Send read command(10) to Phy */
1690 phy_write_1bit(ioaddr
, PHY_DATA_1
, chip_id
);
1691 phy_write_1bit(ioaddr
, PHY_DATA_0
, chip_id
);
1693 /* Send Phy address */
1694 for (i
= 0x10; i
> 0; i
= i
>> 1)
1695 phy_write_1bit(ioaddr
, phy_addr
& i
? PHY_DATA_1
: PHY_DATA_0
, chip_id
);
1697 /* Send register address */
1698 for (i
= 0x10; i
> 0; i
= i
>> 1)
1699 phy_write_1bit(ioaddr
, offset
& i
? PHY_DATA_1
: PHY_DATA_0
, chip_id
);
1701 /* Skip transition state */
1702 phy_read_1bit(ioaddr
, chip_id
);
1704 /* read 16bit data */
1705 for (phy_data
= 0, i
= 0; i
< 16; i
++) {
1707 phy_data
|= phy_read_1bit(ioaddr
, chip_id
);
1713 static u16
phy_readby_cr10(unsigned long iobase
, u8 phy_addr
, u8 offset
)
1715 unsigned long ioaddr
,cr10_value
;
1717 ioaddr
= iobase
+ DCR10
;
1718 cr10_value
= phy_addr
;
1719 cr10_value
= (cr10_value
<<5) + offset
;
1720 cr10_value
= (cr10_value
<<16) + 0x08000000;
1721 outl(cr10_value
,ioaddr
);
1725 cr10_value
= inl(ioaddr
);
1726 if(cr10_value
&0x10000000)
1729 return cr10_value
& 0x0ffff;
1732 static void phy_writeby_cr10(unsigned long iobase
, u8 phy_addr
, u8 offset
, u16 phy_data
)
1734 unsigned long ioaddr
,cr10_value
;
1736 ioaddr
= iobase
+ DCR10
;
1737 cr10_value
= phy_addr
;
1738 cr10_value
= (cr10_value
<<5) + offset
;
1739 cr10_value
= (cr10_value
<<16) + 0x04000000 + phy_data
;
1740 outl(cr10_value
,ioaddr
);
1744 * Write one bit data to Phy Controller
1747 static void phy_write_1bit(unsigned long ioaddr
, u32 phy_data
, u32 chip_id
)
1749 outl(phy_data
, ioaddr
); /* MII Clock Low */
1751 outl(phy_data
| MDCLKH
, ioaddr
); /* MII Clock High */
1753 outl(phy_data
, ioaddr
); /* MII Clock Low */
1759 * Read one bit phy data from PHY controller
1762 static u16
phy_read_1bit(unsigned long ioaddr
, u32 chip_id
)
1766 outl(0x50000 , ioaddr
);
1768 phy_data
= ( inl(ioaddr
) >> 19 ) & 0x1;
1769 outl(0x40000 , ioaddr
);
1776 static DEFINE_PCI_DEVICE_TABLE(uli526x_pci_tbl
) = {
1777 { 0x10B9, 0x5261, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, PCI_ULI5261_ID
},
1778 { 0x10B9, 0x5263, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, PCI_ULI5263_ID
},
1781 MODULE_DEVICE_TABLE(pci
, uli526x_pci_tbl
);
1784 static struct pci_driver uli526x_driver
= {
1786 .id_table
= uli526x_pci_tbl
,
1787 .probe
= uli526x_init_one
,
1788 .remove
= __devexit_p(uli526x_remove_one
),
1789 .suspend
= uli526x_suspend
,
1790 .resume
= uli526x_resume
,
1793 MODULE_AUTHOR("Peer Chen, peer.chen@uli.com.tw");
1794 MODULE_DESCRIPTION("ULi M5261/M5263 fast ethernet driver");
1795 MODULE_LICENSE("GPL");
1797 module_param(debug
, int, 0644);
1798 module_param(mode
, int, 0);
1799 module_param(cr6set
, int, 0);
1800 MODULE_PARM_DESC(debug
, "ULi M5261/M5263 enable debugging (0-1)");
1801 MODULE_PARM_DESC(mode
, "ULi M5261/M5263: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
1804 * when user used insmod to add module, system invoked init_module()
1805 * to register the services.
1808 static int __init
uli526x_init_module(void)
1811 pr_info("%s\n", version
);
1812 printed_version
= 1;
1814 ULI526X_DBUG(0, "init_module() ", debug
);
1817 uli526x_debug
= debug
; /* set debug flag */
1819 uli526x_cr6_user_set
= cr6set
;
1823 case ULI526X_100MHF
:
1825 case ULI526X_100MFD
:
1826 uli526x_media_mode
= mode
;
1829 uli526x_media_mode
= ULI526X_AUTO
;
1833 return pci_register_driver(&uli526x_driver
);
1839 * when user used rmmod to delete module, system invoked clean_module()
1840 * to un-register all registered services.
1843 static void __exit
uli526x_cleanup_module(void)
1845 ULI526X_DBUG(0, "uli526x_clean_module() ", debug
);
1846 pci_unregister_driver(&uli526x_driver
);
1849 module_init(uli526x_init_module
);
1850 module_exit(uli526x_cleanup_module
);