Add linux-next specific files for 20110831
[linux-2.6/next.git] / drivers / net / ethernet / intel / e1000e / 80003es2lan.c
blobb7544336cef43f597905a73fee581cc103d6886f
1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * 80003ES2LAN Gigabit Ethernet Controller (Copper)
31 * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
34 #include "e1000.h"
36 #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00
37 #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02
38 #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10
39 #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F
41 #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008
42 #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800
43 #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010
45 #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
46 #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000
47 #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000
49 #define E1000_KMRNCTRLSTA_OPMODE_MASK 0x000C
50 #define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO 0x0004
52 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
53 #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000
55 #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8
56 #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9
58 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
59 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Disab. */
60 #define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
61 #define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */
62 #define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */
63 #define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */
65 /* PHY Specific Control Register 2 (Page 0, Register 26) */
66 #define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000
67 /* 1=Reverse Auto-Negotiation */
69 /* MAC Specific Control Register (Page 2, Register 21) */
70 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
71 #define GG82563_MSCR_TX_CLK_MASK 0x0007
72 #define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004
73 #define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005
74 #define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007
76 #define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */
78 /* DSP Distance Register (Page 5, Register 26) */
79 #define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M
80 1 = 50-80M
81 2 = 80-110M
82 3 = 110-140M
83 4 = >140M */
85 /* Kumeran Mode Control Register (Page 193, Register 16) */
86 #define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
88 /* Max number of times Kumeran read/write should be validated */
89 #define GG82563_MAX_KMRN_RETRY 0x5
91 /* Power Management Control Register (Page 193, Register 20) */
92 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001
93 /* 1=Enable SERDES Electrical Idle */
95 /* In-Band Control Register (Page 194, Register 18) */
96 #define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */
99 * A table for the GG82563 cable length where the range is defined
100 * with a lower bound at "index" and the upper bound at
101 * "index + 5".
103 static const u16 e1000_gg82563_cable_length_table[] = {
104 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
105 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
106 ARRAY_SIZE(e1000_gg82563_cable_length_table)
108 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
109 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
110 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
111 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
112 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
113 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
114 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
115 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
116 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
117 u16 *data);
118 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
119 u16 data);
120 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
123 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
124 * @hw: pointer to the HW structure
126 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
128 struct e1000_phy_info *phy = &hw->phy;
129 s32 ret_val;
131 if (hw->phy.media_type != e1000_media_type_copper) {
132 phy->type = e1000_phy_none;
133 return 0;
134 } else {
135 phy->ops.power_up = e1000_power_up_phy_copper;
136 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
139 phy->addr = 1;
140 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
141 phy->reset_delay_us = 100;
142 phy->type = e1000_phy_gg82563;
144 /* This can only be done after all function pointers are setup. */
145 ret_val = e1000e_get_phy_id(hw);
147 /* Verify phy id */
148 if (phy->id != GG82563_E_PHY_ID)
149 return -E1000_ERR_PHY;
151 return ret_val;
155 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
156 * @hw: pointer to the HW structure
158 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
160 struct e1000_nvm_info *nvm = &hw->nvm;
161 u32 eecd = er32(EECD);
162 u16 size;
164 nvm->opcode_bits = 8;
165 nvm->delay_usec = 1;
166 switch (nvm->override) {
167 case e1000_nvm_override_spi_large:
168 nvm->page_size = 32;
169 nvm->address_bits = 16;
170 break;
171 case e1000_nvm_override_spi_small:
172 nvm->page_size = 8;
173 nvm->address_bits = 8;
174 break;
175 default:
176 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
177 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
178 break;
181 nvm->type = e1000_nvm_eeprom_spi;
183 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
184 E1000_EECD_SIZE_EX_SHIFT);
187 * Added to a constant, "size" becomes the left-shift value
188 * for setting word_size.
190 size += NVM_WORD_SIZE_BASE_SHIFT;
192 /* EEPROM access above 16k is unsupported */
193 if (size > 14)
194 size = 14;
195 nvm->word_size = 1 << size;
197 return 0;
201 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
202 * @hw: pointer to the HW structure
204 static s32 e1000_init_mac_params_80003es2lan(struct e1000_adapter *adapter)
206 struct e1000_hw *hw = &adapter->hw;
207 struct e1000_mac_info *mac = &hw->mac;
208 struct e1000_mac_operations *func = &mac->ops;
210 /* Set media type */
211 switch (adapter->pdev->device) {
212 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
213 hw->phy.media_type = e1000_media_type_internal_serdes;
214 break;
215 default:
216 hw->phy.media_type = e1000_media_type_copper;
217 break;
220 /* Set mta register count */
221 mac->mta_reg_count = 128;
222 /* Set rar entry count */
223 mac->rar_entry_count = E1000_RAR_ENTRIES;
224 /* FWSM register */
225 mac->has_fwsm = true;
226 /* ARC supported; valid only if manageability features are enabled. */
227 mac->arc_subsystem_valid =
228 (er32(FWSM) & E1000_FWSM_MODE_MASK)
229 ? true : false;
230 /* Adaptive IFS not supported */
231 mac->adaptive_ifs = false;
233 /* check for link */
234 switch (hw->phy.media_type) {
235 case e1000_media_type_copper:
236 func->setup_physical_interface = e1000_setup_copper_link_80003es2lan;
237 func->check_for_link = e1000e_check_for_copper_link;
238 break;
239 case e1000_media_type_fiber:
240 func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
241 func->check_for_link = e1000e_check_for_fiber_link;
242 break;
243 case e1000_media_type_internal_serdes:
244 func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
245 func->check_for_link = e1000e_check_for_serdes_link;
246 break;
247 default:
248 return -E1000_ERR_CONFIG;
249 break;
252 /* set lan id for port to determine which phy lock to use */
253 hw->mac.ops.set_lan_id(hw);
255 return 0;
258 static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)
260 struct e1000_hw *hw = &adapter->hw;
261 s32 rc;
263 rc = e1000_init_mac_params_80003es2lan(adapter);
264 if (rc)
265 return rc;
267 rc = e1000_init_nvm_params_80003es2lan(hw);
268 if (rc)
269 return rc;
271 rc = e1000_init_phy_params_80003es2lan(hw);
272 if (rc)
273 return rc;
275 return 0;
279 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
280 * @hw: pointer to the HW structure
282 * A wrapper to acquire access rights to the correct PHY.
284 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
286 u16 mask;
288 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
289 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
293 * e1000_release_phy_80003es2lan - Release rights to access PHY
294 * @hw: pointer to the HW structure
296 * A wrapper to release access rights to the correct PHY.
298 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
300 u16 mask;
302 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
303 e1000_release_swfw_sync_80003es2lan(hw, mask);
307 * e1000_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register
308 * @hw: pointer to the HW structure
310 * Acquire the semaphore to access the Kumeran interface.
313 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
315 u16 mask;
317 mask = E1000_SWFW_CSR_SM;
319 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
323 * e1000_release_mac_csr_80003es2lan - Release rights to access Kumeran Register
324 * @hw: pointer to the HW structure
326 * Release the semaphore used to access the Kumeran interface
328 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
330 u16 mask;
332 mask = E1000_SWFW_CSR_SM;
334 e1000_release_swfw_sync_80003es2lan(hw, mask);
338 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
339 * @hw: pointer to the HW structure
341 * Acquire the semaphore to access the EEPROM.
343 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
345 s32 ret_val;
347 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
348 if (ret_val)
349 return ret_val;
351 ret_val = e1000e_acquire_nvm(hw);
353 if (ret_val)
354 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
356 return ret_val;
360 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
361 * @hw: pointer to the HW structure
363 * Release the semaphore used to access the EEPROM.
365 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
367 e1000e_release_nvm(hw);
368 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
372 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
373 * @hw: pointer to the HW structure
374 * @mask: specifies which semaphore to acquire
376 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
377 * will also specify which port we're acquiring the lock for.
379 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
381 u32 swfw_sync;
382 u32 swmask = mask;
383 u32 fwmask = mask << 16;
384 s32 i = 0;
385 s32 timeout = 50;
387 while (i < timeout) {
388 if (e1000e_get_hw_semaphore(hw))
389 return -E1000_ERR_SWFW_SYNC;
391 swfw_sync = er32(SW_FW_SYNC);
392 if (!(swfw_sync & (fwmask | swmask)))
393 break;
396 * Firmware currently using resource (fwmask)
397 * or other software thread using resource (swmask)
399 e1000e_put_hw_semaphore(hw);
400 mdelay(5);
401 i++;
404 if (i == timeout) {
405 e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
406 return -E1000_ERR_SWFW_SYNC;
409 swfw_sync |= swmask;
410 ew32(SW_FW_SYNC, swfw_sync);
412 e1000e_put_hw_semaphore(hw);
414 return 0;
418 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
419 * @hw: pointer to the HW structure
420 * @mask: specifies which semaphore to acquire
422 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
423 * will also specify which port we're releasing the lock for.
425 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
427 u32 swfw_sync;
429 while (e1000e_get_hw_semaphore(hw) != 0)
430 ; /* Empty */
432 swfw_sync = er32(SW_FW_SYNC);
433 swfw_sync &= ~mask;
434 ew32(SW_FW_SYNC, swfw_sync);
436 e1000e_put_hw_semaphore(hw);
440 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
441 * @hw: pointer to the HW structure
442 * @offset: offset of the register to read
443 * @data: pointer to the data returned from the operation
445 * Read the GG82563 PHY register.
447 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
448 u32 offset, u16 *data)
450 s32 ret_val;
451 u32 page_select;
452 u16 temp;
454 ret_val = e1000_acquire_phy_80003es2lan(hw);
455 if (ret_val)
456 return ret_val;
458 /* Select Configuration Page */
459 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
460 page_select = GG82563_PHY_PAGE_SELECT;
461 } else {
463 * Use Alternative Page Select register to access
464 * registers 30 and 31
466 page_select = GG82563_PHY_PAGE_SELECT_ALT;
469 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
470 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
471 if (ret_val) {
472 e1000_release_phy_80003es2lan(hw);
473 return ret_val;
476 if (hw->dev_spec.e80003es2lan.mdic_wa_enable == true) {
478 * The "ready" bit in the MDIC register may be incorrectly set
479 * before the device has completed the "Page Select" MDI
480 * transaction. So we wait 200us after each MDI command...
482 udelay(200);
484 /* ...and verify the command was successful. */
485 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
487 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
488 ret_val = -E1000_ERR_PHY;
489 e1000_release_phy_80003es2lan(hw);
490 return ret_val;
493 udelay(200);
495 ret_val = e1000e_read_phy_reg_mdic(hw,
496 MAX_PHY_REG_ADDRESS & offset,
497 data);
499 udelay(200);
500 } else {
501 ret_val = e1000e_read_phy_reg_mdic(hw,
502 MAX_PHY_REG_ADDRESS & offset,
503 data);
506 e1000_release_phy_80003es2lan(hw);
508 return ret_val;
512 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
513 * @hw: pointer to the HW structure
514 * @offset: offset of the register to read
515 * @data: value to write to the register
517 * Write to the GG82563 PHY register.
519 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
520 u32 offset, u16 data)
522 s32 ret_val;
523 u32 page_select;
524 u16 temp;
526 ret_val = e1000_acquire_phy_80003es2lan(hw);
527 if (ret_val)
528 return ret_val;
530 /* Select Configuration Page */
531 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
532 page_select = GG82563_PHY_PAGE_SELECT;
533 } else {
535 * Use Alternative Page Select register to access
536 * registers 30 and 31
538 page_select = GG82563_PHY_PAGE_SELECT_ALT;
541 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
542 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
543 if (ret_val) {
544 e1000_release_phy_80003es2lan(hw);
545 return ret_val;
548 if (hw->dev_spec.e80003es2lan.mdic_wa_enable == true) {
550 * The "ready" bit in the MDIC register may be incorrectly set
551 * before the device has completed the "Page Select" MDI
552 * transaction. So we wait 200us after each MDI command...
554 udelay(200);
556 /* ...and verify the command was successful. */
557 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
559 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
560 e1000_release_phy_80003es2lan(hw);
561 return -E1000_ERR_PHY;
564 udelay(200);
566 ret_val = e1000e_write_phy_reg_mdic(hw,
567 MAX_PHY_REG_ADDRESS & offset,
568 data);
570 udelay(200);
571 } else {
572 ret_val = e1000e_write_phy_reg_mdic(hw,
573 MAX_PHY_REG_ADDRESS & offset,
574 data);
577 e1000_release_phy_80003es2lan(hw);
579 return ret_val;
583 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM
584 * @hw: pointer to the HW structure
585 * @offset: offset of the register to read
586 * @words: number of words to write
587 * @data: buffer of data to write to the NVM
589 * Write "words" of data to the ESB2 NVM.
591 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
592 u16 words, u16 *data)
594 return e1000e_write_nvm_spi(hw, offset, words, data);
598 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
599 * @hw: pointer to the HW structure
601 * Wait a specific amount of time for manageability processes to complete.
602 * This is a function pointer entry point called by the phy module.
604 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
606 s32 timeout = PHY_CFG_TIMEOUT;
607 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
609 if (hw->bus.func == 1)
610 mask = E1000_NVM_CFG_DONE_PORT_1;
612 while (timeout) {
613 if (er32(EEMNGCTL) & mask)
614 break;
615 usleep_range(1000, 2000);
616 timeout--;
618 if (!timeout) {
619 e_dbg("MNG configuration cycle has not completed.\n");
620 return -E1000_ERR_RESET;
623 return 0;
627 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
628 * @hw: pointer to the HW structure
630 * Force the speed and duplex settings onto the PHY. This is a
631 * function pointer entry point called by the phy module.
633 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
635 s32 ret_val;
636 u16 phy_data;
637 bool link;
640 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
641 * forced whenever speed and duplex are forced.
643 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
644 if (ret_val)
645 return ret_val;
647 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
648 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
649 if (ret_val)
650 return ret_val;
652 e_dbg("GG82563 PSCR: %X\n", phy_data);
654 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
655 if (ret_val)
656 return ret_val;
658 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
660 /* Reset the phy to commit changes. */
661 phy_data |= MII_CR_RESET;
663 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
664 if (ret_val)
665 return ret_val;
667 udelay(1);
669 if (hw->phy.autoneg_wait_to_complete) {
670 e_dbg("Waiting for forced speed/duplex link "
671 "on GG82563 phy.\n");
673 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
674 100000, &link);
675 if (ret_val)
676 return ret_val;
678 if (!link) {
680 * We didn't get link.
681 * Reset the DSP and cross our fingers.
683 ret_val = e1000e_phy_reset_dsp(hw);
684 if (ret_val)
685 return ret_val;
688 /* Try once more */
689 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
690 100000, &link);
691 if (ret_val)
692 return ret_val;
695 ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
696 if (ret_val)
697 return ret_val;
700 * Resetting the phy means we need to verify the TX_CLK corresponds
701 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz.
703 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
704 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
705 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
706 else
707 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
710 * In addition, we must re-enable CRS on Tx for both half and full
711 * duplex.
713 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
714 ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
716 return ret_val;
720 * e1000_get_cable_length_80003es2lan - Set approximate cable length
721 * @hw: pointer to the HW structure
723 * Find the approximate cable length as measured by the GG82563 PHY.
724 * This is a function pointer entry point called by the phy module.
726 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
728 struct e1000_phy_info *phy = &hw->phy;
729 s32 ret_val = 0;
730 u16 phy_data, index;
732 ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
733 if (ret_val)
734 goto out;
736 index = phy_data & GG82563_DSPD_CABLE_LENGTH;
738 if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5) {
739 ret_val = -E1000_ERR_PHY;
740 goto out;
743 phy->min_cable_length = e1000_gg82563_cable_length_table[index];
744 phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
746 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
748 out:
749 return ret_val;
753 * e1000_get_link_up_info_80003es2lan - Report speed and duplex
754 * @hw: pointer to the HW structure
755 * @speed: pointer to speed buffer
756 * @duplex: pointer to duplex buffer
758 * Retrieve the current speed and duplex configuration.
760 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
761 u16 *duplex)
763 s32 ret_val;
765 if (hw->phy.media_type == e1000_media_type_copper) {
766 ret_val = e1000e_get_speed_and_duplex_copper(hw,
767 speed,
768 duplex);
769 hw->phy.ops.cfg_on_link_up(hw);
770 } else {
771 ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
772 speed,
773 duplex);
776 return ret_val;
780 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller
781 * @hw: pointer to the HW structure
783 * Perform a global reset to the ESB2 controller.
785 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
787 u32 ctrl;
788 s32 ret_val;
791 * Prevent the PCI-E bus from sticking if there is no TLP connection
792 * on the last TLP read/write transaction when MAC is reset.
794 ret_val = e1000e_disable_pcie_master(hw);
795 if (ret_val)
796 e_dbg("PCI-E Master disable polling has failed.\n");
798 e_dbg("Masking off all interrupts\n");
799 ew32(IMC, 0xffffffff);
801 ew32(RCTL, 0);
802 ew32(TCTL, E1000_TCTL_PSP);
803 e1e_flush();
805 usleep_range(10000, 20000);
807 ctrl = er32(CTRL);
809 ret_val = e1000_acquire_phy_80003es2lan(hw);
810 e_dbg("Issuing a global reset to MAC\n");
811 ew32(CTRL, ctrl | E1000_CTRL_RST);
812 e1000_release_phy_80003es2lan(hw);
814 ret_val = e1000e_get_auto_rd_done(hw);
815 if (ret_val)
816 /* We don't want to continue accessing MAC registers. */
817 return ret_val;
819 /* Clear any pending interrupt events. */
820 ew32(IMC, 0xffffffff);
821 er32(ICR);
823 ret_val = e1000_check_alt_mac_addr_generic(hw);
825 return ret_val;
829 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller
830 * @hw: pointer to the HW structure
832 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
834 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
836 struct e1000_mac_info *mac = &hw->mac;
837 u32 reg_data;
838 s32 ret_val;
839 u16 kum_reg_data;
840 u16 i;
842 e1000_initialize_hw_bits_80003es2lan(hw);
844 /* Initialize identification LED */
845 ret_val = e1000e_id_led_init(hw);
846 if (ret_val)
847 e_dbg("Error initializing identification LED\n");
848 /* This is not fatal and we should not stop init due to this */
850 /* Disabling VLAN filtering */
851 e_dbg("Initializing the IEEE VLAN\n");
852 mac->ops.clear_vfta(hw);
854 /* Setup the receive address. */
855 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
857 /* Zero out the Multicast HASH table */
858 e_dbg("Zeroing the MTA\n");
859 for (i = 0; i < mac->mta_reg_count; i++)
860 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
862 /* Setup link and flow control */
863 ret_val = e1000e_setup_link(hw);
865 /* Disable IBIST slave mode (far-end loopback) */
866 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
867 &kum_reg_data);
868 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
869 e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
870 kum_reg_data);
872 /* Set the transmit descriptor write-back policy */
873 reg_data = er32(TXDCTL(0));
874 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
875 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
876 ew32(TXDCTL(0), reg_data);
878 /* ...for both queues. */
879 reg_data = er32(TXDCTL(1));
880 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
881 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
882 ew32(TXDCTL(1), reg_data);
884 /* Enable retransmit on late collisions */
885 reg_data = er32(TCTL);
886 reg_data |= E1000_TCTL_RTLC;
887 ew32(TCTL, reg_data);
889 /* Configure Gigabit Carry Extend Padding */
890 reg_data = er32(TCTL_EXT);
891 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
892 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
893 ew32(TCTL_EXT, reg_data);
895 /* Configure Transmit Inter-Packet Gap */
896 reg_data = er32(TIPG);
897 reg_data &= ~E1000_TIPG_IPGT_MASK;
898 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
899 ew32(TIPG, reg_data);
901 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
902 reg_data &= ~0x00100000;
903 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
905 /* default to true to enable the MDIC W/A */
906 hw->dev_spec.e80003es2lan.mdic_wa_enable = true;
908 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
909 E1000_KMRNCTRLSTA_OFFSET >>
910 E1000_KMRNCTRLSTA_OFFSET_SHIFT,
911 &i);
912 if (!ret_val) {
913 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
914 E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
915 hw->dev_spec.e80003es2lan.mdic_wa_enable = false;
919 * Clear all of the statistics registers (clear on read). It is
920 * important that we do this after we have tried to establish link
921 * because the symbol error count will increment wildly if there
922 * is no link.
924 e1000_clear_hw_cntrs_80003es2lan(hw);
926 return ret_val;
930 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
931 * @hw: pointer to the HW structure
933 * Initializes required hardware-dependent bits needed for normal operation.
935 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
937 u32 reg;
939 /* Transmit Descriptor Control 0 */
940 reg = er32(TXDCTL(0));
941 reg |= (1 << 22);
942 ew32(TXDCTL(0), reg);
944 /* Transmit Descriptor Control 1 */
945 reg = er32(TXDCTL(1));
946 reg |= (1 << 22);
947 ew32(TXDCTL(1), reg);
949 /* Transmit Arbitration Control 0 */
950 reg = er32(TARC(0));
951 reg &= ~(0xF << 27); /* 30:27 */
952 if (hw->phy.media_type != e1000_media_type_copper)
953 reg &= ~(1 << 20);
954 ew32(TARC(0), reg);
956 /* Transmit Arbitration Control 1 */
957 reg = er32(TARC(1));
958 if (er32(TCTL) & E1000_TCTL_MULR)
959 reg &= ~(1 << 28);
960 else
961 reg |= (1 << 28);
962 ew32(TARC(1), reg);
966 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
967 * @hw: pointer to the HW structure
969 * Setup some GG82563 PHY registers for obtaining link
971 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
973 struct e1000_phy_info *phy = &hw->phy;
974 s32 ret_val;
975 u32 ctrl_ext;
976 u16 data;
978 ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
979 if (ret_val)
980 return ret_val;
982 data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
983 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
984 data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
986 ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
987 if (ret_val)
988 return ret_val;
991 * Options:
992 * MDI/MDI-X = 0 (default)
993 * 0 - Auto for all speeds
994 * 1 - MDI mode
995 * 2 - MDI-X mode
996 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
998 ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
999 if (ret_val)
1000 return ret_val;
1002 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1004 switch (phy->mdix) {
1005 case 1:
1006 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1007 break;
1008 case 2:
1009 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1010 break;
1011 case 0:
1012 default:
1013 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1014 break;
1018 * Options:
1019 * disable_polarity_correction = 0 (default)
1020 * Automatic Correction for Reversed Cable Polarity
1021 * 0 - Disabled
1022 * 1 - Enabled
1024 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1025 if (phy->disable_polarity_correction)
1026 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1028 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
1029 if (ret_val)
1030 return ret_val;
1032 /* SW Reset the PHY so all changes take effect */
1033 ret_val = e1000e_commit_phy(hw);
1034 if (ret_val) {
1035 e_dbg("Error Resetting the PHY\n");
1036 return ret_val;
1039 /* Bypass Rx and Tx FIFO's */
1040 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1041 E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
1042 E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
1043 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
1044 if (ret_val)
1045 return ret_val;
1047 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1048 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1049 &data);
1050 if (ret_val)
1051 return ret_val;
1052 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
1053 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1054 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1055 data);
1056 if (ret_val)
1057 return ret_val;
1059 ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1060 if (ret_val)
1061 return ret_val;
1063 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1064 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
1065 if (ret_val)
1066 return ret_val;
1068 ctrl_ext = er32(CTRL_EXT);
1069 ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1070 ew32(CTRL_EXT, ctrl_ext);
1072 ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1073 if (ret_val)
1074 return ret_val;
1077 * Do not init these registers when the HW is in IAMT mode, since the
1078 * firmware will have already initialized them. We only initialize
1079 * them if the HW is not in IAMT mode.
1081 if (!e1000e_check_mng_mode(hw)) {
1082 /* Enable Electrical Idle on the PHY */
1083 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1084 ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
1085 if (ret_val)
1086 return ret_val;
1088 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);
1089 if (ret_val)
1090 return ret_val;
1092 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1093 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
1094 if (ret_val)
1095 return ret_val;
1099 * Workaround: Disable padding in Kumeran interface in the MAC
1100 * and in the PHY to avoid CRC errors.
1102 ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
1103 if (ret_val)
1104 return ret_val;
1106 data |= GG82563_ICR_DIS_PADDING;
1107 ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
1108 if (ret_val)
1109 return ret_val;
1111 return 0;
1115 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1116 * @hw: pointer to the HW structure
1118 * Essentially a wrapper for setting up all things "copper" related.
1119 * This is a function pointer entry point called by the mac module.
1121 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1123 u32 ctrl;
1124 s32 ret_val;
1125 u16 reg_data;
1127 ctrl = er32(CTRL);
1128 ctrl |= E1000_CTRL_SLU;
1129 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1130 ew32(CTRL, ctrl);
1133 * Set the mac to wait the maximum time between each
1134 * iteration and increase the max iterations when
1135 * polling the phy; this fixes erroneous timeouts at 10Mbps.
1137 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1138 0xFFFF);
1139 if (ret_val)
1140 return ret_val;
1141 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1142 &reg_data);
1143 if (ret_val)
1144 return ret_val;
1145 reg_data |= 0x3F;
1146 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1147 reg_data);
1148 if (ret_val)
1149 return ret_val;
1150 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1151 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1152 &reg_data);
1153 if (ret_val)
1154 return ret_val;
1155 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1156 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1157 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1158 reg_data);
1159 if (ret_val)
1160 return ret_val;
1162 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1163 if (ret_val)
1164 return ret_val;
1166 ret_val = e1000e_setup_copper_link(hw);
1168 return 0;
1172 * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1173 * @hw: pointer to the HW structure
1174 * @duplex: current duplex setting
1176 * Configure the KMRN interface by applying last minute quirks for
1177 * 10/100 operation.
1179 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1181 s32 ret_val = 0;
1182 u16 speed;
1183 u16 duplex;
1185 if (hw->phy.media_type == e1000_media_type_copper) {
1186 ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed,
1187 &duplex);
1188 if (ret_val)
1189 return ret_val;
1191 if (speed == SPEED_1000)
1192 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1193 else
1194 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1197 return ret_val;
1201 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1202 * @hw: pointer to the HW structure
1203 * @duplex: current duplex setting
1205 * Configure the KMRN interface by applying last minute quirks for
1206 * 10/100 operation.
1208 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1210 s32 ret_val;
1211 u32 tipg;
1212 u32 i = 0;
1213 u16 reg_data, reg_data2;
1215 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1216 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1217 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1218 reg_data);
1219 if (ret_val)
1220 return ret_val;
1222 /* Configure Transmit Inter-Packet Gap */
1223 tipg = er32(TIPG);
1224 tipg &= ~E1000_TIPG_IPGT_MASK;
1225 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1226 ew32(TIPG, tipg);
1228 do {
1229 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1230 if (ret_val)
1231 return ret_val;
1233 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1234 if (ret_val)
1235 return ret_val;
1236 i++;
1237 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1239 if (duplex == HALF_DUPLEX)
1240 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1241 else
1242 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1244 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1246 return 0;
1250 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1251 * @hw: pointer to the HW structure
1253 * Configure the KMRN interface by applying last minute quirks for
1254 * gigabit operation.
1256 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1258 s32 ret_val;
1259 u16 reg_data, reg_data2;
1260 u32 tipg;
1261 u32 i = 0;
1263 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1264 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1265 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1266 reg_data);
1267 if (ret_val)
1268 return ret_val;
1270 /* Configure Transmit Inter-Packet Gap */
1271 tipg = er32(TIPG);
1272 tipg &= ~E1000_TIPG_IPGT_MASK;
1273 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1274 ew32(TIPG, tipg);
1276 do {
1277 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1278 if (ret_val)
1279 return ret_val;
1281 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1282 if (ret_val)
1283 return ret_val;
1284 i++;
1285 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1287 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1288 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1290 return ret_val;
1294 * e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1295 * @hw: pointer to the HW structure
1296 * @offset: register offset to be read
1297 * @data: pointer to the read data
1299 * Acquire semaphore, then read the PHY register at offset
1300 * using the kumeran interface. The information retrieved is stored in data.
1301 * Release the semaphore before exiting.
1303 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1304 u16 *data)
1306 u32 kmrnctrlsta;
1307 s32 ret_val = 0;
1309 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1310 if (ret_val)
1311 return ret_val;
1313 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1314 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1315 ew32(KMRNCTRLSTA, kmrnctrlsta);
1316 e1e_flush();
1318 udelay(2);
1320 kmrnctrlsta = er32(KMRNCTRLSTA);
1321 *data = (u16)kmrnctrlsta;
1323 e1000_release_mac_csr_80003es2lan(hw);
1325 return ret_val;
1329 * e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1330 * @hw: pointer to the HW structure
1331 * @offset: register offset to write to
1332 * @data: data to write at register offset
1334 * Acquire semaphore, then write the data to PHY register
1335 * at the offset using the kumeran interface. Release semaphore
1336 * before exiting.
1338 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1339 u16 data)
1341 u32 kmrnctrlsta;
1342 s32 ret_val = 0;
1344 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1345 if (ret_val)
1346 return ret_val;
1348 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1349 E1000_KMRNCTRLSTA_OFFSET) | data;
1350 ew32(KMRNCTRLSTA, kmrnctrlsta);
1351 e1e_flush();
1353 udelay(2);
1355 e1000_release_mac_csr_80003es2lan(hw);
1357 return ret_val;
1361 * e1000_read_mac_addr_80003es2lan - Read device MAC address
1362 * @hw: pointer to the HW structure
1364 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1366 s32 ret_val = 0;
1369 * If there's an alternate MAC address place it in RAR0
1370 * so that it will override the Si installed default perm
1371 * address.
1373 ret_val = e1000_check_alt_mac_addr_generic(hw);
1374 if (ret_val)
1375 goto out;
1377 ret_val = e1000_read_mac_addr_generic(hw);
1379 out:
1380 return ret_val;
1384 * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1385 * @hw: pointer to the HW structure
1387 * In the case of a PHY power down to save power, or to turn off link during a
1388 * driver unload, or wake on lan is not enabled, remove the link.
1390 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1392 /* If the management interface is not enabled, then power down */
1393 if (!(hw->mac.ops.check_mng_mode(hw) ||
1394 hw->phy.ops.check_reset_block(hw)))
1395 e1000_power_down_phy_copper(hw);
1399 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1400 * @hw: pointer to the HW structure
1402 * Clears the hardware counters by reading the counter registers.
1404 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1406 e1000e_clear_hw_cntrs_base(hw);
1408 er32(PRC64);
1409 er32(PRC127);
1410 er32(PRC255);
1411 er32(PRC511);
1412 er32(PRC1023);
1413 er32(PRC1522);
1414 er32(PTC64);
1415 er32(PTC127);
1416 er32(PTC255);
1417 er32(PTC511);
1418 er32(PTC1023);
1419 er32(PTC1522);
1421 er32(ALGNERRC);
1422 er32(RXERRC);
1423 er32(TNCRS);
1424 er32(CEXTERR);
1425 er32(TSCTC);
1426 er32(TSCTFC);
1428 er32(MGTPRC);
1429 er32(MGTPDC);
1430 er32(MGTPTC);
1432 er32(IAC);
1433 er32(ICRXOC);
1435 er32(ICRXPTC);
1436 er32(ICRXATC);
1437 er32(ICTXPTC);
1438 er32(ICTXATC);
1439 er32(ICTXQEC);
1440 er32(ICTXQMTC);
1441 er32(ICRXDMTC);
1444 static struct e1000_mac_operations es2_mac_ops = {
1445 .read_mac_addr = e1000_read_mac_addr_80003es2lan,
1446 .id_led_init = e1000e_id_led_init,
1447 .blink_led = e1000e_blink_led_generic,
1448 .check_mng_mode = e1000e_check_mng_mode_generic,
1449 /* check_for_link dependent on media type */
1450 .cleanup_led = e1000e_cleanup_led_generic,
1451 .clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan,
1452 .get_bus_info = e1000e_get_bus_info_pcie,
1453 .set_lan_id = e1000_set_lan_id_multi_port_pcie,
1454 .get_link_up_info = e1000_get_link_up_info_80003es2lan,
1455 .led_on = e1000e_led_on_generic,
1456 .led_off = e1000e_led_off_generic,
1457 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
1458 .write_vfta = e1000_write_vfta_generic,
1459 .clear_vfta = e1000_clear_vfta_generic,
1460 .reset_hw = e1000_reset_hw_80003es2lan,
1461 .init_hw = e1000_init_hw_80003es2lan,
1462 .setup_link = e1000e_setup_link,
1463 /* setup_physical_interface dependent on media type */
1464 .setup_led = e1000e_setup_led_generic,
1467 static struct e1000_phy_operations es2_phy_ops = {
1468 .acquire = e1000_acquire_phy_80003es2lan,
1469 .check_polarity = e1000_check_polarity_m88,
1470 .check_reset_block = e1000e_check_reset_block_generic,
1471 .commit = e1000e_phy_sw_reset,
1472 .force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan,
1473 .get_cfg_done = e1000_get_cfg_done_80003es2lan,
1474 .get_cable_length = e1000_get_cable_length_80003es2lan,
1475 .get_info = e1000e_get_phy_info_m88,
1476 .read_reg = e1000_read_phy_reg_gg82563_80003es2lan,
1477 .release = e1000_release_phy_80003es2lan,
1478 .reset = e1000e_phy_hw_reset_generic,
1479 .set_d0_lplu_state = NULL,
1480 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1481 .write_reg = e1000_write_phy_reg_gg82563_80003es2lan,
1482 .cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan,
1485 static struct e1000_nvm_operations es2_nvm_ops = {
1486 .acquire = e1000_acquire_nvm_80003es2lan,
1487 .read = e1000e_read_nvm_eerd,
1488 .release = e1000_release_nvm_80003es2lan,
1489 .update = e1000e_update_nvm_checksum_generic,
1490 .valid_led_default = e1000e_valid_led_default,
1491 .validate = e1000e_validate_nvm_checksum_generic,
1492 .write = e1000_write_nvm_80003es2lan,
1495 struct e1000_info e1000_es2_info = {
1496 .mac = e1000_80003es2lan,
1497 .flags = FLAG_HAS_HW_VLAN_FILTER
1498 | FLAG_HAS_JUMBO_FRAMES
1499 | FLAG_HAS_WOL
1500 | FLAG_APME_IN_CTRL3
1501 | FLAG_HAS_CTRLEXT_ON_LOAD
1502 | FLAG_RX_NEEDS_RESTART /* errata */
1503 | FLAG_TARC_SET_BIT_ZERO /* errata */
1504 | FLAG_APME_CHECK_PORT_B
1505 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
1506 | FLAG_TIPG_MEDIUM_FOR_80003ESLAN,
1507 .flags2 = FLAG2_DMA_BURST,
1508 .pba = 38,
1509 .max_hw_frame_size = DEFAULT_JUMBO,
1510 .get_variants = e1000_get_variants_80003es2lan,
1511 .mac_ops = &es2_mac_ops,
1512 .phy_ops = &es2_phy_ops,
1513 .nvm_ops = &es2_nvm_ops,