drivers/net/ethernet/intel/ixgbe/ixgbe.h

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2011 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #ifndef _IXGBE_H_
  29 #define _IXGBE_H_
  30
  31 #include <linux/bitops.h>
  32 #include <linux/types.h>
  33 #include <linux/pci.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/cpumask.h>
  36 #include <linux/aer.h>
  37 #include <linux/if_vlan.h>
  38
  39 #include "ixgbe_type.h"
  40 #include "ixgbe_common.h"
  41 #include "ixgbe_dcb.h"
  42 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
  43 #define IXGBE_FCOE
  44 #include "ixgbe_fcoe.h"
  45 #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
  46 #ifdef CONFIG_IXGBE_DCA
  47 #include <linux/dca.h>
  48 #endif
  49
  50 /* common prefix used by pr_<> macros */
  51 #undef pr_fmt
  52 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  53
  54 /* TX/RX descriptor defines */
  55 #define IXGBE_DEFAULT_TXD                   512
  56 #define IXGBE_MAX_TXD                      4096
  57 #define IXGBE_MIN_TXD                        64
  58
  59 #define IXGBE_DEFAULT_RXD                   512
  60 #define IXGBE_MAX_RXD                      4096
  61 #define IXGBE_MIN_RXD                        64
  62
  63 /* flow control */
  64 #define IXGBE_MIN_FCRTL                    0x40
  65 #define IXGBE_MAX_FCRTL                 0x7FF80
  66 #define IXGBE_MIN_FCRTH                   0x600
  67 #define IXGBE_MAX_FCRTH                 0x7FFF0
  68 #define IXGBE_DEFAULT_FCPAUSE            0xFFFF
  69 #define IXGBE_MIN_FCPAUSE                     0
  70 #define IXGBE_MAX_FCPAUSE                0xFFFF
  71
  72 /* Supported Rx Buffer Sizes */
  73 #define IXGBE_RXBUFFER_512   512    /* Used for packet split */
  74 #define IXGBE_RXBUFFER_2048  2048
  75 #define IXGBE_RXBUFFER_4096  4096
  76 #define IXGBE_RXBUFFER_8192  8192
  77 #define IXGBE_MAX_RXBUFFER   16384  /* largest size for a single descriptor */
  78
  79 /*
  80  * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we
  81  * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
  82  * this adds up to 512 bytes of extra data meaning the smallest allocation
  83  * we could have is 1K.
  84  * i.e. RXBUFFER_512 --> size-1024 slab
  85  */
  86 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512
  87
  88 #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
  89
  90 /* How many Rx Buffers do we bundle into one write to the hardware ? */
  91 #define IXGBE_RX_BUFFER_WRITE   16      /* Must be power of 2 */
  92
  93 #define IXGBE_TX_FLAGS_CSUM             (u32)(1)
  94 #define IXGBE_TX_FLAGS_HW_VLAN          (u32)(1 << 1)
  95 #define IXGBE_TX_FLAGS_SW_VLAN          (u32)(1 << 2)
  96 #define IXGBE_TX_FLAGS_TSO              (u32)(1 << 3)
  97 #define IXGBE_TX_FLAGS_IPV4             (u32)(1 << 4)
  98 #define IXGBE_TX_FLAGS_FCOE             (u32)(1 << 5)
  99 #define IXGBE_TX_FLAGS_FSO              (u32)(1 << 6)
 100 #define IXGBE_TX_FLAGS_TXSW             (u32)(1 << 7)
 101 #define IXGBE_TX_FLAGS_MAPPED_AS_PAGE   (u32)(1 << 8)
 102 #define IXGBE_TX_FLAGS_VLAN_MASK        0xffff0000
 103 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK   0xe0000000
 104 #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT  29
 105 #define IXGBE_TX_FLAGS_VLAN_SHIFT       16
 106
 107 #define IXGBE_MAX_RSC_INT_RATE          162760
 108
 109 #define IXGBE_MAX_VF_MC_ENTRIES         30
 110 #define IXGBE_MAX_VF_FUNCTIONS          64
 111 #define IXGBE_MAX_VFTA_ENTRIES          128
 112 #define MAX_EMULATION_MAC_ADDRS         16
 113 #define IXGBE_MAX_PF_MACVLANS           15
 114 #define VMDQ_P(p)   ((p) + adapter->num_vfs)
 115
 116 struct vf_data_storage {
 117         unsigned char vf_mac_addresses[ETH_ALEN];
 118         u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
 119         u16 num_vf_mc_hashes;
 120         u16 default_vf_vlan_id;
 121         u16 vlans_enabled;
 122         bool clear_to_send;
 123         bool pf_set_mac;
 124         u16 pf_vlan; /* When set, guest VLAN config not allowed. */
 125         u16 pf_qos;
 126         u16 tx_rate;
 127 };
 128
 129 struct vf_macvlans {
 130         struct list_head l;
 131         int vf;
 132         int rar_entry;
 133         bool free;
 134         bool is_macvlan;
 135         u8 vf_macvlan[ETH_ALEN];
 136 };
 137
 138 #define IXGBE_MAX_TXD_PWR       14
 139 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 140
 141 /* Tx Descriptors needed, worst case */
 142 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
 143 #define DESC_NEEDED ((MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE)) + 4)
 144
 145 /* wrapper around a pointer to a socket buffer,
 146  * so a DMA handle can be stored along with the buffer */
 147 struct ixgbe_tx_buffer {
 148         union ixgbe_adv_tx_desc *next_to_watch;
 149         unsigned long time_stamp;
 150         dma_addr_t dma;
 151         u32 length;
 152         u32 tx_flags;
 153         struct sk_buff *skb;
 154         u32 bytecount;
 155         u16 gso_segs;
 156 };
 157
 158 struct ixgbe_rx_buffer {
 159         struct sk_buff *skb;
 160         dma_addr_t dma;
 161         struct page *page;
 162         dma_addr_t page_dma;
 163         unsigned int page_offset;
 164 };
 165
 166 struct ixgbe_queue_stats {
 167         u64 packets;
 168         u64 bytes;
 169 };
 170
 171 struct ixgbe_tx_queue_stats {
 172         u64 restart_queue;
 173         u64 tx_busy;
 174         u64 completed;
 175         u64 tx_done_old;
 176 };
 177
 178 struct ixgbe_rx_queue_stats {
 179         u64 rsc_count;
 180         u64 rsc_flush;
 181         u64 non_eop_descs;
 182         u64 alloc_rx_page_failed;
 183         u64 alloc_rx_buff_failed;
 184 };
 185
 186 enum ixbge_ring_state_t {
 187         __IXGBE_TX_FDIR_INIT_DONE,
 188         __IXGBE_TX_DETECT_HANG,
 189         __IXGBE_HANG_CHECK_ARMED,
 190         __IXGBE_RX_PS_ENABLED,
 191         __IXGBE_RX_RSC_ENABLED,
 192 };
 193
 194 #define ring_is_ps_enabled(ring) \
 195         test_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
 196 #define set_ring_ps_enabled(ring) \
 197         set_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
 198 #define clear_ring_ps_enabled(ring) \
 199         clear_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
 200 #define check_for_tx_hang(ring) \
 201         test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
 202 #define set_check_for_tx_hang(ring) \
 203         set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
 204 #define clear_check_for_tx_hang(ring) \
 205         clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
 206 #define ring_is_rsc_enabled(ring) \
 207         test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
 208 #define set_ring_rsc_enabled(ring) \
 209         set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
 210 #define clear_ring_rsc_enabled(ring) \
 211         clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
 212 struct ixgbe_ring {
 213         struct ixgbe_ring *next;        /* pointer to next ring in q_vector */
 214         void *desc;                     /* descriptor ring memory */
 215         struct device *dev;             /* device for DMA mapping */
 216         struct net_device *netdev;      /* netdev ring belongs to */
 217         union {
 218                 struct ixgbe_tx_buffer *tx_buffer_info;
 219                 struct ixgbe_rx_buffer *rx_buffer_info;
 220         };
 221         unsigned long state;
 222         u8 __iomem *tail;
 223
 224         u16 count;                      /* amount of descriptors */
 225         u16 rx_buf_len;
 226
 227         u8 queue_index; /* needed for multiqueue queue management */
 228         u8 reg_idx;                     /* holds the special value that gets
 229                                          * the hardware register offset
 230                                          * associated with this ring, which is
 231                                          * different for DCB and RSS modes
 232                                          */
 233         u8 atr_sample_rate;
 234         u8 atr_count;
 235
 236         u16 next_to_use;
 237         u16 next_to_clean;
 238
 239         u8 dcb_tc;
 240         struct ixgbe_queue_stats stats;
 241         struct u64_stats_sync syncp;
 242         union {
 243                 struct ixgbe_tx_queue_stats tx_stats;
 244                 struct ixgbe_rx_queue_stats rx_stats;
 245         };
 246         int numa_node;
 247         unsigned int size;              /* length in bytes */
 248         dma_addr_t dma;                 /* phys. address of descriptor ring */
 249         struct rcu_head rcu;
 250         struct ixgbe_q_vector *q_vector; /* back-pointer to host q_vector */
 251 } ____cacheline_internodealigned_in_smp;
 252
 253 enum ixgbe_ring_f_enum {
 254         RING_F_NONE = 0,
 255         RING_F_VMDQ,  /* SR-IOV uses the same ring feature */
 256         RING_F_RSS,
 257         RING_F_FDIR,
 258 #ifdef IXGBE_FCOE
 259         RING_F_FCOE,
 260 #endif /* IXGBE_FCOE */
 261
 262         RING_F_ARRAY_SIZE      /* must be last in enum set */
 263 };
 264
 265 #define IXGBE_MAX_RSS_INDICES  16
 266 #define IXGBE_MAX_VMDQ_INDICES 64
 267 #define IXGBE_MAX_FDIR_INDICES 64
 268 #ifdef IXGBE_FCOE
 269 #define IXGBE_MAX_FCOE_INDICES  8
 270 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
 271 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
 272 #else
 273 #define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
 274 #define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
 275 #endif /* IXGBE_FCOE */
 276 struct ixgbe_ring_feature {
 277         int indices;
 278         int mask;
 279 } ____cacheline_internodealigned_in_smp;
 280
 281 struct ixgbe_ring_container {
 282         struct ixgbe_ring *ring;        /* pointer to linked list of rings */
 283         unsigned int total_bytes;       /* total bytes processed this int */
 284         unsigned int total_packets;     /* total packets processed this int */
 285         u16 work_limit;                 /* total work allowed per interrupt */
 286         u8 count;                       /* total number of rings in vector */
 287         u8 itr;                         /* current ITR setting for ring */
 288 };
 289
 290 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
 291                               ? 8 : 1)
 292 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
 293
 294 /* MAX_MSIX_Q_VECTORS of these are allocated,
 295  * but we only use one per queue-specific vector.
 296  */
 297 struct ixgbe_q_vector {
 298         struct ixgbe_adapter *adapter;
 299         unsigned int v_idx; /* index of q_vector within array, also used for
 300                              * finding the bit in EICR and friends that
 301                              * represents the vector for this ring */
 302 #ifdef CONFIG_IXGBE_DCA
 303         int cpu;            /* CPU for DCA */
 304 #endif
 305         struct napi_struct napi;
 306         struct ixgbe_ring_container rx, tx;
 307         u32 eitr;
 308         cpumask_var_t affinity_mask;
 309         char name[IFNAMSIZ + 9];
 310 };
 311
 312 /* Helper macros to switch between ints/sec and what the register uses.
 313  * And yes, it's the same math going both ways.  The lowest value
 314  * supported by all of the ixgbe hardware is 8.
 315  */
 316 #define EITR_INTS_PER_SEC_TO_REG(_eitr) \
 317         ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
 318 #define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
 319
 320 static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring)
 321 {
 322         u16 ntc = ring->next_to_clean;
 323         u16 ntu = ring->next_to_use;
 324
 325         return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
 326 }
 327
 328 #define IXGBE_RX_DESC_ADV(R, i)     \
 329         (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
 330 #define IXGBE_TX_DESC_ADV(R, i)     \
 331         (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
 332 #define IXGBE_TX_CTXTDESC_ADV(R, i)         \
 333         (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
 334
 335 #define IXGBE_MAX_JUMBO_FRAME_SIZE        16128
 336 #ifdef IXGBE_FCOE
 337 /* Use 3K as the baby jumbo frame size for FCoE */
 338 #define IXGBE_FCOE_JUMBO_FRAME_SIZE       3072
 339 #endif /* IXGBE_FCOE */
 340
 341 #define OTHER_VECTOR 1
 342 #define NON_Q_VECTORS (OTHER_VECTOR)
 343
 344 #define MAX_MSIX_VECTORS_82599 64
 345 #define MAX_MSIX_Q_VECTORS_82599 64
 346 #define MAX_MSIX_VECTORS_82598 18
 347 #define MAX_MSIX_Q_VECTORS_82598 16
 348
 349 #define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
 350 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
 351
 352 #define MIN_MSIX_Q_VECTORS 2
 353 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
 354
 355 /* board specific private data structure */
 356 struct ixgbe_adapter {
 357         unsigned long state;
 358
 359         /* Some features need tri-state capability,
 360          * thus the additional *_CAPABLE flags.
 361          */
 362         u32 flags;
 363 #define IXGBE_FLAG_RX_CSUM_ENABLED              (u32)(1)
 364 #define IXGBE_FLAG_MSI_CAPABLE                  (u32)(1 << 1)
 365 #define IXGBE_FLAG_MSI_ENABLED                  (u32)(1 << 2)
 366 #define IXGBE_FLAG_MSIX_CAPABLE                 (u32)(1 << 3)
 367 #define IXGBE_FLAG_MSIX_ENABLED                 (u32)(1 << 4)
 368 #define IXGBE_FLAG_RX_1BUF_CAPABLE              (u32)(1 << 6)
 369 #define IXGBE_FLAG_RX_PS_CAPABLE                (u32)(1 << 7)
 370 #define IXGBE_FLAG_RX_PS_ENABLED                (u32)(1 << 8)
 371 #define IXGBE_FLAG_IN_NETPOLL                   (u32)(1 << 9)
 372 #define IXGBE_FLAG_DCA_ENABLED                  (u32)(1 << 10)
 373 #define IXGBE_FLAG_DCA_CAPABLE                  (u32)(1 << 11)
 374 #define IXGBE_FLAG_IMIR_ENABLED                 (u32)(1 << 12)
 375 #define IXGBE_FLAG_MQ_CAPABLE                   (u32)(1 << 13)
 376 #define IXGBE_FLAG_DCB_ENABLED                  (u32)(1 << 14)
 377 #define IXGBE_FLAG_RSS_ENABLED                  (u32)(1 << 16)
 378 #define IXGBE_FLAG_RSS_CAPABLE                  (u32)(1 << 17)
 379 #define IXGBE_FLAG_VMDQ_CAPABLE                 (u32)(1 << 18)
 380 #define IXGBE_FLAG_VMDQ_ENABLED                 (u32)(1 << 19)
 381 #define IXGBE_FLAG_FAN_FAIL_CAPABLE             (u32)(1 << 20)
 382 #define IXGBE_FLAG_NEED_LINK_UPDATE             (u32)(1 << 22)
 383 #define IXGBE_FLAG_NEED_LINK_CONFIG             (u32)(1 << 23)
 384 #define IXGBE_FLAG_FDIR_HASH_CAPABLE            (u32)(1 << 24)
 385 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE         (u32)(1 << 25)
 386 #define IXGBE_FLAG_FCOE_CAPABLE                 (u32)(1 << 26)
 387 #define IXGBE_FLAG_FCOE_ENABLED                 (u32)(1 << 27)
 388 #define IXGBE_FLAG_SRIOV_CAPABLE                (u32)(1 << 28)
 389 #define IXGBE_FLAG_SRIOV_ENABLED                (u32)(1 << 29)
 390
 391         u32 flags2;
 392 #define IXGBE_FLAG2_RSC_CAPABLE                 (u32)(1)
 393 #define IXGBE_FLAG2_RSC_ENABLED                 (u32)(1 << 1)
 394 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE         (u32)(1 << 2)
 395 #define IXGBE_FLAG2_TEMP_SENSOR_EVENT           (u32)(1 << 3)
 396 #define IXGBE_FLAG2_SEARCH_FOR_SFP              (u32)(1 << 4)
 397 #define IXGBE_FLAG2_SFP_NEEDS_RESET             (u32)(1 << 5)
 398 #define IXGBE_FLAG2_RESET_REQUESTED             (u32)(1 << 6)
 399 #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT        (u32)(1 << 7)
 400
 401         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 402         u16 bd_number;
 403         struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
 404
 405         /* DCB parameters */
 406         struct ieee_pfc *ixgbe_ieee_pfc;
 407         struct ieee_ets *ixgbe_ieee_ets;
 408         struct ixgbe_dcb_config dcb_cfg;
 409         struct ixgbe_dcb_config temp_dcb_cfg;
 410         u8 dcb_set_bitmap;
 411         u8 dcbx_cap;
 412         enum ixgbe_fc_mode last_lfc_mode;
 413
 414         /* Interrupt Throttle Rate */
 415         u32 rx_itr_setting;
 416         u32 tx_itr_setting;
 417         u16 eitr_low;
 418         u16 eitr_high;
 419
 420         /* Work limits */
 421         u16 tx_work_limit;
 422
 423         /* TX */
 424         struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
 425         int num_tx_queues;
 426         u32 tx_timeout_count;
 427         bool detect_tx_hung;
 428
 429         u64 restart_queue;
 430         u64 lsc_int;
 431
 432         /* RX */
 433         struct ixgbe_ring *rx_ring[MAX_RX_QUEUES] ____cacheline_aligned_in_smp;
 434         int num_rx_queues;
 435         int num_rx_pools;               /* == num_rx_queues in 82598 */
 436         int num_rx_queues_per_pool;     /* 1 if 82598, can be many if 82599 */
 437         u64 hw_csum_rx_error;
 438         u64 hw_rx_no_dma_resources;
 439         u64 non_eop_descs;
 440         int num_msix_vectors;
 441         int max_msix_q_vectors;         /* true count of q_vectors for device */
 442         struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
 443         struct msix_entry *msix_entries;
 444
 445         u32 alloc_rx_page_failed;
 446         u32 alloc_rx_buff_failed;
 447
 448 /* default to trying for four seconds */
 449 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
 450
 451         /* OS defined structs */
 452         struct net_device *netdev;
 453         struct pci_dev *pdev;
 454
 455         u32 test_icr;
 456         struct ixgbe_ring test_tx_ring;
 457         struct ixgbe_ring test_rx_ring;
 458
 459         /* structs defined in ixgbe_hw.h */
 460         struct ixgbe_hw hw;
 461         u16 msg_enable;
 462         struct ixgbe_hw_stats stats;
 463
 464         /* Interrupt Throttle Rate */
 465         u32 rx_eitr_param;
 466         u32 tx_eitr_param;
 467
 468         u64 tx_busy;
 469         unsigned int tx_ring_count;
 470         unsigned int rx_ring_count;
 471
 472         u32 link_speed;
 473         bool link_up;
 474         unsigned long link_check_timeout;
 475
 476         struct work_struct service_task;
 477         struct timer_list service_timer;
 478         u32 fdir_pballoc;
 479         u32 atr_sample_rate;
 480         unsigned long fdir_overflow; /* number of times ATR was backed off */
 481         spinlock_t fdir_perfect_lock;
 482 #ifdef IXGBE_FCOE
 483         struct ixgbe_fcoe fcoe;
 484 #endif /* IXGBE_FCOE */
 485         u64 rsc_total_count;
 486         u64 rsc_total_flush;
 487         u32 wol;
 488         u16 eeprom_version;
 489
 490         int node;
 491         u32 led_reg;
 492         u32 interrupt_event;
 493         char lsc_int_name[IFNAMSIZ + 9];
 494
 495         /* SR-IOV */
 496         DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
 497         unsigned int num_vfs;
 498         struct vf_data_storage *vfinfo;
 499         int vf_rate_link_speed;
 500         struct vf_macvlans vf_mvs;
 501         struct vf_macvlans *mv_list;
 502         bool antispoofing_enabled;
 503
 504         struct hlist_head fdir_filter_list;
 505         union ixgbe_atr_input fdir_mask;
 506         int fdir_filter_count;
 507 };
 508
 509 struct ixgbe_fdir_filter {
 510         struct hlist_node fdir_node;
 511         union ixgbe_atr_input filter;
 512         u16 sw_idx;
 513         u16 action;
 514 };
 515
 516 enum ixbge_state_t {
 517         __IXGBE_TESTING,
 518         __IXGBE_RESETTING,
 519         __IXGBE_DOWN,
 520         __IXGBE_SERVICE_SCHED,
 521         __IXGBE_IN_SFP_INIT,
 522 };
 523
 524 struct ixgbe_rsc_cb {
 525         dma_addr_t dma;
 526         u16 skb_cnt;
 527         bool delay_unmap;
 528 };
 529 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
 530
 531 enum ixgbe_boards {
 532         board_82598,
 533         board_82599,
 534         board_X540,
 535 };
 536
 537 extern struct ixgbe_info ixgbe_82598_info;
 538 extern struct ixgbe_info ixgbe_82599_info;
 539 extern struct ixgbe_info ixgbe_X540_info;
 540 #ifdef CONFIG_IXGBE_DCB
 541 extern const struct dcbnl_rtnl_ops dcbnl_ops;
 542 extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
 543                               struct ixgbe_dcb_config *dst_dcb_cfg,
 544                               int tc_max);
 545 #endif
 546
 547 extern char ixgbe_driver_name[];
 548 extern const char ixgbe_driver_version[];
 549
 550 extern int ixgbe_up(struct ixgbe_adapter *adapter);
 551 extern void ixgbe_down(struct ixgbe_adapter *adapter);
 552 extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
 553 extern void ixgbe_reset(struct ixgbe_adapter *adapter);
 554 extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
 555 extern int ixgbe_setup_rx_resources(struct ixgbe_ring *);
 556 extern int ixgbe_setup_tx_resources(struct ixgbe_ring *);
 557 extern void ixgbe_free_rx_resources(struct ixgbe_ring *);
 558 extern void ixgbe_free_tx_resources(struct ixgbe_ring *);
 559 extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
 560 extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
 561 extern void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
 562                                    struct ixgbe_ring *);
 563 extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
 564 extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
 565 extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
 566 extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *,
 567                                          struct ixgbe_adapter *,
 568                                          struct ixgbe_ring *);
 569 extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
 570                                              struct ixgbe_tx_buffer *);
 571 extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
 572 extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
 573 extern int ethtool_ioctl(struct ifreq *ifr);
 574 extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
 575 extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
 576 extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
 577 extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
 578                                                  union ixgbe_atr_hash_dword input,
 579                                                  union ixgbe_atr_hash_dword common,
 580                                                  u8 queue);
 581 extern s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
 582                                            union ixgbe_atr_input *input_mask);
 583 extern s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
 584                                                  union ixgbe_atr_input *input,
 585                                                  u16 soft_id, u8 queue);
 586 extern s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
 587                                                  union ixgbe_atr_input *input,
 588                                                  u16 soft_id);
 589 extern void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
 590                                                  union ixgbe_atr_input *mask);
 591 extern void ixgbe_set_rx_mode(struct net_device *netdev);
 592 extern int ixgbe_setup_tc(struct net_device *dev, u8 tc);
 593 extern void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32);
 594 extern void ixgbe_do_reset(struct net_device *netdev);
 595 #ifdef IXGBE_FCOE
 596 extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
 597 extern int ixgbe_fso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
 598                      u32 tx_flags, u8 *hdr_len);
 599 extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
 600 extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
 601                           union ixgbe_adv_rx_desc *rx_desc,
 602                           struct sk_buff *skb,
 603                           u32 staterr);
 604 extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
 605                               struct scatterlist *sgl, unsigned int sgc);
 606 extern int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
 607                                  struct scatterlist *sgl, unsigned int sgc);
 608 extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
 609 extern int ixgbe_fcoe_enable(struct net_device *netdev);
 610 extern int ixgbe_fcoe_disable(struct net_device *netdev);
 611 #ifdef CONFIG_IXGBE_DCB
 612 extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
 613 extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
 614 #endif /* CONFIG_IXGBE_DCB */
 615 extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
 616 #endif /* IXGBE_FCOE */
 617
 618 #endif /* _IXGBE_H_ */