1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
33 #include "ixgbe_phy.h"
34 #include "ixgbe_mbx.h"
36 #define IXGBE_82599_MAX_TX_QUEUES 128
37 #define IXGBE_82599_MAX_RX_QUEUES 128
38 #define IXGBE_82599_RAR_ENTRIES 128
39 #define IXGBE_82599_MC_TBL_SIZE 128
40 #define IXGBE_82599_VFT_TBL_SIZE 128
41 #define IXGBE_82599_RX_PB_SIZE 512
43 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
);
44 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
);
45 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
);
46 static s32
ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw
*hw
,
47 ixgbe_link_speed speed
,
49 bool autoneg_wait_to_complete
);
50 static s32
ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw
*hw
,
51 ixgbe_link_speed speed
,
53 bool autoneg_wait_to_complete
);
54 static s32
ixgbe_start_mac_link_82599(struct ixgbe_hw
*hw
,
55 bool autoneg_wait_to_complete
);
56 static s32
ixgbe_setup_mac_link_82599(struct ixgbe_hw
*hw
,
57 ixgbe_link_speed speed
,
59 bool autoneg_wait_to_complete
);
60 static s32
ixgbe_setup_copper_link_82599(struct ixgbe_hw
*hw
,
61 ixgbe_link_speed speed
,
63 bool autoneg_wait_to_complete
);
64 static s32
ixgbe_verify_fw_version_82599(struct ixgbe_hw
*hw
);
65 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw
*hw
);
67 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw
*hw
)
69 struct ixgbe_mac_info
*mac
= &hw
->mac
;
71 /* enable the laser control functions for SFP+ fiber */
72 if (mac
->ops
.get_media_type(hw
) == ixgbe_media_type_fiber
) {
73 mac
->ops
.disable_tx_laser
=
74 &ixgbe_disable_tx_laser_multispeed_fiber
;
75 mac
->ops
.enable_tx_laser
=
76 &ixgbe_enable_tx_laser_multispeed_fiber
;
77 mac
->ops
.flap_tx_laser
= &ixgbe_flap_tx_laser_multispeed_fiber
;
79 mac
->ops
.disable_tx_laser
= NULL
;
80 mac
->ops
.enable_tx_laser
= NULL
;
81 mac
->ops
.flap_tx_laser
= NULL
;
84 if (hw
->phy
.multispeed_fiber
) {
85 /* Set up dual speed SFP+ support */
86 mac
->ops
.setup_link
= &ixgbe_setup_mac_link_multispeed_fiber
;
88 if ((mac
->ops
.get_media_type(hw
) ==
89 ixgbe_media_type_backplane
) &&
90 (hw
->phy
.smart_speed
== ixgbe_smart_speed_auto
||
91 hw
->phy
.smart_speed
== ixgbe_smart_speed_on
) &&
92 !ixgbe_verify_lesm_fw_enabled_82599(hw
))
93 mac
->ops
.setup_link
= &ixgbe_setup_mac_link_smartspeed
;
95 mac
->ops
.setup_link
= &ixgbe_setup_mac_link_82599
;
99 static s32
ixgbe_setup_sfp_modules_82599(struct ixgbe_hw
*hw
)
104 u16 list_offset
, data_offset
, data_value
;
106 if (hw
->phy
.sfp_type
!= ixgbe_sfp_type_unknown
) {
107 ixgbe_init_mac_link_ops_82599(hw
);
109 hw
->phy
.ops
.reset
= NULL
;
111 ret_val
= ixgbe_get_sfp_init_sequence_offsets(hw
, &list_offset
,
116 /* PHY config will finish before releasing the semaphore */
117 ret_val
= hw
->mac
.ops
.acquire_swfw_sync(hw
,
118 IXGBE_GSSR_MAC_CSR_SM
);
120 ret_val
= IXGBE_ERR_SWFW_SYNC
;
124 hw
->eeprom
.ops
.read(hw
, ++data_offset
, &data_value
);
125 while (data_value
!= 0xffff) {
126 IXGBE_WRITE_REG(hw
, IXGBE_CORECTL
, data_value
);
127 IXGBE_WRITE_FLUSH(hw
);
128 hw
->eeprom
.ops
.read(hw
, ++data_offset
, &data_value
);
131 /* Release the semaphore */
132 hw
->mac
.ops
.release_swfw_sync(hw
, IXGBE_GSSR_MAC_CSR_SM
);
134 * Delay obtaining semaphore again to allow FW access,
135 * semaphore_delay is in ms usleep_range needs us.
137 usleep_range(hw
->eeprom
.semaphore_delay
* 1000,
138 hw
->eeprom
.semaphore_delay
* 2000);
140 /* Now restart DSP by setting Restart_AN and clearing LMS */
141 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, ((IXGBE_READ_REG(hw
,
142 IXGBE_AUTOC
) & ~IXGBE_AUTOC_LMS_MASK
) |
143 IXGBE_AUTOC_AN_RESTART
));
145 /* Wait for AN to leave state 0 */
146 for (i
= 0; i
< 10; i
++) {
147 usleep_range(4000, 8000);
148 reg_anlp1
= IXGBE_READ_REG(hw
, IXGBE_ANLP1
);
149 if (reg_anlp1
& IXGBE_ANLP1_AN_STATE_MASK
)
152 if (!(reg_anlp1
& IXGBE_ANLP1_AN_STATE_MASK
)) {
153 hw_dbg(hw
, "sfp module setup not complete\n");
154 ret_val
= IXGBE_ERR_SFP_SETUP_NOT_COMPLETE
;
158 /* Restart DSP by setting Restart_AN and return to SFI mode */
159 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, (IXGBE_READ_REG(hw
,
160 IXGBE_AUTOC
) | IXGBE_AUTOC_LMS_10G_SERIAL
|
161 IXGBE_AUTOC_AN_RESTART
));
168 static s32
ixgbe_get_invariants_82599(struct ixgbe_hw
*hw
)
170 struct ixgbe_mac_info
*mac
= &hw
->mac
;
172 ixgbe_init_mac_link_ops_82599(hw
);
174 mac
->mcft_size
= IXGBE_82599_MC_TBL_SIZE
;
175 mac
->vft_size
= IXGBE_82599_VFT_TBL_SIZE
;
176 mac
->num_rar_entries
= IXGBE_82599_RAR_ENTRIES
;
177 mac
->max_rx_queues
= IXGBE_82599_MAX_RX_QUEUES
;
178 mac
->max_tx_queues
= IXGBE_82599_MAX_TX_QUEUES
;
179 mac
->max_msix_vectors
= ixgbe_get_pcie_msix_count_generic(hw
);
185 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
186 * @hw: pointer to hardware structure
188 * Initialize any function pointers that were not able to be
189 * set during get_invariants because the PHY/SFP type was
190 * not known. Perform the SFP init if necessary.
193 static s32
ixgbe_init_phy_ops_82599(struct ixgbe_hw
*hw
)
195 struct ixgbe_mac_info
*mac
= &hw
->mac
;
196 struct ixgbe_phy_info
*phy
= &hw
->phy
;
199 /* Identify the PHY or SFP module */
200 ret_val
= phy
->ops
.identify(hw
);
202 /* Setup function pointers based on detected SFP module and speeds */
203 ixgbe_init_mac_link_ops_82599(hw
);
205 /* If copper media, overwrite with copper function pointers */
206 if (mac
->ops
.get_media_type(hw
) == ixgbe_media_type_copper
) {
207 mac
->ops
.setup_link
= &ixgbe_setup_copper_link_82599
;
208 mac
->ops
.get_link_capabilities
=
209 &ixgbe_get_copper_link_capabilities_generic
;
212 /* Set necessary function pointers based on phy type */
213 switch (hw
->phy
.type
) {
215 phy
->ops
.check_link
= &ixgbe_check_phy_link_tnx
;
216 phy
->ops
.setup_link
= &ixgbe_setup_phy_link_tnx
;
217 phy
->ops
.get_firmware_version
=
218 &ixgbe_get_phy_firmware_version_tnx
;
221 phy
->ops
.get_firmware_version
=
222 &ixgbe_get_phy_firmware_version_generic
;
232 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
233 * @hw: pointer to hardware structure
234 * @speed: pointer to link speed
235 * @negotiation: true when autoneg or autotry is enabled
237 * Determines the link capabilities by reading the AUTOC register.
239 static s32
ixgbe_get_link_capabilities_82599(struct ixgbe_hw
*hw
,
240 ixgbe_link_speed
*speed
,
246 /* Determine 1G link capabilities off of SFP+ type */
247 if (hw
->phy
.sfp_type
== ixgbe_sfp_type_1g_cu_core0
||
248 hw
->phy
.sfp_type
== ixgbe_sfp_type_1g_cu_core1
) {
249 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
255 * Determine link capabilities based on the stored value of AUTOC,
256 * which represents EEPROM defaults. If AUTOC value has not been
257 * stored, use the current register value.
259 if (hw
->mac
.orig_link_settings_stored
)
260 autoc
= hw
->mac
.orig_autoc
;
262 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
264 switch (autoc
& IXGBE_AUTOC_LMS_MASK
) {
265 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN
:
266 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
267 *negotiation
= false;
270 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN
:
271 *speed
= IXGBE_LINK_SPEED_10GB_FULL
;
272 *negotiation
= false;
275 case IXGBE_AUTOC_LMS_1G_AN
:
276 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
280 case IXGBE_AUTOC_LMS_10G_SERIAL
:
281 *speed
= IXGBE_LINK_SPEED_10GB_FULL
;
282 *negotiation
= false;
285 case IXGBE_AUTOC_LMS_KX4_KX_KR
:
286 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
:
287 *speed
= IXGBE_LINK_SPEED_UNKNOWN
;
288 if (autoc
& IXGBE_AUTOC_KR_SUPP
)
289 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
290 if (autoc
& IXGBE_AUTOC_KX4_SUPP
)
291 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
292 if (autoc
& IXGBE_AUTOC_KX_SUPP
)
293 *speed
|= IXGBE_LINK_SPEED_1GB_FULL
;
297 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII
:
298 *speed
= IXGBE_LINK_SPEED_100_FULL
;
299 if (autoc
& IXGBE_AUTOC_KR_SUPP
)
300 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
301 if (autoc
& IXGBE_AUTOC_KX4_SUPP
)
302 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
303 if (autoc
& IXGBE_AUTOC_KX_SUPP
)
304 *speed
|= IXGBE_LINK_SPEED_1GB_FULL
;
308 case IXGBE_AUTOC_LMS_SGMII_1G_100M
:
309 *speed
= IXGBE_LINK_SPEED_1GB_FULL
| IXGBE_LINK_SPEED_100_FULL
;
310 *negotiation
= false;
314 status
= IXGBE_ERR_LINK_SETUP
;
319 if (hw
->phy
.multispeed_fiber
) {
320 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
|
321 IXGBE_LINK_SPEED_1GB_FULL
;
330 * ixgbe_get_media_type_82599 - Get media type
331 * @hw: pointer to hardware structure
333 * Returns the media type (fiber, copper, backplane)
335 static enum ixgbe_media_type
ixgbe_get_media_type_82599(struct ixgbe_hw
*hw
)
337 enum ixgbe_media_type media_type
;
339 /* Detect if there is a copper PHY attached. */
340 switch (hw
->phy
.type
) {
341 case ixgbe_phy_cu_unknown
:
344 media_type
= ixgbe_media_type_copper
;
350 switch (hw
->device_id
) {
351 case IXGBE_DEV_ID_82599_KX4
:
352 case IXGBE_DEV_ID_82599_KX4_MEZZ
:
353 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE
:
354 case IXGBE_DEV_ID_82599_KR
:
355 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE
:
356 case IXGBE_DEV_ID_82599_XAUI_LOM
:
357 /* Default device ID is mezzanine card KX/KX4 */
358 media_type
= ixgbe_media_type_backplane
;
360 case IXGBE_DEV_ID_82599_SFP
:
361 case IXGBE_DEV_ID_82599_SFP_FCOE
:
362 case IXGBE_DEV_ID_82599_SFP_EM
:
363 case IXGBE_DEV_ID_82599_SFP_SF2
:
364 media_type
= ixgbe_media_type_fiber
;
366 case IXGBE_DEV_ID_82599_CX4
:
367 media_type
= ixgbe_media_type_cx4
;
369 case IXGBE_DEV_ID_82599_T3_LOM
:
370 media_type
= ixgbe_media_type_copper
;
372 case IXGBE_DEV_ID_82599_LS
:
373 media_type
= ixgbe_media_type_fiber_lco
;
376 media_type
= ixgbe_media_type_unknown
;
384 * ixgbe_start_mac_link_82599 - Setup MAC link settings
385 * @hw: pointer to hardware structure
386 * @autoneg_wait_to_complete: true when waiting for completion is needed
388 * Configures link settings based on values in the ixgbe_hw struct.
389 * Restarts the link. Performs autonegotiation if needed.
391 static s32
ixgbe_start_mac_link_82599(struct ixgbe_hw
*hw
,
392 bool autoneg_wait_to_complete
)
400 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
401 autoc_reg
|= IXGBE_AUTOC_AN_RESTART
;
402 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, autoc_reg
);
404 /* Only poll for autoneg to complete if specified to do so */
405 if (autoneg_wait_to_complete
) {
406 if ((autoc_reg
& IXGBE_AUTOC_LMS_MASK
) ==
407 IXGBE_AUTOC_LMS_KX4_KX_KR
||
408 (autoc_reg
& IXGBE_AUTOC_LMS_MASK
) ==
409 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
||
410 (autoc_reg
& IXGBE_AUTOC_LMS_MASK
) ==
411 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII
) {
412 links_reg
= 0; /* Just in case Autoneg time = 0 */
413 for (i
= 0; i
< IXGBE_AUTO_NEG_TIME
; i
++) {
414 links_reg
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
415 if (links_reg
& IXGBE_LINKS_KX_AN_COMP
)
419 if (!(links_reg
& IXGBE_LINKS_KX_AN_COMP
)) {
420 status
= IXGBE_ERR_AUTONEG_NOT_COMPLETE
;
421 hw_dbg(hw
, "Autoneg did not complete.\n");
426 /* Add delay to filter out noises during initial link setup */
433 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
434 * @hw: pointer to hardware structure
436 * The base drivers may require better control over SFP+ module
437 * PHY states. This includes selectively shutting down the Tx
438 * laser on the PHY, effectively halting physical link.
440 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
)
442 u32 esdp_reg
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
444 /* Disable tx laser; allow 100us to go dark per spec */
445 esdp_reg
|= IXGBE_ESDP_SDP3
;
446 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
447 IXGBE_WRITE_FLUSH(hw
);
452 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
453 * @hw: pointer to hardware structure
455 * The base drivers may require better control over SFP+ module
456 * PHY states. This includes selectively turning on the Tx
457 * laser on the PHY, effectively starting physical link.
459 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
)
461 u32 esdp_reg
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
463 /* Enable tx laser; allow 100ms to light up */
464 esdp_reg
&= ~IXGBE_ESDP_SDP3
;
465 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
466 IXGBE_WRITE_FLUSH(hw
);
471 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
472 * @hw: pointer to hardware structure
474 * When the driver changes the link speeds that it can support,
475 * it sets autotry_restart to true to indicate that we need to
476 * initiate a new autotry session with the link partner. To do
477 * so, we set the speed then disable and re-enable the tx laser, to
478 * alert the link partner that it also needs to restart autotry on its
479 * end. This is consistent with true clause 37 autoneg, which also
480 * involves a loss of signal.
482 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
)
484 if (hw
->mac
.autotry_restart
) {
485 ixgbe_disable_tx_laser_multispeed_fiber(hw
);
486 ixgbe_enable_tx_laser_multispeed_fiber(hw
);
487 hw
->mac
.autotry_restart
= false;
492 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
493 * @hw: pointer to hardware structure
494 * @speed: new link speed
495 * @autoneg: true if autonegotiation enabled
496 * @autoneg_wait_to_complete: true when waiting for completion is needed
498 * Set the link speed in the AUTOC register and restarts link.
500 static s32
ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw
*hw
,
501 ixgbe_link_speed speed
,
503 bool autoneg_wait_to_complete
)
506 ixgbe_link_speed link_speed
= IXGBE_LINK_SPEED_UNKNOWN
;
507 ixgbe_link_speed highest_link_speed
= IXGBE_LINK_SPEED_UNKNOWN
;
509 u32 esdp_reg
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
511 bool link_up
= false;
514 /* Mask off requested but non-supported speeds */
515 status
= hw
->mac
.ops
.get_link_capabilities(hw
, &link_speed
,
523 * Try each speed one by one, highest priority first. We do this in
524 * software because 10gb fiber doesn't support speed autonegotiation.
526 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
) {
528 highest_link_speed
= IXGBE_LINK_SPEED_10GB_FULL
;
530 /* If we already have link at this speed, just jump out */
531 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
,
536 if ((link_speed
== IXGBE_LINK_SPEED_10GB_FULL
) && link_up
)
539 /* Set the module link speed */
540 esdp_reg
|= (IXGBE_ESDP_SDP5_DIR
| IXGBE_ESDP_SDP5
);
541 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
542 IXGBE_WRITE_FLUSH(hw
);
544 /* Allow module to change analog characteristics (1G->10G) */
547 status
= ixgbe_setup_mac_link_82599(hw
,
548 IXGBE_LINK_SPEED_10GB_FULL
,
550 autoneg_wait_to_complete
);
554 /* Flap the tx laser if it has not already been done */
555 hw
->mac
.ops
.flap_tx_laser(hw
);
558 * Wait for the controller to acquire link. Per IEEE 802.3ap,
559 * Section 73.10.2, we may have to wait up to 500ms if KR is
560 * attempted. 82599 uses the same timing for 10g SFI.
562 for (i
= 0; i
< 5; i
++) {
563 /* Wait for the link partner to also set speed */
566 /* If we have link, just jump out */
567 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
,
577 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
) {
579 if (highest_link_speed
== IXGBE_LINK_SPEED_UNKNOWN
)
580 highest_link_speed
= IXGBE_LINK_SPEED_1GB_FULL
;
582 /* If we already have link at this speed, just jump out */
583 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
,
588 if ((link_speed
== IXGBE_LINK_SPEED_1GB_FULL
) && link_up
)
591 /* Set the module link speed */
592 esdp_reg
&= ~IXGBE_ESDP_SDP5
;
593 esdp_reg
|= IXGBE_ESDP_SDP5_DIR
;
594 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
595 IXGBE_WRITE_FLUSH(hw
);
597 /* Allow module to change analog characteristics (10G->1G) */
600 status
= ixgbe_setup_mac_link_82599(hw
,
601 IXGBE_LINK_SPEED_1GB_FULL
,
603 autoneg_wait_to_complete
);
607 /* Flap the tx laser if it has not already been done */
608 hw
->mac
.ops
.flap_tx_laser(hw
);
610 /* Wait for the link partner to also set speed */
613 /* If we have link, just jump out */
614 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
,
624 * We didn't get link. Configure back to the highest speed we tried,
625 * (if there was more than one). We call ourselves back with just the
626 * single highest speed that the user requested.
629 status
= ixgbe_setup_mac_link_multispeed_fiber(hw
,
632 autoneg_wait_to_complete
);
635 /* Set autoneg_advertised value based on input link speed */
636 hw
->phy
.autoneg_advertised
= 0;
638 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
)
639 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_10GB_FULL
;
641 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
)
642 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_1GB_FULL
;
648 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
649 * @hw: pointer to hardware structure
650 * @speed: new link speed
651 * @autoneg: true if autonegotiation enabled
652 * @autoneg_wait_to_complete: true when waiting for completion is needed
654 * Implements the Intel SmartSpeed algorithm.
656 static s32
ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw
*hw
,
657 ixgbe_link_speed speed
, bool autoneg
,
658 bool autoneg_wait_to_complete
)
661 ixgbe_link_speed link_speed
= IXGBE_LINK_SPEED_UNKNOWN
;
663 bool link_up
= false;
664 u32 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
666 /* Set autoneg_advertised value based on input link speed */
667 hw
->phy
.autoneg_advertised
= 0;
669 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
)
670 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_10GB_FULL
;
672 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
)
673 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_1GB_FULL
;
675 if (speed
& IXGBE_LINK_SPEED_100_FULL
)
676 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_100_FULL
;
679 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
680 * autoneg advertisement if link is unable to be established at the
681 * highest negotiated rate. This can sometimes happen due to integrity
682 * issues with the physical media connection.
685 /* First, try to get link with full advertisement */
686 hw
->phy
.smart_speed_active
= false;
687 for (j
= 0; j
< IXGBE_SMARTSPEED_MAX_RETRIES
; j
++) {
688 status
= ixgbe_setup_mac_link_82599(hw
, speed
, autoneg
,
689 autoneg_wait_to_complete
);
694 * Wait for the controller to acquire link. Per IEEE 802.3ap,
695 * Section 73.10.2, we may have to wait up to 500ms if KR is
696 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
697 * Table 9 in the AN MAS.
699 for (i
= 0; i
< 5; i
++) {
702 /* If we have link, just jump out */
703 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
,
714 * We didn't get link. If we advertised KR plus one of KX4/KX
715 * (or BX4/BX), then disable KR and try again.
717 if (((autoc_reg
& IXGBE_AUTOC_KR_SUPP
) == 0) ||
718 ((autoc_reg
& IXGBE_AUTOC_KX4_KX_SUPP_MASK
) == 0))
721 /* Turn SmartSpeed on to disable KR support */
722 hw
->phy
.smart_speed_active
= true;
723 status
= ixgbe_setup_mac_link_82599(hw
, speed
, autoneg
,
724 autoneg_wait_to_complete
);
729 * Wait for the controller to acquire link. 600ms will allow for
730 * the AN link_fail_inhibit_timer as well for multiple cycles of
731 * parallel detect, both 10g and 1g. This allows for the maximum
732 * connect attempts as defined in the AN MAS table 73-7.
734 for (i
= 0; i
< 6; i
++) {
737 /* If we have link, just jump out */
738 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
,
747 /* We didn't get link. Turn SmartSpeed back off. */
748 hw
->phy
.smart_speed_active
= false;
749 status
= ixgbe_setup_mac_link_82599(hw
, speed
, autoneg
,
750 autoneg_wait_to_complete
);
753 if (link_up
&& (link_speed
== IXGBE_LINK_SPEED_1GB_FULL
))
754 hw_dbg(hw
, "Smartspeed has downgraded the link speed from "
755 "the maximum advertised\n");
760 * ixgbe_setup_mac_link_82599 - Set MAC link speed
761 * @hw: pointer to hardware structure
762 * @speed: new link speed
763 * @autoneg: true if autonegotiation enabled
764 * @autoneg_wait_to_complete: true when waiting for completion is needed
766 * Set the link speed in the AUTOC register and restarts link.
768 static s32
ixgbe_setup_mac_link_82599(struct ixgbe_hw
*hw
,
769 ixgbe_link_speed speed
, bool autoneg
,
770 bool autoneg_wait_to_complete
)
773 u32 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
774 u32 autoc2
= IXGBE_READ_REG(hw
, IXGBE_AUTOC2
);
775 u32 start_autoc
= autoc
;
777 u32 link_mode
= autoc
& IXGBE_AUTOC_LMS_MASK
;
778 u32 pma_pmd_1g
= autoc
& IXGBE_AUTOC_1G_PMA_PMD_MASK
;
779 u32 pma_pmd_10g_serial
= autoc2
& IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK
;
782 ixgbe_link_speed link_capabilities
= IXGBE_LINK_SPEED_UNKNOWN
;
784 /* Check to see if speed passed in is supported. */
785 hw
->mac
.ops
.get_link_capabilities(hw
, &link_capabilities
, &autoneg
);
789 speed
&= link_capabilities
;
791 if (speed
== IXGBE_LINK_SPEED_UNKNOWN
) {
792 status
= IXGBE_ERR_LINK_SETUP
;
796 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
797 if (hw
->mac
.orig_link_settings_stored
)
798 orig_autoc
= hw
->mac
.orig_autoc
;
802 if (link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR
||
803 link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
||
804 link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII
) {
805 /* Set KX4/KX/KR support according to speed requested */
806 autoc
&= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK
| IXGBE_AUTOC_KR_SUPP
);
807 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
)
808 if (orig_autoc
& IXGBE_AUTOC_KX4_SUPP
)
809 autoc
|= IXGBE_AUTOC_KX4_SUPP
;
810 if ((orig_autoc
& IXGBE_AUTOC_KR_SUPP
) &&
811 (hw
->phy
.smart_speed_active
== false))
812 autoc
|= IXGBE_AUTOC_KR_SUPP
;
813 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
)
814 autoc
|= IXGBE_AUTOC_KX_SUPP
;
815 } else if ((pma_pmd_1g
== IXGBE_AUTOC_1G_SFI
) &&
816 (link_mode
== IXGBE_AUTOC_LMS_1G_LINK_NO_AN
||
817 link_mode
== IXGBE_AUTOC_LMS_1G_AN
)) {
818 /* Switch from 1G SFI to 10G SFI if requested */
819 if ((speed
== IXGBE_LINK_SPEED_10GB_FULL
) &&
820 (pma_pmd_10g_serial
== IXGBE_AUTOC2_10G_SFI
)) {
821 autoc
&= ~IXGBE_AUTOC_LMS_MASK
;
822 autoc
|= IXGBE_AUTOC_LMS_10G_SERIAL
;
824 } else if ((pma_pmd_10g_serial
== IXGBE_AUTOC2_10G_SFI
) &&
825 (link_mode
== IXGBE_AUTOC_LMS_10G_SERIAL
)) {
826 /* Switch from 10G SFI to 1G SFI if requested */
827 if ((speed
== IXGBE_LINK_SPEED_1GB_FULL
) &&
828 (pma_pmd_1g
== IXGBE_AUTOC_1G_SFI
)) {
829 autoc
&= ~IXGBE_AUTOC_LMS_MASK
;
831 autoc
|= IXGBE_AUTOC_LMS_1G_AN
;
833 autoc
|= IXGBE_AUTOC_LMS_1G_LINK_NO_AN
;
837 if (autoc
!= start_autoc
) {
839 autoc
|= IXGBE_AUTOC_AN_RESTART
;
840 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, autoc
);
842 /* Only poll for autoneg to complete if specified to do so */
843 if (autoneg_wait_to_complete
) {
844 if (link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR
||
845 link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
||
846 link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII
) {
847 links_reg
= 0; /*Just in case Autoneg time=0*/
848 for (i
= 0; i
< IXGBE_AUTO_NEG_TIME
; i
++) {
850 IXGBE_READ_REG(hw
, IXGBE_LINKS
);
851 if (links_reg
& IXGBE_LINKS_KX_AN_COMP
)
855 if (!(links_reg
& IXGBE_LINKS_KX_AN_COMP
)) {
857 IXGBE_ERR_AUTONEG_NOT_COMPLETE
;
858 hw_dbg(hw
, "Autoneg did not "
864 /* Add delay to filter out noises during initial link setup */
873 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
874 * @hw: pointer to hardware structure
875 * @speed: new link speed
876 * @autoneg: true if autonegotiation enabled
877 * @autoneg_wait_to_complete: true if waiting is needed to complete
879 * Restarts link on PHY and MAC based on settings passed in.
881 static s32
ixgbe_setup_copper_link_82599(struct ixgbe_hw
*hw
,
882 ixgbe_link_speed speed
,
884 bool autoneg_wait_to_complete
)
888 /* Setup the PHY according to input speed */
889 status
= hw
->phy
.ops
.setup_link_speed(hw
, speed
, autoneg
,
890 autoneg_wait_to_complete
);
892 ixgbe_start_mac_link_82599(hw
, autoneg_wait_to_complete
);
898 * ixgbe_reset_hw_82599 - Perform hardware reset
899 * @hw: pointer to hardware structure
901 * Resets the hardware by resetting the transmit and receive units, masks
902 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
905 static s32
ixgbe_reset_hw_82599(struct ixgbe_hw
*hw
)
913 /* Call adapter stop to disable tx/rx and clear interrupts */
914 hw
->mac
.ops
.stop_adapter(hw
);
916 /* PHY ops must be identified and initialized prior to reset */
918 /* Identify PHY and related function pointers */
919 status
= hw
->phy
.ops
.init(hw
);
921 if (status
== IXGBE_ERR_SFP_NOT_SUPPORTED
)
924 /* Setup SFP module if there is one present. */
925 if (hw
->phy
.sfp_setup_needed
) {
926 status
= hw
->mac
.ops
.setup_sfp(hw
);
927 hw
->phy
.sfp_setup_needed
= false;
930 if (status
== IXGBE_ERR_SFP_NOT_SUPPORTED
)
934 if (hw
->phy
.reset_disable
== false && hw
->phy
.ops
.reset
!= NULL
)
935 hw
->phy
.ops
.reset(hw
);
938 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
939 * access and verify no pending requests before reset
941 ixgbe_disable_pcie_master(hw
);
945 * Issue global reset to the MAC. This needs to be a SW reset.
946 * If link reset is used, it might reset the MAC when mng is using it
948 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
949 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, (ctrl
| IXGBE_CTRL_RST
));
950 IXGBE_WRITE_FLUSH(hw
);
952 /* Poll for reset bit to self-clear indicating reset is complete */
953 for (i
= 0; i
< 10; i
++) {
955 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
956 if (!(ctrl
& IXGBE_CTRL_RST
))
959 if (ctrl
& IXGBE_CTRL_RST
) {
960 status
= IXGBE_ERR_RESET_FAILED
;
961 hw_dbg(hw
, "Reset polling failed to complete.\n");
965 * Double resets are required for recovery from certain error
966 * conditions. Between resets, it is necessary to stall to allow time
967 * for any pending HW events to complete. We use 1usec since that is
968 * what is needed for ixgbe_disable_pcie_master(). The second reset
969 * then clears out any effects of those events.
971 if (hw
->mac
.flags
& IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
) {
972 hw
->mac
.flags
&= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
;
980 * Store the original AUTOC/AUTOC2 values if they have not been
981 * stored off yet. Otherwise restore the stored original
982 * values since the reset operation sets back to defaults.
984 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
985 autoc2
= IXGBE_READ_REG(hw
, IXGBE_AUTOC2
);
986 if (hw
->mac
.orig_link_settings_stored
== false) {
987 hw
->mac
.orig_autoc
= autoc
;
988 hw
->mac
.orig_autoc2
= autoc2
;
989 hw
->mac
.orig_link_settings_stored
= true;
991 if (autoc
!= hw
->mac
.orig_autoc
)
992 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, (hw
->mac
.orig_autoc
|
993 IXGBE_AUTOC_AN_RESTART
));
995 if ((autoc2
& IXGBE_AUTOC2_UPPER_MASK
) !=
996 (hw
->mac
.orig_autoc2
& IXGBE_AUTOC2_UPPER_MASK
)) {
997 autoc2
&= ~IXGBE_AUTOC2_UPPER_MASK
;
998 autoc2
|= (hw
->mac
.orig_autoc2
&
999 IXGBE_AUTOC2_UPPER_MASK
);
1000 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC2
, autoc2
);
1004 /* Store the permanent mac address */
1005 hw
->mac
.ops
.get_mac_addr(hw
, hw
->mac
.perm_addr
);
1008 * Store MAC address from RAR0, clear receive address registers, and
1009 * clear the multicast table. Also reset num_rar_entries to 128,
1010 * since we modify this value when programming the SAN MAC address.
1012 hw
->mac
.num_rar_entries
= 128;
1013 hw
->mac
.ops
.init_rx_addrs(hw
);
1015 /* Store the permanent SAN mac address */
1016 hw
->mac
.ops
.get_san_mac_addr(hw
, hw
->mac
.san_addr
);
1018 /* Add the SAN MAC address to the RAR only if it's a valid address */
1019 if (ixgbe_validate_mac_addr(hw
->mac
.san_addr
) == 0) {
1020 hw
->mac
.ops
.set_rar(hw
, hw
->mac
.num_rar_entries
- 1,
1021 hw
->mac
.san_addr
, 0, IXGBE_RAH_AV
);
1023 /* Reserve the last RAR for the SAN MAC address */
1024 hw
->mac
.num_rar_entries
--;
1027 /* Store the alternative WWNN/WWPN prefix */
1028 hw
->mac
.ops
.get_wwn_prefix(hw
, &hw
->mac
.wwnn_prefix
,
1029 &hw
->mac
.wwpn_prefix
);
1036 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1037 * @hw: pointer to hardware structure
1039 s32
ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw
*hw
)
1042 u32 fdirctrl
= IXGBE_READ_REG(hw
, IXGBE_FDIRCTRL
);
1043 fdirctrl
&= ~IXGBE_FDIRCTRL_INIT_DONE
;
1046 * Before starting reinitialization process,
1047 * FDIRCMD.CMD must be zero.
1049 for (i
= 0; i
< IXGBE_FDIRCMD_CMD_POLL
; i
++) {
1050 if (!(IXGBE_READ_REG(hw
, IXGBE_FDIRCMD
) &
1051 IXGBE_FDIRCMD_CMD_MASK
))
1055 if (i
>= IXGBE_FDIRCMD_CMD_POLL
) {
1056 hw_dbg(hw
, "Flow Director previous command isn't complete, "
1057 "aborting table re-initialization.\n");
1058 return IXGBE_ERR_FDIR_REINIT_FAILED
;
1061 IXGBE_WRITE_REG(hw
, IXGBE_FDIRFREE
, 0);
1062 IXGBE_WRITE_FLUSH(hw
);
1064 * 82599 adapters flow director init flow cannot be restarted,
1065 * Workaround 82599 silicon errata by performing the following steps
1066 * before re-writing the FDIRCTRL control register with the same value.
1067 * - write 1 to bit 8 of FDIRCMD register &
1068 * - write 0 to bit 8 of FDIRCMD register
1070 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCMD
,
1071 (IXGBE_READ_REG(hw
, IXGBE_FDIRCMD
) |
1072 IXGBE_FDIRCMD_CLEARHT
));
1073 IXGBE_WRITE_FLUSH(hw
);
1074 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCMD
,
1075 (IXGBE_READ_REG(hw
, IXGBE_FDIRCMD
) &
1076 ~IXGBE_FDIRCMD_CLEARHT
));
1077 IXGBE_WRITE_FLUSH(hw
);
1079 * Clear FDIR Hash register to clear any leftover hashes
1080 * waiting to be programmed.
1082 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHASH
, 0x00);
1083 IXGBE_WRITE_FLUSH(hw
);
1085 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCTRL
, fdirctrl
);
1086 IXGBE_WRITE_FLUSH(hw
);
1088 /* Poll init-done after we write FDIRCTRL register */
1089 for (i
= 0; i
< IXGBE_FDIR_INIT_DONE_POLL
; i
++) {
1090 if (IXGBE_READ_REG(hw
, IXGBE_FDIRCTRL
) &
1091 IXGBE_FDIRCTRL_INIT_DONE
)
1095 if (i
>= IXGBE_FDIR_INIT_DONE_POLL
) {
1096 hw_dbg(hw
, "Flow Director Signature poll time exceeded!\n");
1097 return IXGBE_ERR_FDIR_REINIT_FAILED
;
1100 /* Clear FDIR statistics registers (read to clear) */
1101 IXGBE_READ_REG(hw
, IXGBE_FDIRUSTAT
);
1102 IXGBE_READ_REG(hw
, IXGBE_FDIRFSTAT
);
1103 IXGBE_READ_REG(hw
, IXGBE_FDIRMATCH
);
1104 IXGBE_READ_REG(hw
, IXGBE_FDIRMISS
);
1105 IXGBE_READ_REG(hw
, IXGBE_FDIRLEN
);
1111 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1112 * @hw: pointer to hardware structure
1113 * @fdirctrl: value to write to flow director control register
1115 static void ixgbe_fdir_enable_82599(struct ixgbe_hw
*hw
, u32 fdirctrl
)
1119 /* Prime the keys for hashing */
1120 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHKEY
, IXGBE_ATR_BUCKET_HASH_KEY
);
1121 IXGBE_WRITE_REG(hw
, IXGBE_FDIRSKEY
, IXGBE_ATR_SIGNATURE_HASH_KEY
);
1124 * Poll init-done after we write the register. Estimated times:
1125 * 10G: PBALLOC = 11b, timing is 60us
1126 * 1G: PBALLOC = 11b, timing is 600us
1127 * 100M: PBALLOC = 11b, timing is 6ms
1129 * Multiple these timings by 4 if under full Rx load
1131 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1132 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1133 * this might not finish in our poll time, but we can live with that
1136 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCTRL
, fdirctrl
);
1137 IXGBE_WRITE_FLUSH(hw
);
1138 for (i
= 0; i
< IXGBE_FDIR_INIT_DONE_POLL
; i
++) {
1139 if (IXGBE_READ_REG(hw
, IXGBE_FDIRCTRL
) &
1140 IXGBE_FDIRCTRL_INIT_DONE
)
1142 usleep_range(1000, 2000);
1145 if (i
>= IXGBE_FDIR_INIT_DONE_POLL
)
1146 hw_dbg(hw
, "Flow Director poll time exceeded!\n");
1150 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1151 * @hw: pointer to hardware structure
1152 * @fdirctrl: value to write to flow director control register, initially
1153 * contains just the value of the Rx packet buffer allocation
1155 s32
ixgbe_init_fdir_signature_82599(struct ixgbe_hw
*hw
, u32 fdirctrl
)
1158 * Continue setup of fdirctrl register bits:
1159 * Move the flexible bytes to use the ethertype - shift 6 words
1160 * Set the maximum length per hash bucket to 0xA filters
1161 * Send interrupt when 64 filters are left
1163 fdirctrl
|= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT
) |
1164 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT
) |
1165 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT
);
1167 /* write hashes and fdirctrl register, poll for completion */
1168 ixgbe_fdir_enable_82599(hw
, fdirctrl
);
1174 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1175 * @hw: pointer to hardware structure
1176 * @fdirctrl: value to write to flow director control register, initially
1177 * contains just the value of the Rx packet buffer allocation
1179 s32
ixgbe_init_fdir_perfect_82599(struct ixgbe_hw
*hw
, u32 fdirctrl
)
1182 * Continue setup of fdirctrl register bits:
1183 * Turn perfect match filtering on
1184 * Report hash in RSS field of Rx wb descriptor
1185 * Initialize the drop queue
1186 * Move the flexible bytes to use the ethertype - shift 6 words
1187 * Set the maximum length per hash bucket to 0xA filters
1188 * Send interrupt when 64 (0x4 * 16) filters are left
1190 fdirctrl
|= IXGBE_FDIRCTRL_PERFECT_MATCH
|
1191 IXGBE_FDIRCTRL_REPORT_STATUS
|
1192 (IXGBE_FDIR_DROP_QUEUE
<< IXGBE_FDIRCTRL_DROP_Q_SHIFT
) |
1193 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT
) |
1194 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT
) |
1195 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT
);
1197 /* write hashes and fdirctrl register, poll for completion */
1198 ixgbe_fdir_enable_82599(hw
, fdirctrl
);
1204 * These defines allow us to quickly generate all of the necessary instructions
1205 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1206 * for values 0 through 15
1208 #define IXGBE_ATR_COMMON_HASH_KEY \
1209 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1210 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1213 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1214 common_hash ^= lo_hash_dword >> n; \
1215 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1216 bucket_hash ^= lo_hash_dword >> n; \
1217 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1218 sig_hash ^= lo_hash_dword << (16 - n); \
1219 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1220 common_hash ^= hi_hash_dword >> n; \
1221 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1222 bucket_hash ^= hi_hash_dword >> n; \
1223 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1224 sig_hash ^= hi_hash_dword << (16 - n); \
1228 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1229 * @stream: input bitstream to compute the hash on
1231 * This function is almost identical to the function above but contains
1232 * several optomizations such as unwinding all of the loops, letting the
1233 * compiler work out all of the conditional ifs since the keys are static
1234 * defines, and computing two keys at once since the hashed dword stream
1235 * will be the same for both keys.
1237 static u32
ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input
,
1238 union ixgbe_atr_hash_dword common
)
1240 u32 hi_hash_dword
, lo_hash_dword
, flow_vm_vlan
;
1241 u32 sig_hash
= 0, bucket_hash
= 0, common_hash
= 0;
1243 /* record the flow_vm_vlan bits as they are a key part to the hash */
1244 flow_vm_vlan
= ntohl(input
.dword
);
1246 /* generate common hash dword */
1247 hi_hash_dword
= ntohl(common
.dword
);
1249 /* low dword is word swapped version of common */
1250 lo_hash_dword
= (hi_hash_dword
>> 16) | (hi_hash_dword
<< 16);
1252 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1253 hi_hash_dword
^= flow_vm_vlan
^ (flow_vm_vlan
>> 16);
1255 /* Process bits 0 and 16 */
1256 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1259 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1260 * delay this because bit 0 of the stream should not be processed
1261 * so we do not add the vlan until after bit 0 was processed
1263 lo_hash_dword
^= flow_vm_vlan
^ (flow_vm_vlan
<< 16);
1265 /* Process remaining 30 bit of the key */
1266 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1267 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1268 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1269 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1270 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1271 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1272 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1273 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1274 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1275 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1276 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1277 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1278 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1279 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1280 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1282 /* combine common_hash result with signature and bucket hashes */
1283 bucket_hash
^= common_hash
;
1284 bucket_hash
&= IXGBE_ATR_HASH_MASK
;
1286 sig_hash
^= common_hash
<< 16;
1287 sig_hash
&= IXGBE_ATR_HASH_MASK
<< 16;
1289 /* return completed signature hash */
1290 return sig_hash
^ bucket_hash
;
1294 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1295 * @hw: pointer to hardware structure
1296 * @input: unique input dword
1297 * @common: compressed common input dword
1298 * @queue: queue index to direct traffic to
1300 s32
ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw
*hw
,
1301 union ixgbe_atr_hash_dword input
,
1302 union ixgbe_atr_hash_dword common
,
1309 * Get the flow_type in order to program FDIRCMD properly
1310 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1312 switch (input
.formatted
.flow_type
) {
1313 case IXGBE_ATR_FLOW_TYPE_TCPV4
:
1314 case IXGBE_ATR_FLOW_TYPE_UDPV4
:
1315 case IXGBE_ATR_FLOW_TYPE_SCTPV4
:
1316 case IXGBE_ATR_FLOW_TYPE_TCPV6
:
1317 case IXGBE_ATR_FLOW_TYPE_UDPV6
:
1318 case IXGBE_ATR_FLOW_TYPE_SCTPV6
:
1321 hw_dbg(hw
, " Error on flow type input\n");
1322 return IXGBE_ERR_CONFIG
;
1325 /* configure FDIRCMD register */
1326 fdircmd
= IXGBE_FDIRCMD_CMD_ADD_FLOW
| IXGBE_FDIRCMD_FILTER_UPDATE
|
1327 IXGBE_FDIRCMD_LAST
| IXGBE_FDIRCMD_QUEUE_EN
;
1328 fdircmd
|= input
.formatted
.flow_type
<< IXGBE_FDIRCMD_FLOW_TYPE_SHIFT
;
1329 fdircmd
|= (u32
)queue
<< IXGBE_FDIRCMD_RX_QUEUE_SHIFT
;
1332 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1333 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1335 fdirhashcmd
= (u64
)fdircmd
<< 32;
1336 fdirhashcmd
|= ixgbe_atr_compute_sig_hash_82599(input
, common
);
1337 IXGBE_WRITE_REG64(hw
, IXGBE_FDIRHASH
, fdirhashcmd
);
1339 hw_dbg(hw
, "Tx Queue=%x hash=%x\n", queue
, (u32
)fdirhashcmd
);
1344 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1347 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1348 bucket_hash ^= lo_hash_dword >> n; \
1349 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1350 bucket_hash ^= hi_hash_dword >> n; \
1354 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1355 * @atr_input: input bitstream to compute the hash on
1356 * @input_mask: mask for the input bitstream
1358 * This function serves two main purposes. First it applys the input_mask
1359 * to the atr_input resulting in a cleaned up atr_input data stream.
1360 * Secondly it computes the hash and stores it in the bkt_hash field at
1361 * the end of the input byte stream. This way it will be available for
1362 * future use without needing to recompute the hash.
1364 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input
*input
,
1365 union ixgbe_atr_input
*input_mask
)
1368 u32 hi_hash_dword
, lo_hash_dword
, flow_vm_vlan
;
1369 u32 bucket_hash
= 0;
1371 /* Apply masks to input data */
1372 input
->dword_stream
[0] &= input_mask
->dword_stream
[0];
1373 input
->dword_stream
[1] &= input_mask
->dword_stream
[1];
1374 input
->dword_stream
[2] &= input_mask
->dword_stream
[2];
1375 input
->dword_stream
[3] &= input_mask
->dword_stream
[3];
1376 input
->dword_stream
[4] &= input_mask
->dword_stream
[4];
1377 input
->dword_stream
[5] &= input_mask
->dword_stream
[5];
1378 input
->dword_stream
[6] &= input_mask
->dword_stream
[6];
1379 input
->dword_stream
[7] &= input_mask
->dword_stream
[7];
1380 input
->dword_stream
[8] &= input_mask
->dword_stream
[8];
1381 input
->dword_stream
[9] &= input_mask
->dword_stream
[9];
1382 input
->dword_stream
[10] &= input_mask
->dword_stream
[10];
1384 /* record the flow_vm_vlan bits as they are a key part to the hash */
1385 flow_vm_vlan
= ntohl(input
->dword_stream
[0]);
1387 /* generate common hash dword */
1388 hi_hash_dword
= ntohl(input
->dword_stream
[1] ^
1389 input
->dword_stream
[2] ^
1390 input
->dword_stream
[3] ^
1391 input
->dword_stream
[4] ^
1392 input
->dword_stream
[5] ^
1393 input
->dword_stream
[6] ^
1394 input
->dword_stream
[7] ^
1395 input
->dword_stream
[8] ^
1396 input
->dword_stream
[9] ^
1397 input
->dword_stream
[10]);
1399 /* low dword is word swapped version of common */
1400 lo_hash_dword
= (hi_hash_dword
>> 16) | (hi_hash_dword
<< 16);
1402 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1403 hi_hash_dword
^= flow_vm_vlan
^ (flow_vm_vlan
>> 16);
1405 /* Process bits 0 and 16 */
1406 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1409 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1410 * delay this because bit 0 of the stream should not be processed
1411 * so we do not add the vlan until after bit 0 was processed
1413 lo_hash_dword
^= flow_vm_vlan
^ (flow_vm_vlan
<< 16);
1415 /* Process remaining 30 bit of the key */
1416 IXGBE_COMPUTE_BKT_HASH_ITERATION(1);
1417 IXGBE_COMPUTE_BKT_HASH_ITERATION(2);
1418 IXGBE_COMPUTE_BKT_HASH_ITERATION(3);
1419 IXGBE_COMPUTE_BKT_HASH_ITERATION(4);
1420 IXGBE_COMPUTE_BKT_HASH_ITERATION(5);
1421 IXGBE_COMPUTE_BKT_HASH_ITERATION(6);
1422 IXGBE_COMPUTE_BKT_HASH_ITERATION(7);
1423 IXGBE_COMPUTE_BKT_HASH_ITERATION(8);
1424 IXGBE_COMPUTE_BKT_HASH_ITERATION(9);
1425 IXGBE_COMPUTE_BKT_HASH_ITERATION(10);
1426 IXGBE_COMPUTE_BKT_HASH_ITERATION(11);
1427 IXGBE_COMPUTE_BKT_HASH_ITERATION(12);
1428 IXGBE_COMPUTE_BKT_HASH_ITERATION(13);
1429 IXGBE_COMPUTE_BKT_HASH_ITERATION(14);
1430 IXGBE_COMPUTE_BKT_HASH_ITERATION(15);
1433 * Limit hash to 13 bits since max bucket count is 8K.
1434 * Store result at the end of the input stream.
1436 input
->formatted
.bkt_hash
= bucket_hash
& 0x1FFF;
1440 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1441 * @input_mask: mask to be bit swapped
1443 * The source and destination port masks for flow director are bit swapped
1444 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1445 * generate a correctly swapped value we need to bit swap the mask and that
1446 * is what is accomplished by this function.
1448 static u32
ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input
*input_mask
)
1450 u32 mask
= ntohs(input_mask
->formatted
.dst_port
);
1451 mask
<<= IXGBE_FDIRTCPM_DPORTM_SHIFT
;
1452 mask
|= ntohs(input_mask
->formatted
.src_port
);
1453 mask
= ((mask
& 0x55555555) << 1) | ((mask
& 0xAAAAAAAA) >> 1);
1454 mask
= ((mask
& 0x33333333) << 2) | ((mask
& 0xCCCCCCCC) >> 2);
1455 mask
= ((mask
& 0x0F0F0F0F) << 4) | ((mask
& 0xF0F0F0F0) >> 4);
1456 return ((mask
& 0x00FF00FF) << 8) | ((mask
& 0xFF00FF00) >> 8);
1460 * These two macros are meant to address the fact that we have registers
1461 * that are either all or in part big-endian. As a result on big-endian
1462 * systems we will end up byte swapping the value to little-endian before
1463 * it is byte swapped again and written to the hardware in the original
1464 * big-endian format.
1466 #define IXGBE_STORE_AS_BE32(_value) \
1467 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1468 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1470 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1471 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value)))
1473 #define IXGBE_STORE_AS_BE16(_value) \
1474 ntohs(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1476 s32
ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw
*hw
,
1477 union ixgbe_atr_input
*input_mask
)
1479 /* mask IPv6 since it is currently not supported */
1480 u32 fdirm
= IXGBE_FDIRM_DIPv6
;
1484 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1485 * are zero, then assume a full mask for that field. Also assume that
1486 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1487 * cannot be masked out in this implementation.
1489 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1493 /* verify bucket hash is cleared on hash generation */
1494 if (input_mask
->formatted
.bkt_hash
)
1495 hw_dbg(hw
, " bucket hash should always be 0 in mask\n");
1497 /* Program FDIRM and verify partial masks */
1498 switch (input_mask
->formatted
.vm_pool
& 0x7F) {
1500 fdirm
|= IXGBE_FDIRM_POOL
;
1504 hw_dbg(hw
, " Error on vm pool mask\n");
1505 return IXGBE_ERR_CONFIG
;
1508 switch (input_mask
->formatted
.flow_type
& IXGBE_ATR_L4TYPE_MASK
) {
1510 fdirm
|= IXGBE_FDIRM_L4P
;
1511 if (input_mask
->formatted
.dst_port
||
1512 input_mask
->formatted
.src_port
) {
1513 hw_dbg(hw
, " Error on src/dst port mask\n");
1514 return IXGBE_ERR_CONFIG
;
1516 case IXGBE_ATR_L4TYPE_MASK
:
1519 hw_dbg(hw
, " Error on flow type mask\n");
1520 return IXGBE_ERR_CONFIG
;
1523 switch (ntohs(input_mask
->formatted
.vlan_id
) & 0xEFFF) {
1525 /* mask VLAN ID, fall through to mask VLAN priority */
1526 fdirm
|= IXGBE_FDIRM_VLANID
;
1528 /* mask VLAN priority */
1529 fdirm
|= IXGBE_FDIRM_VLANP
;
1532 /* mask VLAN ID only, fall through */
1533 fdirm
|= IXGBE_FDIRM_VLANID
;
1535 /* no VLAN fields masked */
1538 hw_dbg(hw
, " Error on VLAN mask\n");
1539 return IXGBE_ERR_CONFIG
;
1542 switch (input_mask
->formatted
.flex_bytes
& 0xFFFF) {
1544 /* Mask Flex Bytes, fall through */
1545 fdirm
|= IXGBE_FDIRM_FLEX
;
1549 hw_dbg(hw
, " Error on flexible byte mask\n");
1550 return IXGBE_ERR_CONFIG
;
1553 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1554 IXGBE_WRITE_REG(hw
, IXGBE_FDIRM
, fdirm
);
1556 /* store the TCP/UDP port masks, bit reversed from port layout */
1557 fdirtcpm
= ixgbe_get_fdirtcpm_82599(input_mask
);
1559 /* write both the same so that UDP and TCP use the same mask */
1560 IXGBE_WRITE_REG(hw
, IXGBE_FDIRTCPM
, ~fdirtcpm
);
1561 IXGBE_WRITE_REG(hw
, IXGBE_FDIRUDPM
, ~fdirtcpm
);
1563 /* store source and destination IP masks (big-enian) */
1564 IXGBE_WRITE_REG_BE32(hw
, IXGBE_FDIRSIP4M
,
1565 ~input_mask
->formatted
.src_ip
[0]);
1566 IXGBE_WRITE_REG_BE32(hw
, IXGBE_FDIRDIP4M
,
1567 ~input_mask
->formatted
.dst_ip
[0]);
1572 s32
ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw
*hw
,
1573 union ixgbe_atr_input
*input
,
1574 u16 soft_id
, u8 queue
)
1576 u32 fdirport
, fdirvlan
, fdirhash
, fdircmd
;
1578 /* currently IPv6 is not supported, must be programmed with 0 */
1579 IXGBE_WRITE_REG_BE32(hw
, IXGBE_FDIRSIPv6(0),
1580 input
->formatted
.src_ip
[0]);
1581 IXGBE_WRITE_REG_BE32(hw
, IXGBE_FDIRSIPv6(1),
1582 input
->formatted
.src_ip
[1]);
1583 IXGBE_WRITE_REG_BE32(hw
, IXGBE_FDIRSIPv6(2),
1584 input
->formatted
.src_ip
[2]);
1586 /* record the source address (big-endian) */
1587 IXGBE_WRITE_REG_BE32(hw
, IXGBE_FDIRIPSA
, input
->formatted
.src_ip
[0]);
1589 /* record the first 32 bits of the destination address (big-endian) */
1590 IXGBE_WRITE_REG_BE32(hw
, IXGBE_FDIRIPDA
, input
->formatted
.dst_ip
[0]);
1592 /* record source and destination port (little-endian)*/
1593 fdirport
= ntohs(input
->formatted
.dst_port
);
1594 fdirport
<<= IXGBE_FDIRPORT_DESTINATION_SHIFT
;
1595 fdirport
|= ntohs(input
->formatted
.src_port
);
1596 IXGBE_WRITE_REG(hw
, IXGBE_FDIRPORT
, fdirport
);
1598 /* record vlan (little-endian) and flex_bytes(big-endian) */
1599 fdirvlan
= IXGBE_STORE_AS_BE16(input
->formatted
.flex_bytes
);
1600 fdirvlan
<<= IXGBE_FDIRVLAN_FLEX_SHIFT
;
1601 fdirvlan
|= ntohs(input
->formatted
.vlan_id
);
1602 IXGBE_WRITE_REG(hw
, IXGBE_FDIRVLAN
, fdirvlan
);
1604 /* configure FDIRHASH register */
1605 fdirhash
= input
->formatted
.bkt_hash
;
1606 fdirhash
|= soft_id
<< IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT
;
1607 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHASH
, fdirhash
);
1610 * flush all previous writes to make certain registers are
1611 * programmed prior to issuing the command
1613 IXGBE_WRITE_FLUSH(hw
);
1615 /* configure FDIRCMD register */
1616 fdircmd
= IXGBE_FDIRCMD_CMD_ADD_FLOW
| IXGBE_FDIRCMD_FILTER_UPDATE
|
1617 IXGBE_FDIRCMD_LAST
| IXGBE_FDIRCMD_QUEUE_EN
;
1618 if (queue
== IXGBE_FDIR_DROP_QUEUE
)
1619 fdircmd
|= IXGBE_FDIRCMD_DROP
;
1620 fdircmd
|= input
->formatted
.flow_type
<< IXGBE_FDIRCMD_FLOW_TYPE_SHIFT
;
1621 fdircmd
|= (u32
)queue
<< IXGBE_FDIRCMD_RX_QUEUE_SHIFT
;
1622 fdircmd
|= (u32
)input
->formatted
.vm_pool
<< IXGBE_FDIRCMD_VT_POOL_SHIFT
;
1624 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCMD
, fdircmd
);
1629 s32
ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw
*hw
,
1630 union ixgbe_atr_input
*input
,
1638 /* configure FDIRHASH register */
1639 fdirhash
= input
->formatted
.bkt_hash
;
1640 fdirhash
|= soft_id
<< IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT
;
1641 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHASH
, fdirhash
);
1643 /* flush hash to HW */
1644 IXGBE_WRITE_FLUSH(hw
);
1646 /* Query if filter is present */
1647 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCMD
, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT
);
1649 for (retry_count
= 10; retry_count
; retry_count
--) {
1650 /* allow 10us for query to process */
1652 /* verify query completed successfully */
1653 fdircmd
= IXGBE_READ_REG(hw
, IXGBE_FDIRCMD
);
1654 if (!(fdircmd
& IXGBE_FDIRCMD_CMD_MASK
))
1659 err
= IXGBE_ERR_FDIR_REINIT_FAILED
;
1661 /* if filter exists in hardware then remove it */
1662 if (fdircmd
& IXGBE_FDIRCMD_FILTER_VALID
) {
1663 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHASH
, fdirhash
);
1664 IXGBE_WRITE_FLUSH(hw
);
1665 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCMD
,
1666 IXGBE_FDIRCMD_CMD_REMOVE_FLOW
);
1673 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1674 * @hw: pointer to hardware structure
1675 * @reg: analog register to read
1678 * Performs read operation to Omer analog register specified.
1680 static s32
ixgbe_read_analog_reg8_82599(struct ixgbe_hw
*hw
, u32 reg
, u8
*val
)
1684 IXGBE_WRITE_REG(hw
, IXGBE_CORECTL
, IXGBE_CORECTL_WRITE_CMD
|
1686 IXGBE_WRITE_FLUSH(hw
);
1688 core_ctl
= IXGBE_READ_REG(hw
, IXGBE_CORECTL
);
1689 *val
= (u8
)core_ctl
;
1695 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1696 * @hw: pointer to hardware structure
1697 * @reg: atlas register to write
1698 * @val: value to write
1700 * Performs write operation to Omer analog register specified.
1702 static s32
ixgbe_write_analog_reg8_82599(struct ixgbe_hw
*hw
, u32 reg
, u8 val
)
1706 core_ctl
= (reg
<< 8) | val
;
1707 IXGBE_WRITE_REG(hw
, IXGBE_CORECTL
, core_ctl
);
1708 IXGBE_WRITE_FLUSH(hw
);
1715 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1716 * @hw: pointer to hardware structure
1718 * Starts the hardware using the generic start_hw function
1719 * and the generation start_hw function.
1720 * Then performs revision-specific operations, if any.
1722 static s32
ixgbe_start_hw_82599(struct ixgbe_hw
*hw
)
1726 ret_val
= ixgbe_start_hw_generic(hw
);
1730 ret_val
= ixgbe_start_hw_gen2(hw
);
1734 /* We need to run link autotry after the driver loads */
1735 hw
->mac
.autotry_restart
= true;
1736 hw
->mac
.rx_pb_size
= IXGBE_82599_RX_PB_SIZE
;
1739 ret_val
= ixgbe_verify_fw_version_82599(hw
);
1745 * ixgbe_identify_phy_82599 - Get physical layer module
1746 * @hw: pointer to hardware structure
1748 * Determines the physical layer module found on the current adapter.
1749 * If PHY already detected, maintains current PHY type in hw struct,
1750 * otherwise executes the PHY detection routine.
1752 static s32
ixgbe_identify_phy_82599(struct ixgbe_hw
*hw
)
1754 s32 status
= IXGBE_ERR_PHY_ADDR_INVALID
;
1756 /* Detect PHY if not unknown - returns success if already detected. */
1757 status
= ixgbe_identify_phy_generic(hw
);
1759 /* 82599 10GBASE-T requires an external PHY */
1760 if (hw
->mac
.ops
.get_media_type(hw
) == ixgbe_media_type_copper
)
1763 status
= ixgbe_identify_sfp_module_generic(hw
);
1766 /* Set PHY type none if no PHY detected */
1767 if (hw
->phy
.type
== ixgbe_phy_unknown
) {
1768 hw
->phy
.type
= ixgbe_phy_none
;
1772 /* Return error if SFP module has been detected but is not supported */
1773 if (hw
->phy
.type
== ixgbe_phy_sfp_unsupported
)
1774 status
= IXGBE_ERR_SFP_NOT_SUPPORTED
;
1781 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1782 * @hw: pointer to hardware structure
1784 * Determines physical layer capabilities of the current configuration.
1786 static u32
ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw
*hw
)
1788 u32 physical_layer
= IXGBE_PHYSICAL_LAYER_UNKNOWN
;
1789 u32 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
1790 u32 autoc2
= IXGBE_READ_REG(hw
, IXGBE_AUTOC2
);
1791 u32 pma_pmd_10g_serial
= autoc2
& IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK
;
1792 u32 pma_pmd_10g_parallel
= autoc
& IXGBE_AUTOC_10G_PMA_PMD_MASK
;
1793 u32 pma_pmd_1g
= autoc
& IXGBE_AUTOC_1G_PMA_PMD_MASK
;
1794 u16 ext_ability
= 0;
1795 u8 comp_codes_10g
= 0;
1796 u8 comp_codes_1g
= 0;
1798 hw
->phy
.ops
.identify(hw
);
1800 switch (hw
->phy
.type
) {
1803 case ixgbe_phy_cu_unknown
:
1804 hw
->phy
.ops
.read_reg(hw
, MDIO_PMA_EXTABLE
, MDIO_MMD_PMAPMD
,
1806 if (ext_ability
& MDIO_PMA_EXTABLE_10GBT
)
1807 physical_layer
|= IXGBE_PHYSICAL_LAYER_10GBASE_T
;
1808 if (ext_ability
& MDIO_PMA_EXTABLE_1000BT
)
1809 physical_layer
|= IXGBE_PHYSICAL_LAYER_1000BASE_T
;
1810 if (ext_ability
& MDIO_PMA_EXTABLE_100BTX
)
1811 physical_layer
|= IXGBE_PHYSICAL_LAYER_100BASE_TX
;
1817 switch (autoc
& IXGBE_AUTOC_LMS_MASK
) {
1818 case IXGBE_AUTOC_LMS_1G_AN
:
1819 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN
:
1820 if (pma_pmd_1g
== IXGBE_AUTOC_1G_KX_BX
) {
1821 physical_layer
= IXGBE_PHYSICAL_LAYER_1000BASE_KX
|
1822 IXGBE_PHYSICAL_LAYER_1000BASE_BX
;
1825 /* SFI mode so read SFP module */
1828 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN
:
1829 if (pma_pmd_10g_parallel
== IXGBE_AUTOC_10G_CX4
)
1830 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_CX4
;
1831 else if (pma_pmd_10g_parallel
== IXGBE_AUTOC_10G_KX4
)
1832 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_KX4
;
1833 else if (pma_pmd_10g_parallel
== IXGBE_AUTOC_10G_XAUI
)
1834 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_XAUI
;
1837 case IXGBE_AUTOC_LMS_10G_SERIAL
:
1838 if (pma_pmd_10g_serial
== IXGBE_AUTOC2_10G_KR
) {
1839 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_KR
;
1841 } else if (pma_pmd_10g_serial
== IXGBE_AUTOC2_10G_SFI
)
1844 case IXGBE_AUTOC_LMS_KX4_KX_KR
:
1845 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
:
1846 if (autoc
& IXGBE_AUTOC_KX_SUPP
)
1847 physical_layer
|= IXGBE_PHYSICAL_LAYER_1000BASE_KX
;
1848 if (autoc
& IXGBE_AUTOC_KX4_SUPP
)
1849 physical_layer
|= IXGBE_PHYSICAL_LAYER_10GBASE_KX4
;
1850 if (autoc
& IXGBE_AUTOC_KR_SUPP
)
1851 physical_layer
|= IXGBE_PHYSICAL_LAYER_10GBASE_KR
;
1860 /* SFP check must be done last since DA modules are sometimes used to
1861 * test KR mode - we need to id KR mode correctly before SFP module.
1862 * Call identify_sfp because the pluggable module may have changed */
1863 hw
->phy
.ops
.identify_sfp(hw
);
1864 if (hw
->phy
.sfp_type
== ixgbe_sfp_type_not_present
)
1867 switch (hw
->phy
.type
) {
1868 case ixgbe_phy_sfp_passive_tyco
:
1869 case ixgbe_phy_sfp_passive_unknown
:
1870 physical_layer
= IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU
;
1872 case ixgbe_phy_sfp_ftl_active
:
1873 case ixgbe_phy_sfp_active_unknown
:
1874 physical_layer
= IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA
;
1876 case ixgbe_phy_sfp_avago
:
1877 case ixgbe_phy_sfp_ftl
:
1878 case ixgbe_phy_sfp_intel
:
1879 case ixgbe_phy_sfp_unknown
:
1880 hw
->phy
.ops
.read_i2c_eeprom(hw
,
1881 IXGBE_SFF_1GBE_COMP_CODES
, &comp_codes_1g
);
1882 hw
->phy
.ops
.read_i2c_eeprom(hw
,
1883 IXGBE_SFF_10GBE_COMP_CODES
, &comp_codes_10g
);
1884 if (comp_codes_10g
& IXGBE_SFF_10GBASESR_CAPABLE
)
1885 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_SR
;
1886 else if (comp_codes_10g
& IXGBE_SFF_10GBASELR_CAPABLE
)
1887 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_LR
;
1888 else if (comp_codes_1g
& IXGBE_SFF_1GBASET_CAPABLE
)
1889 physical_layer
= IXGBE_PHYSICAL_LAYER_1000BASE_T
;
1896 return physical_layer
;
1900 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1901 * @hw: pointer to hardware structure
1902 * @regval: register value to write to RXCTRL
1904 * Enables the Rx DMA unit for 82599
1906 static s32
ixgbe_enable_rx_dma_82599(struct ixgbe_hw
*hw
, u32 regval
)
1908 #define IXGBE_MAX_SECRX_POLL 30
1913 * Workaround for 82599 silicon errata when enabling the Rx datapath.
1914 * If traffic is incoming before we enable the Rx unit, it could hang
1915 * the Rx DMA unit. Therefore, make sure the security engine is
1916 * completely disabled prior to enabling the Rx unit.
1918 secrxreg
= IXGBE_READ_REG(hw
, IXGBE_SECRXCTRL
);
1919 secrxreg
|= IXGBE_SECRXCTRL_RX_DIS
;
1920 IXGBE_WRITE_REG(hw
, IXGBE_SECRXCTRL
, secrxreg
);
1921 for (i
= 0; i
< IXGBE_MAX_SECRX_POLL
; i
++) {
1922 secrxreg
= IXGBE_READ_REG(hw
, IXGBE_SECRXSTAT
);
1923 if (secrxreg
& IXGBE_SECRXSTAT_SECRX_RDY
)
1926 /* Use interrupt-safe sleep just in case */
1930 /* For informational purposes only */
1931 if (i
>= IXGBE_MAX_SECRX_POLL
)
1932 hw_dbg(hw
, "Rx unit being enabled before security "
1933 "path fully disabled. Continuing with init.\n");
1935 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, regval
);
1936 secrxreg
= IXGBE_READ_REG(hw
, IXGBE_SECRXCTRL
);
1937 secrxreg
&= ~IXGBE_SECRXCTRL_RX_DIS
;
1938 IXGBE_WRITE_REG(hw
, IXGBE_SECRXCTRL
, secrxreg
);
1939 IXGBE_WRITE_FLUSH(hw
);
1945 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
1946 * @hw: pointer to hardware structure
1948 * Verifies that installed the firmware version is 0.6 or higher
1949 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
1951 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
1952 * if the FW version is not supported.
1954 static s32
ixgbe_verify_fw_version_82599(struct ixgbe_hw
*hw
)
1956 s32 status
= IXGBE_ERR_EEPROM_VERSION
;
1957 u16 fw_offset
, fw_ptp_cfg_offset
;
1960 /* firmware check is only necessary for SFI devices */
1961 if (hw
->phy
.media_type
!= ixgbe_media_type_fiber
) {
1963 goto fw_version_out
;
1966 /* get the offset to the Firmware Module block */
1967 hw
->eeprom
.ops
.read(hw
, IXGBE_FW_PTR
, &fw_offset
);
1969 if ((fw_offset
== 0) || (fw_offset
== 0xFFFF))
1970 goto fw_version_out
;
1972 /* get the offset to the Pass Through Patch Configuration block */
1973 hw
->eeprom
.ops
.read(hw
, (fw_offset
+
1974 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR
),
1975 &fw_ptp_cfg_offset
);
1977 if ((fw_ptp_cfg_offset
== 0) || (fw_ptp_cfg_offset
== 0xFFFF))
1978 goto fw_version_out
;
1980 /* get the firmware version */
1981 hw
->eeprom
.ops
.read(hw
, (fw_ptp_cfg_offset
+
1982 IXGBE_FW_PATCH_VERSION_4
),
1985 if (fw_version
> 0x5)
1993 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
1994 * @hw: pointer to hardware structure
1996 * Returns true if the LESM FW module is present and enabled. Otherwise
1997 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
1999 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw
*hw
)
2001 bool lesm_enabled
= false;
2002 u16 fw_offset
, fw_lesm_param_offset
, fw_lesm_state
;
2005 /* get the offset to the Firmware Module block */
2006 status
= hw
->eeprom
.ops
.read(hw
, IXGBE_FW_PTR
, &fw_offset
);
2008 if ((status
!= 0) ||
2009 (fw_offset
== 0) || (fw_offset
== 0xFFFF))
2012 /* get the offset to the LESM Parameters block */
2013 status
= hw
->eeprom
.ops
.read(hw
, (fw_offset
+
2014 IXGBE_FW_LESM_PARAMETERS_PTR
),
2015 &fw_lesm_param_offset
);
2017 if ((status
!= 0) ||
2018 (fw_lesm_param_offset
== 0) || (fw_lesm_param_offset
== 0xFFFF))
2021 /* get the lesm state word */
2022 status
= hw
->eeprom
.ops
.read(hw
, (fw_lesm_param_offset
+
2023 IXGBE_FW_LESM_STATE_1
),
2026 if ((status
== 0) &&
2027 (fw_lesm_state
& IXGBE_FW_LESM_STATE_ENABLED
))
2028 lesm_enabled
= true;
2031 return lesm_enabled
;
2035 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2036 * fastest available method
2038 * @hw: pointer to hardware structure
2039 * @offset: offset of word in EEPROM to read
2040 * @words: number of words
2041 * @data: word(s) read from the EEPROM
2043 * Retrieves 16 bit word(s) read from EEPROM
2045 static s32
ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw
*hw
, u16 offset
,
2046 u16 words
, u16
*data
)
2048 struct ixgbe_eeprom_info
*eeprom
= &hw
->eeprom
;
2049 s32 ret_val
= IXGBE_ERR_CONFIG
;
2052 * If EEPROM is detected and can be addressed using 14 bits,
2053 * use EERD otherwise use bit bang
2055 if ((eeprom
->type
== ixgbe_eeprom_spi
) &&
2056 (offset
+ (words
- 1) <= IXGBE_EERD_MAX_ADDR
))
2057 ret_val
= ixgbe_read_eerd_buffer_generic(hw
, offset
, words
,
2060 ret_val
= ixgbe_read_eeprom_buffer_bit_bang_generic(hw
, offset
,
2068 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2069 * fastest available method
2071 * @hw: pointer to hardware structure
2072 * @offset: offset of word in the EEPROM to read
2073 * @data: word read from the EEPROM
2075 * Reads a 16 bit word from the EEPROM
2077 static s32
ixgbe_read_eeprom_82599(struct ixgbe_hw
*hw
,
2078 u16 offset
, u16
*data
)
2080 struct ixgbe_eeprom_info
*eeprom
= &hw
->eeprom
;
2081 s32 ret_val
= IXGBE_ERR_CONFIG
;
2084 * If EEPROM is detected and can be addressed using 14 bits,
2085 * use EERD otherwise use bit bang
2087 if ((eeprom
->type
== ixgbe_eeprom_spi
) &&
2088 (offset
<= IXGBE_EERD_MAX_ADDR
))
2089 ret_val
= ixgbe_read_eerd_generic(hw
, offset
, data
);
2091 ret_val
= ixgbe_read_eeprom_bit_bang_generic(hw
, offset
, data
);
2096 static struct ixgbe_mac_operations mac_ops_82599
= {
2097 .init_hw
= &ixgbe_init_hw_generic
,
2098 .reset_hw
= &ixgbe_reset_hw_82599
,
2099 .start_hw
= &ixgbe_start_hw_82599
,
2100 .clear_hw_cntrs
= &ixgbe_clear_hw_cntrs_generic
,
2101 .get_media_type
= &ixgbe_get_media_type_82599
,
2102 .get_supported_physical_layer
= &ixgbe_get_supported_physical_layer_82599
,
2103 .enable_rx_dma
= &ixgbe_enable_rx_dma_82599
,
2104 .get_mac_addr
= &ixgbe_get_mac_addr_generic
,
2105 .get_san_mac_addr
= &ixgbe_get_san_mac_addr_generic
,
2106 .get_device_caps
= &ixgbe_get_device_caps_generic
,
2107 .get_wwn_prefix
= &ixgbe_get_wwn_prefix_generic
,
2108 .stop_adapter
= &ixgbe_stop_adapter_generic
,
2109 .get_bus_info
= &ixgbe_get_bus_info_generic
,
2110 .set_lan_id
= &ixgbe_set_lan_id_multi_port_pcie
,
2111 .read_analog_reg8
= &ixgbe_read_analog_reg8_82599
,
2112 .write_analog_reg8
= &ixgbe_write_analog_reg8_82599
,
2113 .setup_link
= &ixgbe_setup_mac_link_82599
,
2114 .set_rxpba
= &ixgbe_set_rxpba_generic
,
2115 .check_link
= &ixgbe_check_mac_link_generic
,
2116 .get_link_capabilities
= &ixgbe_get_link_capabilities_82599
,
2117 .led_on
= &ixgbe_led_on_generic
,
2118 .led_off
= &ixgbe_led_off_generic
,
2119 .blink_led_start
= &ixgbe_blink_led_start_generic
,
2120 .blink_led_stop
= &ixgbe_blink_led_stop_generic
,
2121 .set_rar
= &ixgbe_set_rar_generic
,
2122 .clear_rar
= &ixgbe_clear_rar_generic
,
2123 .set_vmdq
= &ixgbe_set_vmdq_generic
,
2124 .clear_vmdq
= &ixgbe_clear_vmdq_generic
,
2125 .init_rx_addrs
= &ixgbe_init_rx_addrs_generic
,
2126 .update_mc_addr_list
= &ixgbe_update_mc_addr_list_generic
,
2127 .enable_mc
= &ixgbe_enable_mc_generic
,
2128 .disable_mc
= &ixgbe_disable_mc_generic
,
2129 .clear_vfta
= &ixgbe_clear_vfta_generic
,
2130 .set_vfta
= &ixgbe_set_vfta_generic
,
2131 .fc_enable
= &ixgbe_fc_enable_generic
,
2132 .set_fw_drv_ver
= &ixgbe_set_fw_drv_ver_generic
,
2133 .init_uta_tables
= &ixgbe_init_uta_tables_generic
,
2134 .setup_sfp
= &ixgbe_setup_sfp_modules_82599
,
2135 .set_mac_anti_spoofing
= &ixgbe_set_mac_anti_spoofing
,
2136 .set_vlan_anti_spoofing
= &ixgbe_set_vlan_anti_spoofing
,
2137 .acquire_swfw_sync
= &ixgbe_acquire_swfw_sync
,
2138 .release_swfw_sync
= &ixgbe_release_swfw_sync
,
2142 static struct ixgbe_eeprom_operations eeprom_ops_82599
= {
2143 .init_params
= &ixgbe_init_eeprom_params_generic
,
2144 .read
= &ixgbe_read_eeprom_82599
,
2145 .read_buffer
= &ixgbe_read_eeprom_buffer_82599
,
2146 .write
= &ixgbe_write_eeprom_generic
,
2147 .write_buffer
= &ixgbe_write_eeprom_buffer_bit_bang_generic
,
2148 .calc_checksum
= &ixgbe_calc_eeprom_checksum_generic
,
2149 .validate_checksum
= &ixgbe_validate_eeprom_checksum_generic
,
2150 .update_checksum
= &ixgbe_update_eeprom_checksum_generic
,
2153 static struct ixgbe_phy_operations phy_ops_82599
= {
2154 .identify
= &ixgbe_identify_phy_82599
,
2155 .identify_sfp
= &ixgbe_identify_sfp_module_generic
,
2156 .init
= &ixgbe_init_phy_ops_82599
,
2157 .reset
= &ixgbe_reset_phy_generic
,
2158 .read_reg
= &ixgbe_read_phy_reg_generic
,
2159 .write_reg
= &ixgbe_write_phy_reg_generic
,
2160 .setup_link
= &ixgbe_setup_phy_link_generic
,
2161 .setup_link_speed
= &ixgbe_setup_phy_link_speed_generic
,
2162 .read_i2c_byte
= &ixgbe_read_i2c_byte_generic
,
2163 .write_i2c_byte
= &ixgbe_write_i2c_byte_generic
,
2164 .read_i2c_eeprom
= &ixgbe_read_i2c_eeprom_generic
,
2165 .write_i2c_eeprom
= &ixgbe_write_i2c_eeprom_generic
,
2166 .check_overtemp
= &ixgbe_tn_check_overtemp
,
2169 struct ixgbe_info ixgbe_82599_info
= {
2170 .mac
= ixgbe_mac_82599EB
,
2171 .get_invariants
= &ixgbe_get_invariants_82599
,
2172 .mac_ops
= &mac_ops_82599
,
2173 .eeprom_ops
= &eeprom_ops_82599
,
2174 .phy_ops
= &phy_ops_82599
,
2175 .mbx_ops
= &mbx_ops_generic
,