drivers/net/ethernet/mellanox/mlx4/mlx4_en.h

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34 #ifndef _MLX4_EN_H_
  35 #define _MLX4_EN_H_
  36
  37 #include <linux/bitops.h>
  38 #include <linux/compiler.h>
  39 #include <linux/list.h>
  40 #include <linux/mutex.h>
  41 #include <linux/netdevice.h>
  42 #include <linux/if_vlan.h>
  43
  44 #include <linux/mlx4/device.h>
  45 #include <linux/mlx4/qp.h>
  46 #include <linux/mlx4/cq.h>
  47 #include <linux/mlx4/srq.h>
  48 #include <linux/mlx4/doorbell.h>
  49 #include <linux/mlx4/cmd.h>
  50
  51 #include "en_port.h"
  52
  53 #define DRV_NAME        "mlx4_en"
  54 #define DRV_VERSION     "1.5.4.1"
  55 #define DRV_RELDATE     "March 2011"
  56
  57 #define MLX4_EN_MSG_LEVEL       (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
  58
  59 /*
  60  * Device constants
  61  */
  62
  63
  64 #define MLX4_EN_PAGE_SHIFT      12
  65 #define MLX4_EN_PAGE_SIZE       (1 << MLX4_EN_PAGE_SHIFT)
  66 #define MAX_RX_RINGS            16
  67 #define MIN_RX_RINGS            4
  68 #define TXBB_SIZE               64
  69 #define HEADROOM                (2048 / TXBB_SIZE + 1)
  70 #define STAMP_STRIDE            64
  71 #define STAMP_DWORDS            (STAMP_STRIDE / 4)
  72 #define STAMP_SHIFT             31
  73 #define STAMP_VAL               0x7fffffff
  74 #define STATS_DELAY             (HZ / 4)
  75
  76 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */
  77 #define MAX_DESC_SIZE           512
  78 #define MAX_DESC_TXBBS          (MAX_DESC_SIZE / TXBB_SIZE)
  79
  80 /*
  81  * OS related constants and tunables
  82  */
  83
  84 #define MLX4_EN_WATCHDOG_TIMEOUT        (15 * HZ)
  85
  86 #define MLX4_EN_ALLOC_ORDER     2
  87 #define MLX4_EN_ALLOC_SIZE      (PAGE_SIZE << MLX4_EN_ALLOC_ORDER)
  88
  89 #define MLX4_EN_MAX_LRO_DESCRIPTORS     32
  90
  91 /* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU
  92  * and 4K allocations) */
  93 enum {
  94         FRAG_SZ0 = 512 - NET_IP_ALIGN,
  95         FRAG_SZ1 = 1024,
  96         FRAG_SZ2 = 4096,
  97         FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
  98 };
  99 #define MLX4_EN_MAX_RX_FRAGS    4
 100
 101 /* Maximum ring sizes */
 102 #define MLX4_EN_MAX_TX_SIZE     8192
 103 #define MLX4_EN_MAX_RX_SIZE     8192
 104
 105 /* Minimum ring size for our page-allocation sceme to work */
 106 #define MLX4_EN_MIN_RX_SIZE     (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
 107 #define MLX4_EN_MIN_TX_SIZE     (4096 / TXBB_SIZE)
 108
 109 #define MLX4_EN_SMALL_PKT_SIZE          64
 110 #define MLX4_EN_NUM_TX_RINGS            8
 111 #define MLX4_EN_NUM_PPP_RINGS           8
 112 #define MAX_TX_RINGS                    (MLX4_EN_NUM_TX_RINGS + MLX4_EN_NUM_PPP_RINGS)
 113 #define MLX4_EN_DEF_TX_RING_SIZE        512
 114 #define MLX4_EN_DEF_RX_RING_SIZE        1024
 115
 116 /* Target number of packets to coalesce with interrupt moderation */
 117 #define MLX4_EN_RX_COAL_TARGET  44
 118 #define MLX4_EN_RX_COAL_TIME    0x10
 119
 120 #define MLX4_EN_TX_COAL_PKTS    5
 121 #define MLX4_EN_TX_COAL_TIME    0x80
 122
 123 #define MLX4_EN_RX_RATE_LOW             400000
 124 #define MLX4_EN_RX_COAL_TIME_LOW        0
 125 #define MLX4_EN_RX_RATE_HIGH            450000
 126 #define MLX4_EN_RX_COAL_TIME_HIGH       128
 127 #define MLX4_EN_RX_SIZE_THRESH          1024
 128 #define MLX4_EN_RX_RATE_THRESH          (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
 129 #define MLX4_EN_SAMPLE_INTERVAL         0
 130 #define MLX4_EN_AVG_PKT_SMALL           256
 131
 132 #define MLX4_EN_AUTO_CONF       0xffff
 133
 134 #define MLX4_EN_DEF_RX_PAUSE    1
 135 #define MLX4_EN_DEF_TX_PAUSE    1
 136
 137 /* Interval between successive polls in the Tx routine when polling is used
 138    instead of interrupts (in per-core Tx rings) - should be power of 2 */
 139 #define MLX4_EN_TX_POLL_MODER   16
 140 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
 141
 142 #define ETH_LLC_SNAP_SIZE       8
 143
 144 #define SMALL_PACKET_SIZE      (256 - NET_IP_ALIGN)
 145 #define HEADER_COPY_SIZE       (128 - NET_IP_ALIGN)
 146 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
 147
 148 #define MLX4_EN_MIN_MTU         46
 149 #define ETH_BCAST               0xffffffffffffULL
 150
 151 #define MLX4_EN_LOOPBACK_RETRIES        5
 152 #define MLX4_EN_LOOPBACK_TIMEOUT        100
 153
 154 #ifdef MLX4_EN_PERF_STAT
 155 /* Number of samples to 'average' */
 156 #define AVG_SIZE                        128
 157 #define AVG_FACTOR                      1024
 158 #define NUM_PERF_STATS                  NUM_PERF_COUNTERS
 159
 160 #define INC_PERF_COUNTER(cnt)           (++(cnt))
 161 #define ADD_PERF_COUNTER(cnt, add)      ((cnt) += (add))
 162 #define AVG_PERF_COUNTER(cnt, sample) \
 163         ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
 164 #define GET_PERF_COUNTER(cnt)           (cnt)
 165 #define GET_AVG_PERF_COUNTER(cnt)       ((cnt) / AVG_FACTOR)
 166
 167 #else
 168
 169 #define NUM_PERF_STATS                  0
 170 #define INC_PERF_COUNTER(cnt)           do {} while (0)
 171 #define ADD_PERF_COUNTER(cnt, add)      do {} while (0)
 172 #define AVG_PERF_COUNTER(cnt, sample)   do {} while (0)
 173 #define GET_PERF_COUNTER(cnt)           (0)
 174 #define GET_AVG_PERF_COUNTER(cnt)       (0)
 175 #endif /* MLX4_EN_PERF_STAT */
 176
 177 /*
 178  * Configurables
 179  */
 180
 181 enum cq_type {
 182         RX = 0,
 183         TX = 1,
 184 };
 185
 186
 187 /*
 188  * Useful macros
 189  */
 190 #define ROUNDUP_LOG2(x)         ilog2(roundup_pow_of_two(x))
 191 #define XNOR(x, y)              (!(x) == !(y))
 192 #define ILLEGAL_MAC(addr)       (addr == 0xffffffffffffULL || addr == 0x0)
 193
 194
 195 struct mlx4_en_tx_info {
 196         struct sk_buff *skb;
 197         u32 nr_txbb;
 198         u8 linear;
 199         u8 data_offset;
 200         u8 inl;
 201 };
 202
 203
 204 #define MLX4_EN_BIT_DESC_OWN    0x80000000
 205 #define CTRL_SIZE       sizeof(struct mlx4_wqe_ctrl_seg)
 206 #define MLX4_EN_MEMTYPE_PAD     0x100
 207 #define DS_SIZE         sizeof(struct mlx4_wqe_data_seg)
 208
 209
 210 struct mlx4_en_tx_desc {
 211         struct mlx4_wqe_ctrl_seg ctrl;
 212         union {
 213                 struct mlx4_wqe_data_seg data; /* at least one data segment */
 214                 struct mlx4_wqe_lso_seg lso;
 215                 struct mlx4_wqe_inline_seg inl;
 216         };
 217 };
 218
 219 #define MLX4_EN_USE_SRQ         0x01000000
 220
 221 #define MLX4_EN_CX3_LOW_ID      0x1000
 222 #define MLX4_EN_CX3_HIGH_ID     0x1005
 223
 224 struct mlx4_en_rx_alloc {
 225         struct page *page;
 226         u16 offset;
 227 };
 228
 229 struct mlx4_en_tx_ring {
 230         struct mlx4_hwq_resources wqres;
 231         u32 size ; /* number of TXBBs */
 232         u32 size_mask;
 233         u16 stride;
 234         u16 cqn;        /* index of port CQ associated with this ring */
 235         u32 prod;
 236         u32 cons;
 237         u32 buf_size;
 238         u32 doorbell_qpn;
 239         void *buf;
 240         u16 poll_cnt;
 241         int blocked;
 242         struct mlx4_en_tx_info *tx_info;
 243         u8 *bounce_buf;
 244         u32 last_nr_txbb;
 245         struct mlx4_qp qp;
 246         struct mlx4_qp_context context;
 247         int qpn;
 248         enum mlx4_qp_state qp_state;
 249         struct mlx4_srq dummy;
 250         unsigned long bytes;
 251         unsigned long packets;
 252         spinlock_t comp_lock;
 253         struct mlx4_bf bf;
 254         bool bf_enabled;
 255 };
 256
 257 struct mlx4_en_rx_desc {
 258         /* actual number of entries depends on rx ring stride */
 259         struct mlx4_wqe_data_seg data[0];
 260 };
 261
 262 struct mlx4_en_rx_ring {
 263         struct mlx4_hwq_resources wqres;
 264         struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
 265         u32 size ;      /* number of Rx descs*/
 266         u32 actual_size;
 267         u32 size_mask;
 268         u16 stride;
 269         u16 log_stride;
 270         u16 cqn;        /* index of port CQ associated with this ring */
 271         u32 prod;
 272         u32 cons;
 273         u32 buf_size;
 274         void *buf;
 275         void *rx_info;
 276         unsigned long bytes;
 277         unsigned long packets;
 278 };
 279
 280
 281 static inline int mlx4_en_can_lro(__be16 status)
 282 {
 283         return (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4       |
 284                                      MLX4_CQE_STATUS_IPV4F      |
 285                                      MLX4_CQE_STATUS_IPV6       |
 286                                      MLX4_CQE_STATUS_IPV4OPT    |
 287                                      MLX4_CQE_STATUS_TCP        |
 288                                      MLX4_CQE_STATUS_UDP        |
 289                                      MLX4_CQE_STATUS_IPOK)) ==
 290                 cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
 291                             MLX4_CQE_STATUS_IPOK |
 292                             MLX4_CQE_STATUS_TCP);
 293 }
 294
 295 struct mlx4_en_cq {
 296         struct mlx4_cq          mcq;
 297         struct mlx4_hwq_resources wqres;
 298         int                     ring;
 299         spinlock_t              lock;
 300         struct net_device      *dev;
 301         struct napi_struct      napi;
 302         /* Per-core Tx cq processing support */
 303         struct timer_list timer;
 304         int size;
 305         int buf_size;
 306         unsigned vector;
 307         enum cq_type is_tx;
 308         u16 moder_time;
 309         u16 moder_cnt;
 310         struct mlx4_cqe *buf;
 311 #define MLX4_EN_OPCODE_ERROR    0x1e
 312 };
 313
 314 struct mlx4_en_port_profile {
 315         u32 flags;
 316         u32 tx_ring_num;
 317         u32 rx_ring_num;
 318         u32 tx_ring_size;
 319         u32 rx_ring_size;
 320         u8 rx_pause;
 321         u8 rx_ppp;
 322         u8 tx_pause;
 323         u8 tx_ppp;
 324 };
 325
 326 struct mlx4_en_profile {
 327         int rss_xor;
 328         int tcp_rss;
 329         int udp_rss;
 330         u8 rss_mask;
 331         u32 active_ports;
 332         u32 small_pkt_int;
 333         u8 no_reset;
 334         struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
 335 };
 336
 337 struct mlx4_en_dev {
 338         struct mlx4_dev         *dev;
 339         struct pci_dev          *pdev;
 340         struct mutex            state_lock;
 341         struct net_device       *pndev[MLX4_MAX_PORTS + 1];
 342         u32                     port_cnt;
 343         bool                    device_up;
 344         struct mlx4_en_profile  profile;
 345         u32                     LSO_support;
 346         struct workqueue_struct *workqueue;
 347         struct device           *dma_device;
 348         void __iomem            *uar_map;
 349         struct mlx4_uar         priv_uar;
 350         struct mlx4_mr          mr;
 351         u32                     priv_pdn;
 352         spinlock_t              uar_lock;
 353         u8                      mac_removed[MLX4_MAX_PORTS + 1];
 354 };
 355
 356
 357 struct mlx4_en_rss_map {
 358         int base_qpn;
 359         struct mlx4_qp qps[MAX_RX_RINGS];
 360         enum mlx4_qp_state state[MAX_RX_RINGS];
 361         struct mlx4_qp indir_qp;
 362         enum mlx4_qp_state indir_state;
 363 };
 364
 365 struct mlx4_en_rss_context {
 366         __be32 base_qpn;
 367         __be32 default_qpn;
 368         u16 reserved;
 369         u8 hash_fn;
 370         u8 flags;
 371         __be32 rss_key[10];
 372         __be32 base_qpn_udp;
 373 };
 374
 375 struct mlx4_en_port_state {
 376         int link_state;
 377         int link_speed;
 378         int transciver;
 379 };
 380
 381 struct mlx4_en_pkt_stats {
 382         unsigned long broadcast;
 383         unsigned long rx_prio[8];
 384         unsigned long tx_prio[8];
 385 #define NUM_PKT_STATS           17
 386 };
 387
 388 struct mlx4_en_port_stats {
 389         unsigned long tso_packets;
 390         unsigned long queue_stopped;
 391         unsigned long wake_queue;
 392         unsigned long tx_timeout;
 393         unsigned long rx_alloc_failed;
 394         unsigned long rx_chksum_good;
 395         unsigned long rx_chksum_none;
 396         unsigned long tx_chksum_offload;
 397 #define NUM_PORT_STATS          8
 398 };
 399
 400 struct mlx4_en_perf_stats {
 401         u32 tx_poll;
 402         u64 tx_pktsz_avg;
 403         u32 inflight_avg;
 404         u16 tx_coal_avg;
 405         u16 rx_coal_avg;
 406         u32 napi_quota;
 407 #define NUM_PERF_COUNTERS               6
 408 };
 409
 410 struct mlx4_en_frag_info {
 411         u16 frag_size;
 412         u16 frag_prefix_size;
 413         u16 frag_stride;
 414         u16 frag_align;
 415         u16 last_offset;
 416
 417 };
 418
 419 struct mlx4_en_priv {
 420         struct mlx4_en_dev *mdev;
 421         struct mlx4_en_port_profile *prof;
 422         struct net_device *dev;
 423         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 424         struct net_device_stats stats;
 425         struct net_device_stats ret_stats;
 426         struct mlx4_en_port_state port_state;
 427         spinlock_t stats_lock;
 428
 429         unsigned long last_moder_packets;
 430         unsigned long last_moder_tx_packets;
 431         unsigned long last_moder_bytes;
 432         unsigned long last_moder_jiffies;
 433         int last_moder_time;
 434         u16 rx_usecs;
 435         u16 rx_frames;
 436         u16 tx_usecs;
 437         u16 tx_frames;
 438         u32 pkt_rate_low;
 439         u16 rx_usecs_low;
 440         u32 pkt_rate_high;
 441         u16 rx_usecs_high;
 442         u16 sample_interval;
 443         u16 adaptive_rx_coal;
 444         u32 msg_enable;
 445         u32 loopback_ok;
 446         u32 validate_loopback;
 447
 448         struct mlx4_hwq_resources res;
 449         int link_state;
 450         int last_link_state;
 451         bool port_up;
 452         int port;
 453         int registered;
 454         int allocated;
 455         int stride;
 456         u64 mac;
 457         int mac_index;
 458         unsigned max_mtu;
 459         int base_qpn;
 460
 461         struct mlx4_en_rss_map rss_map;
 462         u32 flags;
 463 #define MLX4_EN_FLAG_PROMISC    0x1
 464 #define MLX4_EN_FLAG_MC_PROMISC 0x2
 465         u32 tx_ring_num;
 466         u32 rx_ring_num;
 467         u32 rx_skb_size;
 468         struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
 469         u16 num_frags;
 470         u16 log_rx_info;
 471
 472         struct mlx4_en_tx_ring tx_ring[MAX_TX_RINGS];
 473         int tx_vector;
 474         struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS];
 475         struct mlx4_en_cq tx_cq[MAX_TX_RINGS];
 476         struct mlx4_en_cq rx_cq[MAX_RX_RINGS];
 477         struct work_struct mcast_task;
 478         struct work_struct mac_task;
 479         struct work_struct watchdog_task;
 480         struct work_struct linkstate_task;
 481         struct delayed_work stats_task;
 482         struct mlx4_en_perf_stats pstats;
 483         struct mlx4_en_pkt_stats pkstats;
 484         struct mlx4_en_port_stats port_stats;
 485         char *mc_addrs;
 486         int mc_addrs_cnt;
 487         struct mlx4_en_stat_out_mbox hw_stats;
 488         int vids[128];
 489         bool wol;
 490 };
 491
 492 enum mlx4_en_wol {
 493         MLX4_EN_WOL_MAGIC = (1ULL << 61),
 494         MLX4_EN_WOL_ENABLED = (1ULL << 62),
 495         MLX4_EN_WOL_DO_MODIFY = (1ULL << 63),
 496 };
 497
 498
 499 void mlx4_en_destroy_netdev(struct net_device *dev);
 500 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
 501                         struct mlx4_en_port_profile *prof);
 502
 503 int mlx4_en_start_port(struct net_device *dev);
 504 void mlx4_en_stop_port(struct net_device *dev);
 505
 506 void mlx4_en_free_resources(struct mlx4_en_priv *priv, bool reserve_vectors);
 507 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
 508
 509 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
 510                       int entries, int ring, enum cq_type mode);
 511 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
 512                         bool reserve_vectors);
 513 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 514 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 515 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 516 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 517
 518 void mlx4_en_poll_tx_cq(unsigned long data);
 519 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
 520 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb);
 521 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
 522
 523 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring,
 524                            int qpn, u32 size, u16 stride);
 525 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring);
 526 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
 527                              struct mlx4_en_tx_ring *ring,
 528                              int cq);
 529 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
 530                                 struct mlx4_en_tx_ring *ring);
 531
 532 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
 533                            struct mlx4_en_rx_ring *ring,
 534                            u32 size, u16 stride);
 535 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
 536                              struct mlx4_en_rx_ring *ring);
 537 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
 538 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
 539                                 struct mlx4_en_rx_ring *ring);
 540 int mlx4_en_process_rx_cq(struct net_device *dev,
 541                           struct mlx4_en_cq *cq,
 542                           int budget);
 543 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
 544 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
 545                              int is_tx, int rss, int qpn, int cqn,
 546                              struct mlx4_qp_context *context);
 547 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
 548 int mlx4_en_map_buffer(struct mlx4_buf *buf);
 549 void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
 550
 551 void mlx4_en_calc_rx_buf(struct net_device *dev);
 552 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
 553 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
 554 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
 555 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
 556
 557 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
 558 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
 559 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
 560                           u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
 561 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
 562                            u8 promisc);
 563
 564 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
 565 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
 566
 567 #define MLX4_EN_NUM_SELF_TEST   5
 568 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
 569 u64 mlx4_en_mac_to_u64(u8 *addr);
 570
 571 /*
 572  * Globals
 573  */
 574 extern const struct ethtool_ops mlx4_en_ethtool_ops;
 575
 576
 577
 578 /*
 579  * printk / logging functions
 580  */
 581
 582 int en_print(const char *level, const struct mlx4_en_priv *priv,
 583              const char *format, ...) __attribute__ ((format (printf, 3, 4)));
 584
 585 #define en_dbg(mlevel, priv, format, arg...)                    \
 586 do {                                                            \
 587         if (NETIF_MSG_##mlevel & priv->msg_enable)              \
 588                 en_print(KERN_DEBUG, priv, format, ##arg);      \
 589 } while (0)
 590 #define en_warn(priv, format, arg...)                   \
 591         en_print(KERN_WARNING, priv, format, ##arg)
 592 #define en_err(priv, format, arg...)                    \
 593         en_print(KERN_ERR, priv, format, ##arg)
 594 #define en_info(priv, format, arg...)                   \
 595         en_print(KERN_INFO, priv, format, ## arg)
 596
 597 #define mlx4_err(mdev, format, arg...)                  \
 598         pr_err("%s %s: " format, DRV_NAME,              \
 599                dev_name(&mdev->pdev->dev), ##arg)
 600 #define mlx4_info(mdev, format, arg...)                 \
 601         pr_info("%s %s: " format, DRV_NAME,             \
 602                 dev_name(&mdev->pdev->dev), ##arg)
 603 #define mlx4_warn(mdev, format, arg...)                 \
 604         pr_warning("%s %s: " format, DRV_NAME,          \
 605                    dev_name(&mdev->pdev->dev), ##arg)
 606
 607 #endif