2 * Copyright (c) 2008-2009 Nuvoton technology corporation.
4 * Wan ZongShun <mcuos.com@gmail.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation;version 2 of the License.
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/mii.h>
15 #include <linux/netdevice.h>
16 #include <linux/etherdevice.h>
17 #include <linux/skbuff.h>
18 #include <linux/ethtool.h>
19 #include <linux/platform_device.h>
20 #include <linux/clk.h>
21 #include <linux/gfp.h>
23 #define DRV_MODULE_NAME "w90p910-emc"
24 #define DRV_MODULE_VERSION "0.1"
26 /* Ethernet MAC Registers */
27 #define REG_CAMCMR 0x00
28 #define REG_CAMEN 0x04
29 #define REG_CAMM_BASE 0x08
30 #define REG_CAML_BASE 0x0c
31 #define REG_TXDLSA 0x88
32 #define REG_RXDLSA 0x8C
33 #define REG_MCMDR 0x90
35 #define REG_MIIDA 0x98
36 #define REG_FFTCR 0x9C
39 #define REG_DMARFC 0xa8
41 #define REG_MISTA 0xb0
42 #define REG_CTXDSA 0xcc
43 #define REG_CTXBSA 0xd0
44 #define REG_CRXDSA 0xd4
45 #define REG_CRXBSA 0xd8
47 /* mac controller bit */
48 #define MCMDR_RXON 0x01
49 #define MCMDR_ACP (0x01 << 3)
50 #define MCMDR_SPCRC (0x01 << 5)
51 #define MCMDR_TXON (0x01 << 8)
52 #define MCMDR_FDUP (0x01 << 18)
53 #define MCMDR_ENMDC (0x01 << 19)
54 #define MCMDR_OPMOD (0x01 << 20)
55 #define SWR (0x01 << 24)
57 /* cam command regiser */
58 #define CAMCMR_AUP 0x01
59 #define CAMCMR_AMP (0x01 << 1)
60 #define CAMCMR_ABP (0x01 << 2)
61 #define CAMCMR_CCAM (0x01 << 3)
62 #define CAMCMR_ECMP (0x01 << 4)
65 /* mac mii controller bit */
66 #define MDCCR (0x0a << 20)
67 #define PHYAD (0x01 << 8)
68 #define PHYWR (0x01 << 16)
69 #define PHYBUSY (0x01 << 17)
70 #define PHYPRESP (0x01 << 18)
71 #define CAM_ENTRY_SIZE 0x08
73 /* rx and tx status */
74 #define TXDS_TXCP (0x01 << 19)
75 #define RXDS_CRCE (0x01 << 17)
76 #define RXDS_PTLE (0x01 << 19)
77 #define RXDS_RXGD (0x01 << 20)
78 #define RXDS_ALIE (0x01 << 21)
79 #define RXDS_RP (0x01 << 22)
81 /* mac interrupt status*/
82 #define MISTA_EXDEF (0x01 << 19)
83 #define MISTA_TXBERR (0x01 << 24)
84 #define MISTA_TDU (0x01 << 23)
85 #define MISTA_RDU (0x01 << 10)
86 #define MISTA_RXBERR (0x01 << 11)
90 #define ENRXGD (0x01 << 4)
91 #define ENRXBERR (0x01 << 11)
92 #define ENTXINTR (0x01 << 16)
93 #define ENTXCP (0x01 << 18)
94 #define ENTXABT (0x01 << 21)
95 #define ENTXBERR (0x01 << 24)
96 #define ENMDC (0x01 << 19)
97 #define PHYBUSY (0x01 << 17)
98 #define MDCCR_VAL 0xa00000
100 /* rx and tx owner bit */
101 #define RX_OWEN_DMA (0x01 << 31)
102 #define RX_OWEN_CPU (~(0x03 << 30))
103 #define TX_OWEN_DMA (0x01 << 31)
104 #define TX_OWEN_CPU (~(0x01 << 31))
106 /* tx frame desc controller bit */
107 #define MACTXINTEN 0x04
109 #define PADDINGMODE 0x01
111 /* fftcr controller bit */
112 #define TXTHD (0x03 << 8)
113 #define BLENGTH (0x01 << 20)
115 /* global setting for driver */
116 #define RX_DESC_SIZE 50
117 #define TX_DESC_SIZE 10
118 #define MAX_RBUFF_SZ 0x600
119 #define MAX_TBUFF_SZ 0x600
120 #define TX_TIMEOUT (HZ/2)
124 static int w90p910_mdio_read(struct net_device
*dev
, int phy_id
, int reg
);
126 struct w90p910_rxbd
{
129 unsigned int reserved
;
133 struct w90p910_txbd
{
141 struct w90p910_rxbd desclist
[RX_DESC_SIZE
];
142 char recv_buf
[RX_DESC_SIZE
][MAX_RBUFF_SZ
];
146 struct w90p910_txbd desclist
[TX_DESC_SIZE
];
147 char tran_buf
[TX_DESC_SIZE
][MAX_TBUFF_SZ
];
150 struct w90p910_ether
{
151 struct recv_pdesc
*rdesc
;
152 struct tran_pdesc
*tdesc
;
153 dma_addr_t rdesc_phys
;
154 dma_addr_t tdesc_phys
;
155 struct net_device_stats stats
;
156 struct platform_device
*pdev
;
157 struct resource
*res
;
161 struct mii_if_info mii
;
162 struct timer_list check_timer
;
168 unsigned int finish_tx
;
169 unsigned int rx_packets
;
170 unsigned int rx_bytes
;
171 unsigned int start_tx_ptr
;
172 unsigned int start_rx_ptr
;
173 unsigned int linkflag
;
176 static void update_linkspeed_register(struct net_device
*dev
,
177 unsigned int speed
, unsigned int duplex
)
179 struct w90p910_ether
*ether
= netdev_priv(dev
);
182 val
= __raw_readl(ether
->reg
+ REG_MCMDR
);
184 if (speed
== SPEED_100
) {
185 /* 100 full/half duplex */
186 if (duplex
== DUPLEX_FULL
) {
187 val
|= (MCMDR_OPMOD
| MCMDR_FDUP
);
193 /* 10 full/half duplex */
194 if (duplex
== DUPLEX_FULL
) {
198 val
&= ~(MCMDR_FDUP
| MCMDR_OPMOD
);
202 __raw_writel(val
, ether
->reg
+ REG_MCMDR
);
205 static void update_linkspeed(struct net_device
*dev
)
207 struct w90p910_ether
*ether
= netdev_priv(dev
);
208 struct platform_device
*pdev
;
209 unsigned int bmsr
, bmcr
, lpa
, speed
, duplex
;
213 if (!mii_link_ok(ðer
->mii
)) {
214 ether
->linkflag
= 0x0;
215 netif_carrier_off(dev
);
216 dev_warn(&pdev
->dev
, "%s: Link down.\n", dev
->name
);
220 if (ether
->linkflag
== 1)
223 bmsr
= w90p910_mdio_read(dev
, ether
->mii
.phy_id
, MII_BMSR
);
224 bmcr
= w90p910_mdio_read(dev
, ether
->mii
.phy_id
, MII_BMCR
);
226 if (bmcr
& BMCR_ANENABLE
) {
227 if (!(bmsr
& BMSR_ANEGCOMPLETE
))
230 lpa
= w90p910_mdio_read(dev
, ether
->mii
.phy_id
, MII_LPA
);
232 if ((lpa
& LPA_100FULL
) || (lpa
& LPA_100HALF
))
237 if ((lpa
& LPA_100FULL
) || (lpa
& LPA_10FULL
))
238 duplex
= DUPLEX_FULL
;
240 duplex
= DUPLEX_HALF
;
243 speed
= (bmcr
& BMCR_SPEED100
) ? SPEED_100
: SPEED_10
;
244 duplex
= (bmcr
& BMCR_FULLDPLX
) ? DUPLEX_FULL
: DUPLEX_HALF
;
247 update_linkspeed_register(dev
, speed
, duplex
);
249 dev_info(&pdev
->dev
, "%s: Link now %i-%s\n", dev
->name
, speed
,
250 (duplex
== DUPLEX_FULL
) ? "FullDuplex" : "HalfDuplex");
251 ether
->linkflag
= 0x01;
253 netif_carrier_on(dev
);
256 static void w90p910_check_link(unsigned long dev_id
)
258 struct net_device
*dev
= (struct net_device
*) dev_id
;
259 struct w90p910_ether
*ether
= netdev_priv(dev
);
261 update_linkspeed(dev
);
262 mod_timer(ðer
->check_timer
, jiffies
+ msecs_to_jiffies(1000));
265 static void w90p910_write_cam(struct net_device
*dev
,
266 unsigned int x
, unsigned char *pval
)
268 struct w90p910_ether
*ether
= netdev_priv(dev
);
269 unsigned int msw
, lsw
;
271 msw
= (pval
[0] << 24) | (pval
[1] << 16) | (pval
[2] << 8) | pval
[3];
273 lsw
= (pval
[4] << 24) | (pval
[5] << 16);
275 __raw_writel(lsw
, ether
->reg
+ REG_CAML_BASE
+ x
* CAM_ENTRY_SIZE
);
276 __raw_writel(msw
, ether
->reg
+ REG_CAMM_BASE
+ x
* CAM_ENTRY_SIZE
);
279 static int w90p910_init_desc(struct net_device
*dev
)
281 struct w90p910_ether
*ether
;
282 struct w90p910_txbd
*tdesc
;
283 struct w90p910_rxbd
*rdesc
;
284 struct platform_device
*pdev
;
287 ether
= netdev_priv(dev
);
290 ether
->tdesc
= (struct tran_pdesc
*)
291 dma_alloc_coherent(&pdev
->dev
, sizeof(struct tran_pdesc
),
292 ðer
->tdesc_phys
, GFP_KERNEL
);
295 dev_err(&pdev
->dev
, "Failed to allocate memory for tx desc\n");
299 ether
->rdesc
= (struct recv_pdesc
*)
300 dma_alloc_coherent(&pdev
->dev
, sizeof(struct recv_pdesc
),
301 ðer
->rdesc_phys
, GFP_KERNEL
);
304 dev_err(&pdev
->dev
, "Failed to allocate memory for rx desc\n");
305 dma_free_coherent(&pdev
->dev
, sizeof(struct tran_pdesc
),
306 ether
->tdesc
, ether
->tdesc_phys
);
310 for (i
= 0; i
< TX_DESC_SIZE
; i
++) {
313 tdesc
= &(ether
->tdesc
->desclist
[i
]);
315 if (i
== TX_DESC_SIZE
- 1)
316 offset
= offsetof(struct tran_pdesc
, desclist
[0]);
318 offset
= offsetof(struct tran_pdesc
, desclist
[i
+ 1]);
320 tdesc
->next
= ether
->tdesc_phys
+ offset
;
321 tdesc
->buffer
= ether
->tdesc_phys
+
322 offsetof(struct tran_pdesc
, tran_buf
[i
]);
327 ether
->start_tx_ptr
= ether
->tdesc_phys
;
329 for (i
= 0; i
< RX_DESC_SIZE
; i
++) {
332 rdesc
= &(ether
->rdesc
->desclist
[i
]);
334 if (i
== RX_DESC_SIZE
- 1)
335 offset
= offsetof(struct recv_pdesc
, desclist
[0]);
337 offset
= offsetof(struct recv_pdesc
, desclist
[i
+ 1]);
339 rdesc
->next
= ether
->rdesc_phys
+ offset
;
340 rdesc
->sl
= RX_OWEN_DMA
;
341 rdesc
->buffer
= ether
->rdesc_phys
+
342 offsetof(struct recv_pdesc
, recv_buf
[i
]);
345 ether
->start_rx_ptr
= ether
->rdesc_phys
;
350 static void w90p910_set_fifo_threshold(struct net_device
*dev
)
352 struct w90p910_ether
*ether
= netdev_priv(dev
);
355 val
= TXTHD
| BLENGTH
;
356 __raw_writel(val
, ether
->reg
+ REG_FFTCR
);
359 static void w90p910_return_default_idle(struct net_device
*dev
)
361 struct w90p910_ether
*ether
= netdev_priv(dev
);
364 val
= __raw_readl(ether
->reg
+ REG_MCMDR
);
366 __raw_writel(val
, ether
->reg
+ REG_MCMDR
);
369 static void w90p910_trigger_rx(struct net_device
*dev
)
371 struct w90p910_ether
*ether
= netdev_priv(dev
);
373 __raw_writel(ENSTART
, ether
->reg
+ REG_RSDR
);
376 static void w90p910_trigger_tx(struct net_device
*dev
)
378 struct w90p910_ether
*ether
= netdev_priv(dev
);
380 __raw_writel(ENSTART
, ether
->reg
+ REG_TSDR
);
383 static void w90p910_enable_mac_interrupt(struct net_device
*dev
)
385 struct w90p910_ether
*ether
= netdev_priv(dev
);
388 val
= ENTXINTR
| ENRXINTR
| ENRXGD
| ENTXCP
;
389 val
|= ENTXBERR
| ENRXBERR
| ENTXABT
;
391 __raw_writel(val
, ether
->reg
+ REG_MIEN
);
394 static void w90p910_get_and_clear_int(struct net_device
*dev
,
397 struct w90p910_ether
*ether
= netdev_priv(dev
);
399 *val
= __raw_readl(ether
->reg
+ REG_MISTA
);
400 __raw_writel(*val
, ether
->reg
+ REG_MISTA
);
403 static void w90p910_set_global_maccmd(struct net_device
*dev
)
405 struct w90p910_ether
*ether
= netdev_priv(dev
);
408 val
= __raw_readl(ether
->reg
+ REG_MCMDR
);
409 val
|= MCMDR_SPCRC
| MCMDR_ENMDC
| MCMDR_ACP
| ENMDC
;
410 __raw_writel(val
, ether
->reg
+ REG_MCMDR
);
413 static void w90p910_enable_cam(struct net_device
*dev
)
415 struct w90p910_ether
*ether
= netdev_priv(dev
);
418 w90p910_write_cam(dev
, CAM0
, dev
->dev_addr
);
420 val
= __raw_readl(ether
->reg
+ REG_CAMEN
);
422 __raw_writel(val
, ether
->reg
+ REG_CAMEN
);
425 static void w90p910_enable_cam_command(struct net_device
*dev
)
427 struct w90p910_ether
*ether
= netdev_priv(dev
);
430 val
= CAMCMR_ECMP
| CAMCMR_ABP
| CAMCMR_AMP
;
431 __raw_writel(val
, ether
->reg
+ REG_CAMCMR
);
434 static void w90p910_enable_tx(struct net_device
*dev
, unsigned int enable
)
436 struct w90p910_ether
*ether
= netdev_priv(dev
);
439 val
= __raw_readl(ether
->reg
+ REG_MCMDR
);
446 __raw_writel(val
, ether
->reg
+ REG_MCMDR
);
449 static void w90p910_enable_rx(struct net_device
*dev
, unsigned int enable
)
451 struct w90p910_ether
*ether
= netdev_priv(dev
);
454 val
= __raw_readl(ether
->reg
+ REG_MCMDR
);
461 __raw_writel(val
, ether
->reg
+ REG_MCMDR
);
464 static void w90p910_set_curdest(struct net_device
*dev
)
466 struct w90p910_ether
*ether
= netdev_priv(dev
);
468 __raw_writel(ether
->start_rx_ptr
, ether
->reg
+ REG_RXDLSA
);
469 __raw_writel(ether
->start_tx_ptr
, ether
->reg
+ REG_TXDLSA
);
472 static void w90p910_reset_mac(struct net_device
*dev
)
474 struct w90p910_ether
*ether
= netdev_priv(dev
);
476 w90p910_enable_tx(dev
, 0);
477 w90p910_enable_rx(dev
, 0);
478 w90p910_set_fifo_threshold(dev
);
479 w90p910_return_default_idle(dev
);
481 if (!netif_queue_stopped(dev
))
482 netif_stop_queue(dev
);
484 w90p910_init_desc(dev
);
486 dev
->trans_start
= jiffies
; /* prevent tx timeout */
488 ether
->finish_tx
= 0x0;
491 w90p910_set_curdest(dev
);
492 w90p910_enable_cam(dev
);
493 w90p910_enable_cam_command(dev
);
494 w90p910_enable_mac_interrupt(dev
);
495 w90p910_enable_tx(dev
, 1);
496 w90p910_enable_rx(dev
, 1);
497 w90p910_trigger_tx(dev
);
498 w90p910_trigger_rx(dev
);
500 dev
->trans_start
= jiffies
; /* prevent tx timeout */
502 if (netif_queue_stopped(dev
))
503 netif_wake_queue(dev
);
506 static void w90p910_mdio_write(struct net_device
*dev
,
507 int phy_id
, int reg
, int data
)
509 struct w90p910_ether
*ether
= netdev_priv(dev
);
510 struct platform_device
*pdev
;
515 __raw_writel(data
, ether
->reg
+ REG_MIID
);
517 val
= (phy_id
<< 0x08) | reg
;
518 val
|= PHYBUSY
| PHYWR
| MDCCR_VAL
;
519 __raw_writel(val
, ether
->reg
+ REG_MIIDA
);
521 for (i
= 0; i
< DELAY
; i
++) {
522 if ((__raw_readl(ether
->reg
+ REG_MIIDA
) & PHYBUSY
) == 0)
527 dev_warn(&pdev
->dev
, "mdio write timed out\n");
530 static int w90p910_mdio_read(struct net_device
*dev
, int phy_id
, int reg
)
532 struct w90p910_ether
*ether
= netdev_priv(dev
);
533 struct platform_device
*pdev
;
534 unsigned int val
, i
, data
;
538 val
= (phy_id
<< 0x08) | reg
;
539 val
|= PHYBUSY
| MDCCR_VAL
;
540 __raw_writel(val
, ether
->reg
+ REG_MIIDA
);
542 for (i
= 0; i
< DELAY
; i
++) {
543 if ((__raw_readl(ether
->reg
+ REG_MIIDA
) & PHYBUSY
) == 0)
548 dev_warn(&pdev
->dev
, "mdio read timed out\n");
551 data
= __raw_readl(ether
->reg
+ REG_MIID
);
557 static int w90p910_set_mac_address(struct net_device
*dev
, void *addr
)
559 struct sockaddr
*address
= addr
;
561 if (!is_valid_ether_addr(address
->sa_data
))
562 return -EADDRNOTAVAIL
;
564 memcpy(dev
->dev_addr
, address
->sa_data
, dev
->addr_len
);
565 w90p910_write_cam(dev
, CAM0
, dev
->dev_addr
);
570 static int w90p910_ether_close(struct net_device
*dev
)
572 struct w90p910_ether
*ether
= netdev_priv(dev
);
573 struct platform_device
*pdev
;
577 dma_free_coherent(&pdev
->dev
, sizeof(struct recv_pdesc
),
578 ether
->rdesc
, ether
->rdesc_phys
);
579 dma_free_coherent(&pdev
->dev
, sizeof(struct tran_pdesc
),
580 ether
->tdesc
, ether
->tdesc_phys
);
582 netif_stop_queue(dev
);
584 del_timer_sync(ðer
->check_timer
);
585 clk_disable(ether
->rmiiclk
);
586 clk_disable(ether
->clk
);
588 free_irq(ether
->txirq
, dev
);
589 free_irq(ether
->rxirq
, dev
);
594 static struct net_device_stats
*w90p910_ether_stats(struct net_device
*dev
)
596 struct w90p910_ether
*ether
;
598 ether
= netdev_priv(dev
);
600 return ðer
->stats
;
603 static int w90p910_send_frame(struct net_device
*dev
,
604 unsigned char *data
, int length
)
606 struct w90p910_ether
*ether
;
607 struct w90p910_txbd
*txbd
;
608 struct platform_device
*pdev
;
609 unsigned char *buffer
;
611 ether
= netdev_priv(dev
);
614 txbd
= ðer
->tdesc
->desclist
[ether
->cur_tx
];
615 buffer
= ether
->tdesc
->tran_buf
[ether
->cur_tx
];
618 dev_err(&pdev
->dev
, "send data %d bytes, check it\n", length
);
622 txbd
->sl
= length
& 0xFFFF;
624 memcpy(buffer
, data
, length
);
626 txbd
->mode
= TX_OWEN_DMA
| PADDINGMODE
| CRCMODE
| MACTXINTEN
;
628 w90p910_enable_tx(dev
, 1);
630 w90p910_trigger_tx(dev
);
632 if (++ether
->cur_tx
>= TX_DESC_SIZE
)
635 txbd
= ðer
->tdesc
->desclist
[ether
->cur_tx
];
637 if (txbd
->mode
& TX_OWEN_DMA
)
638 netif_stop_queue(dev
);
643 static int w90p910_ether_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
645 struct w90p910_ether
*ether
= netdev_priv(dev
);
647 if (!(w90p910_send_frame(dev
, skb
->data
, skb
->len
))) {
649 dev_kfree_skb_irq(skb
);
655 static irqreturn_t
w90p910_tx_interrupt(int irq
, void *dev_id
)
657 struct w90p910_ether
*ether
;
658 struct w90p910_txbd
*txbd
;
659 struct platform_device
*pdev
;
660 struct net_device
*dev
;
661 unsigned int cur_entry
, entry
, status
;
664 ether
= netdev_priv(dev
);
667 w90p910_get_and_clear_int(dev
, &status
);
669 cur_entry
= __raw_readl(ether
->reg
+ REG_CTXDSA
);
671 entry
= ether
->tdesc_phys
+
672 offsetof(struct tran_pdesc
, desclist
[ether
->finish_tx
]);
674 while (entry
!= cur_entry
) {
675 txbd
= ðer
->tdesc
->desclist
[ether
->finish_tx
];
677 if (++ether
->finish_tx
>= TX_DESC_SIZE
)
678 ether
->finish_tx
= 0;
680 if (txbd
->sl
& TXDS_TXCP
) {
681 ether
->stats
.tx_packets
++;
682 ether
->stats
.tx_bytes
+= txbd
->sl
& 0xFFFF;
684 ether
->stats
.tx_errors
++;
690 if (netif_queue_stopped(dev
))
691 netif_wake_queue(dev
);
693 entry
= ether
->tdesc_phys
+
694 offsetof(struct tran_pdesc
, desclist
[ether
->finish_tx
]);
697 if (status
& MISTA_EXDEF
) {
698 dev_err(&pdev
->dev
, "emc defer exceed interrupt\n");
699 } else if (status
& MISTA_TXBERR
) {
700 dev_err(&pdev
->dev
, "emc bus error interrupt\n");
701 w90p910_reset_mac(dev
);
702 } else if (status
& MISTA_TDU
) {
703 if (netif_queue_stopped(dev
))
704 netif_wake_queue(dev
);
710 static void netdev_rx(struct net_device
*dev
)
712 struct w90p910_ether
*ether
;
713 struct w90p910_rxbd
*rxbd
;
714 struct platform_device
*pdev
;
717 unsigned int length
, status
, val
, entry
;
719 ether
= netdev_priv(dev
);
722 rxbd
= ðer
->rdesc
->desclist
[ether
->cur_rx
];
725 val
= __raw_readl(ether
->reg
+ REG_CRXDSA
);
727 entry
= ether
->rdesc_phys
+
728 offsetof(struct recv_pdesc
, desclist
[ether
->cur_rx
]);
734 length
= status
& 0xFFFF;
736 if (status
& RXDS_RXGD
) {
737 data
= ether
->rdesc
->recv_buf
[ether
->cur_rx
];
738 skb
= dev_alloc_skb(length
+2);
740 dev_err(&pdev
->dev
, "get skb buffer error\n");
741 ether
->stats
.rx_dropped
++;
746 skb_put(skb
, length
);
747 skb_copy_to_linear_data(skb
, data
, length
);
748 skb
->protocol
= eth_type_trans(skb
, dev
);
749 ether
->stats
.rx_packets
++;
750 ether
->stats
.rx_bytes
+= length
;
753 ether
->stats
.rx_errors
++;
755 if (status
& RXDS_RP
) {
756 dev_err(&pdev
->dev
, "rx runt err\n");
757 ether
->stats
.rx_length_errors
++;
758 } else if (status
& RXDS_CRCE
) {
759 dev_err(&pdev
->dev
, "rx crc err\n");
760 ether
->stats
.rx_crc_errors
++;
761 } else if (status
& RXDS_ALIE
) {
762 dev_err(&pdev
->dev
, "rx aligment err\n");
763 ether
->stats
.rx_frame_errors
++;
764 } else if (status
& RXDS_PTLE
) {
765 dev_err(&pdev
->dev
, "rx longer err\n");
766 ether
->stats
.rx_over_errors
++;
770 rxbd
->sl
= RX_OWEN_DMA
;
771 rxbd
->reserved
= 0x0;
773 if (++ether
->cur_rx
>= RX_DESC_SIZE
)
776 rxbd
= ðer
->rdesc
->desclist
[ether
->cur_rx
];
781 static irqreturn_t
w90p910_rx_interrupt(int irq
, void *dev_id
)
783 struct net_device
*dev
;
784 struct w90p910_ether
*ether
;
785 struct platform_device
*pdev
;
789 ether
= netdev_priv(dev
);
792 w90p910_get_and_clear_int(dev
, &status
);
794 if (status
& MISTA_RDU
) {
796 w90p910_trigger_rx(dev
);
799 } else if (status
& MISTA_RXBERR
) {
800 dev_err(&pdev
->dev
, "emc rx bus error\n");
801 w90p910_reset_mac(dev
);
808 static int w90p910_ether_open(struct net_device
*dev
)
810 struct w90p910_ether
*ether
;
811 struct platform_device
*pdev
;
813 ether
= netdev_priv(dev
);
816 w90p910_reset_mac(dev
);
817 w90p910_set_fifo_threshold(dev
);
818 w90p910_set_curdest(dev
);
819 w90p910_enable_cam(dev
);
820 w90p910_enable_cam_command(dev
);
821 w90p910_enable_mac_interrupt(dev
);
822 w90p910_set_global_maccmd(dev
);
823 w90p910_enable_rx(dev
, 1);
825 clk_enable(ether
->rmiiclk
);
826 clk_enable(ether
->clk
);
828 ether
->rx_packets
= 0x0;
829 ether
->rx_bytes
= 0x0;
831 if (request_irq(ether
->txirq
, w90p910_tx_interrupt
,
832 0x0, pdev
->name
, dev
)) {
833 dev_err(&pdev
->dev
, "register irq tx failed\n");
837 if (request_irq(ether
->rxirq
, w90p910_rx_interrupt
,
838 0x0, pdev
->name
, dev
)) {
839 dev_err(&pdev
->dev
, "register irq rx failed\n");
840 free_irq(ether
->txirq
, dev
);
844 mod_timer(ðer
->check_timer
, jiffies
+ msecs_to_jiffies(1000));
845 netif_start_queue(dev
);
846 w90p910_trigger_rx(dev
);
848 dev_info(&pdev
->dev
, "%s is OPENED\n", dev
->name
);
853 static void w90p910_ether_set_multicast_list(struct net_device
*dev
)
855 struct w90p910_ether
*ether
;
856 unsigned int rx_mode
;
858 ether
= netdev_priv(dev
);
860 if (dev
->flags
& IFF_PROMISC
)
861 rx_mode
= CAMCMR_AUP
| CAMCMR_AMP
| CAMCMR_ABP
| CAMCMR_ECMP
;
862 else if ((dev
->flags
& IFF_ALLMULTI
) || !netdev_mc_empty(dev
))
863 rx_mode
= CAMCMR_AMP
| CAMCMR_ABP
| CAMCMR_ECMP
;
865 rx_mode
= CAMCMR_ECMP
| CAMCMR_ABP
;
866 __raw_writel(rx_mode
, ether
->reg
+ REG_CAMCMR
);
869 static int w90p910_ether_ioctl(struct net_device
*dev
,
870 struct ifreq
*ifr
, int cmd
)
872 struct w90p910_ether
*ether
= netdev_priv(dev
);
873 struct mii_ioctl_data
*data
= if_mii(ifr
);
875 return generic_mii_ioctl(ðer
->mii
, data
, cmd
, NULL
);
878 static void w90p910_get_drvinfo(struct net_device
*dev
,
879 struct ethtool_drvinfo
*info
)
881 strcpy(info
->driver
, DRV_MODULE_NAME
);
882 strcpy(info
->version
, DRV_MODULE_VERSION
);
885 static int w90p910_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
887 struct w90p910_ether
*ether
= netdev_priv(dev
);
888 return mii_ethtool_gset(ðer
->mii
, cmd
);
891 static int w90p910_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
893 struct w90p910_ether
*ether
= netdev_priv(dev
);
894 return mii_ethtool_sset(ðer
->mii
, cmd
);
897 static int w90p910_nway_reset(struct net_device
*dev
)
899 struct w90p910_ether
*ether
= netdev_priv(dev
);
900 return mii_nway_restart(ðer
->mii
);
903 static u32
w90p910_get_link(struct net_device
*dev
)
905 struct w90p910_ether
*ether
= netdev_priv(dev
);
906 return mii_link_ok(ðer
->mii
);
909 static const struct ethtool_ops w90p910_ether_ethtool_ops
= {
910 .get_settings
= w90p910_get_settings
,
911 .set_settings
= w90p910_set_settings
,
912 .get_drvinfo
= w90p910_get_drvinfo
,
913 .nway_reset
= w90p910_nway_reset
,
914 .get_link
= w90p910_get_link
,
917 static const struct net_device_ops w90p910_ether_netdev_ops
= {
918 .ndo_open
= w90p910_ether_open
,
919 .ndo_stop
= w90p910_ether_close
,
920 .ndo_start_xmit
= w90p910_ether_start_xmit
,
921 .ndo_get_stats
= w90p910_ether_stats
,
922 .ndo_set_rx_mode
= w90p910_ether_set_multicast_list
,
923 .ndo_set_mac_address
= w90p910_set_mac_address
,
924 .ndo_do_ioctl
= w90p910_ether_ioctl
,
925 .ndo_validate_addr
= eth_validate_addr
,
926 .ndo_change_mtu
= eth_change_mtu
,
929 static void __init
get_mac_address(struct net_device
*dev
)
931 struct w90p910_ether
*ether
= netdev_priv(dev
);
932 struct platform_device
*pdev
;
944 if (is_valid_ether_addr(addr
))
945 memcpy(dev
->dev_addr
, &addr
, 0x06);
947 dev_err(&pdev
->dev
, "invalid mac address\n");
950 static int w90p910_ether_setup(struct net_device
*dev
)
952 struct w90p910_ether
*ether
= netdev_priv(dev
);
955 dev
->netdev_ops
= &w90p910_ether_netdev_ops
;
956 dev
->ethtool_ops
= &w90p910_ether_ethtool_ops
;
958 dev
->tx_queue_len
= 16;
960 dev
->watchdog_timeo
= TX_TIMEOUT
;
962 get_mac_address(dev
);
966 ether
->finish_tx
= 0x0;
967 ether
->linkflag
= 0x0;
968 ether
->mii
.phy_id
= 0x01;
969 ether
->mii
.phy_id_mask
= 0x1f;
970 ether
->mii
.reg_num_mask
= 0x1f;
971 ether
->mii
.dev
= dev
;
972 ether
->mii
.mdio_read
= w90p910_mdio_read
;
973 ether
->mii
.mdio_write
= w90p910_mdio_write
;
975 setup_timer(ðer
->check_timer
, w90p910_check_link
,
981 static int __devinit
w90p910_ether_probe(struct platform_device
*pdev
)
983 struct w90p910_ether
*ether
;
984 struct net_device
*dev
;
987 dev
= alloc_etherdev(sizeof(struct w90p910_ether
));
991 ether
= netdev_priv(dev
);
993 ether
->res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
994 if (ether
->res
== NULL
) {
995 dev_err(&pdev
->dev
, "failed to get I/O memory\n");
1000 if (!request_mem_region(ether
->res
->start
,
1001 resource_size(ether
->res
), pdev
->name
)) {
1002 dev_err(&pdev
->dev
, "failed to request I/O memory\n");
1007 ether
->reg
= ioremap(ether
->res
->start
, resource_size(ether
->res
));
1008 if (ether
->reg
== NULL
) {
1009 dev_err(&pdev
->dev
, "failed to remap I/O memory\n");
1011 goto failed_free_mem
;
1014 ether
->txirq
= platform_get_irq(pdev
, 0);
1015 if (ether
->txirq
< 0) {
1016 dev_err(&pdev
->dev
, "failed to get ether tx irq\n");
1018 goto failed_free_io
;
1021 ether
->rxirq
= platform_get_irq(pdev
, 1);
1022 if (ether
->rxirq
< 0) {
1023 dev_err(&pdev
->dev
, "failed to get ether rx irq\n");
1025 goto failed_free_txirq
;
1028 platform_set_drvdata(pdev
, dev
);
1030 ether
->clk
= clk_get(&pdev
->dev
, NULL
);
1031 if (IS_ERR(ether
->clk
)) {
1032 dev_err(&pdev
->dev
, "failed to get ether clock\n");
1033 error
= PTR_ERR(ether
->clk
);
1034 goto failed_free_rxirq
;
1037 ether
->rmiiclk
= clk_get(&pdev
->dev
, "RMII");
1038 if (IS_ERR(ether
->rmiiclk
)) {
1039 dev_err(&pdev
->dev
, "failed to get ether clock\n");
1040 error
= PTR_ERR(ether
->rmiiclk
);
1041 goto failed_put_clk
;
1046 w90p910_ether_setup(dev
);
1048 error
= register_netdev(dev
);
1050 dev_err(&pdev
->dev
, "Regiter EMC w90p910 FAILED\n");
1052 goto failed_put_rmiiclk
;
1057 clk_put(ether
->rmiiclk
);
1059 clk_put(ether
->clk
);
1061 free_irq(ether
->rxirq
, pdev
);
1062 platform_set_drvdata(pdev
, NULL
);
1064 free_irq(ether
->txirq
, pdev
);
1066 iounmap(ether
->reg
);
1068 release_mem_region(ether
->res
->start
, resource_size(ether
->res
));
1074 static int __devexit
w90p910_ether_remove(struct platform_device
*pdev
)
1076 struct net_device
*dev
= platform_get_drvdata(pdev
);
1077 struct w90p910_ether
*ether
= netdev_priv(dev
);
1079 unregister_netdev(dev
);
1081 clk_put(ether
->rmiiclk
);
1082 clk_put(ether
->clk
);
1084 iounmap(ether
->reg
);
1085 release_mem_region(ether
->res
->start
, resource_size(ether
->res
));
1087 free_irq(ether
->txirq
, dev
);
1088 free_irq(ether
->rxirq
, dev
);
1090 del_timer_sync(ðer
->check_timer
);
1091 platform_set_drvdata(pdev
, NULL
);
1097 static struct platform_driver w90p910_ether_driver
= {
1098 .probe
= w90p910_ether_probe
,
1099 .remove
= __devexit_p(w90p910_ether_remove
),
1101 .name
= "nuc900-emc",
1102 .owner
= THIS_MODULE
,
1106 static int __init
w90p910_ether_init(void)
1108 return platform_driver_register(&w90p910_ether_driver
);
1111 static void __exit
w90p910_ether_exit(void)
1113 platform_driver_unregister(&w90p910_ether_driver
);
1116 module_init(w90p910_ether_init
);
1117 module_exit(w90p910_ether_exit
);
1119 MODULE_AUTHOR("Wan ZongShun <mcuos.com@gmail.com>");
1120 MODULE_DESCRIPTION("w90p910 MAC driver!");
1121 MODULE_LICENSE("GPL");
1122 MODULE_ALIAS("platform:nuc900-emc");