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Add linux-next specific files for 20110831
[linux-2.6/next.git] / drivers / sh / intc / core.c
blobf8925299d7c0303b2f487c5b4a19120808e214b2
1 /*
2 * Shared interrupt handling code for IPR and INTC2 types of IRQs.
3 *
4 * Copyright (C) 2007, 2008 Magnus Damm
5 * Copyright (C) 2009, 2010 Paul Mundt
6 *
7 * Based on intc2.c and ipr.c
8 *
9 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
10 * Copyright (C) 2000 Kazumoto Kojima
11 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
12 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
13 * Copyright (C) 2005, 2006 Paul Mundt
14 *
15 * This file is subject to the terms and conditions of the GNU General Public
16 * License. See the file "COPYING" in the main directory of this archive
17 * for more details.
18 */
19 #define pr_fmt(fmt) "intc: " fmt
20
21 #include <linux/init.h>
22 #include <linux/irq.h>
23 #include <linux/io.h>
24 #include <linux/slab.h>
25 #include <linux/stat.h>
26 #include <linux/interrupt.h>
27 #include <linux/sh_intc.h>
28 #include <linux/sysdev.h>
29 #include <linux/syscore_ops.h>
30 #include <linux/list.h>
31 #include <linux/spinlock.h>
32 #include <linux/radix-tree.h>
33 #include "internals.h"
34
35 LIST_HEAD(intc_list);
36 DEFINE_RAW_SPINLOCK(intc_big_lock);
37 unsigned int nr_intc_controllers;
38
39 /*
40 * Default priority level
41 * - this needs to be at least 2 for 5-bit priorities on 7780
42 */
43 static unsigned int default_prio_level = 2; /* 2 - 16 */
44 static unsigned int intc_prio_level[NR_IRQS]; /* for now */
45
46 unsigned int intc_get_dfl_prio_level(void)
47 {
48 return default_prio_level;
49 }
50
51 unsigned int intc_get_prio_level(unsigned int irq)
52 {
53 return intc_prio_level[irq];
54 }
55
56 void intc_set_prio_level(unsigned int irq, unsigned int level)
57 {
58 unsigned long flags;
59
60 raw_spin_lock_irqsave(&intc_big_lock, flags);
61 intc_prio_level[irq] = level;
62 raw_spin_unlock_irqrestore(&intc_big_lock, flags);
63 }
64
65 static void intc_redirect_irq(unsigned int irq, struct irq_desc *desc)
66 {
67 generic_handle_irq((unsigned int)irq_get_handler_data(irq));
68 }
69
70 static void __init intc_register_irq(struct intc_desc *desc,
71 struct intc_desc_int *d,
72 intc_enum enum_id,
73 unsigned int irq)
74 {
75 struct intc_handle_int *hp;
76 struct irq_data *irq_data;
77 unsigned int data[2], primary;
78 unsigned long flags;
79
80 /*
81 * Register the IRQ position with the global IRQ map, then insert
82 * it in to the radix tree.
83 */
84 irq_reserve_irq(irq);
85
86 raw_spin_lock_irqsave(&intc_big_lock, flags);
87 radix_tree_insert(&d->tree, enum_id, intc_irq_xlate_get(irq));
88 raw_spin_unlock_irqrestore(&intc_big_lock, flags);
89
90 /*
91 * Prefer single interrupt source bitmap over other combinations:
92 *
93 * 1. bitmap, single interrupt source
94 * 2. priority, single interrupt source
95 * 3. bitmap, multiple interrupt sources (groups)
96 * 4. priority, multiple interrupt sources (groups)
97 */
98 data[0] = intc_get_mask_handle(desc, d, enum_id, 0);
99 data[1] = intc_get_prio_handle(desc, d, enum_id, 0);
100
101 primary = 0;
102 if (!data[0] && data[1])
103 primary = 1;
104
105 if (!data[0] && !data[1])
106 pr_warning("missing unique irq mask for irq %d (vect 0x%04x)\n",
107 irq, irq2evt(irq));
108
109 data[0] = data[0] ? data[0] : intc_get_mask_handle(desc, d, enum_id, 1);
110 data[1] = data[1] ? data[1] : intc_get_prio_handle(desc, d, enum_id, 1);
111
112 if (!data[primary])
113 primary ^= 1;
114
115 BUG_ON(!data[primary]); /* must have primary masking method */
116
117 irq_data = irq_get_irq_data(irq);
118
119 disable_irq_nosync(irq);
120 irq_set_chip_and_handler_name(irq, &d->chip, handle_level_irq,
121 "level");
122 irq_set_chip_data(irq, (void *)data[primary]);
123
124 /*
125 * set priority level
126 */
127 intc_set_prio_level(irq, intc_get_dfl_prio_level());
128
129 /* enable secondary masking method if present */
130 if (data[!primary])
131 _intc_enable(irq_data, data[!primary]);
132
133 /* add irq to d->prio list if priority is available */
134 if (data[1]) {
135 hp = d->prio + d->nr_prio;
136 hp->irq = irq;
137 hp->handle = data[1];
138
139 if (primary) {
140 /*
141 * only secondary priority should access registers, so
142 * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
143 */
144 hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
145 hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
146 }
147 d->nr_prio++;
148 }
149
150 /* add irq to d->sense list if sense is available */
151 data[0] = intc_get_sense_handle(desc, d, enum_id);
152 if (data[0]) {
153 (d->sense + d->nr_sense)->irq = irq;
154 (d->sense + d->nr_sense)->handle = data[0];
155 d->nr_sense++;
156 }
157
158 /* irq should be disabled by default */
159 d->chip.irq_mask(irq_data);
160
161 intc_set_ack_handle(irq, desc, d, enum_id);
162 intc_set_dist_handle(irq, desc, d, enum_id);
163
164 activate_irq(irq);
165 }
166
167 static unsigned int __init save_reg(struct intc_desc_int *d,
168 unsigned int cnt,
169 unsigned long value,
170 unsigned int smp)
171 {
172 if (value) {
173 value = intc_phys_to_virt(d, value);
174
175 d->reg[cnt] = value;
176 #ifdef CONFIG_SMP
177 d->smp[cnt] = smp;
178 #endif
179 return 1;
180 }
181
182 return 0;
183 }
184
185 int __init register_intc_controller(struct intc_desc *desc)
186 {
187 unsigned int i, k, smp;
188 struct intc_hw_desc *hw = &desc->hw;
189 struct intc_desc_int *d;
190 struct resource *res;
191
192 pr_info("Registered controller '%s' with %u IRQs\n",
193 desc->name, hw->nr_vectors);
194
195 d = kzalloc(sizeof(*d), GFP_NOWAIT);
196 if (!d)
197 goto err0;
198
199 INIT_LIST_HEAD(&d->list);
200 list_add_tail(&d->list, &intc_list);
201
202 raw_spin_lock_init(&d->lock);
203 INIT_RADIX_TREE(&d->tree, GFP_ATOMIC);
204
205 d->index = nr_intc_controllers;
206
207 if (desc->num_resources) {
208 d->nr_windows = desc->num_resources;
209 d->window = kzalloc(d->nr_windows * sizeof(*d->window),
210 GFP_NOWAIT);
211 if (!d->window)
212 goto err1;
213
214 for (k = 0; k < d->nr_windows; k++) {
215 res = desc->resource + k;
216 WARN_ON(resource_type(res) != IORESOURCE_MEM);
217 d->window[k].phys = res->start;
218 d->window[k].size = resource_size(res);
219 d->window[k].virt = ioremap_nocache(res->start,
220 resource_size(res));
221 if (!d->window[k].virt)
222 goto err2;
223 }
224 }
225
226 d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0;
227 #ifdef CONFIG_INTC_BALANCING
228 if (d->nr_reg)
229 d->nr_reg += hw->nr_mask_regs;
230 #endif
231 d->nr_reg += hw->prio_regs ? hw->nr_prio_regs * 2 : 0;
232 d->nr_reg += hw->sense_regs ? hw->nr_sense_regs : 0;
233 d->nr_reg += hw->ack_regs ? hw->nr_ack_regs : 0;
234 d->nr_reg += hw->subgroups ? hw->nr_subgroups : 0;
235
236 d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT);
237 if (!d->reg)
238 goto err2;
239
240 #ifdef CONFIG_SMP
241 d->smp = kzalloc(d->nr_reg * sizeof(*d->smp), GFP_NOWAIT);
242 if (!d->smp)
243 goto err3;
244 #endif
245 k = 0;
246
247 if (hw->mask_regs) {
248 for (i = 0; i < hw->nr_mask_regs; i++) {
249 smp = IS_SMP(hw->mask_regs[i]);
250 k += save_reg(d, k, hw->mask_regs[i].set_reg, smp);
251 k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp);
252 #ifdef CONFIG_INTC_BALANCING
253 k += save_reg(d, k, hw->mask_regs[i].dist_reg, 0);
254 #endif
255 }
256 }
257
258 if (hw->prio_regs) {
259 d->prio = kzalloc(hw->nr_vectors * sizeof(*d->prio),
260 GFP_NOWAIT);
261 if (!d->prio)
262 goto err4;
263
264 for (i = 0; i < hw->nr_prio_regs; i++) {
265 smp = IS_SMP(hw->prio_regs[i]);
266 k += save_reg(d, k, hw->prio_regs[i].set_reg, smp);
267 k += save_reg(d, k, hw->prio_regs[i].clr_reg, smp);
268 }
269 }
270
271 if (hw->sense_regs) {
272 d->sense = kzalloc(hw->nr_vectors * sizeof(*d->sense),
273 GFP_NOWAIT);
274 if (!d->sense)
275 goto err5;
276
277 for (i = 0; i < hw->nr_sense_regs; i++)
278 k += save_reg(d, k, hw->sense_regs[i].reg, 0);
279 }
280
281 if (hw->subgroups)
282 for (i = 0; i < hw->nr_subgroups; i++)
283 if (hw->subgroups[i].reg)
284 k+= save_reg(d, k, hw->subgroups[i].reg, 0);
285
286 memcpy(&d->chip, &intc_irq_chip, sizeof(struct irq_chip));
287 d->chip.name = desc->name;
288
289 if (hw->ack_regs)
290 for (i = 0; i < hw->nr_ack_regs; i++)
291 k += save_reg(d, k, hw->ack_regs[i].set_reg, 0);
292 else
293 d->chip.irq_mask_ack = d->chip.irq_disable;
294
295 /* disable bits matching force_disable before registering irqs */
296 if (desc->force_disable)
297 intc_enable_disable_enum(desc, d, desc->force_disable, 0);
298
299 /* disable bits matching force_enable before registering irqs */
300 if (desc->force_enable)
301 intc_enable_disable_enum(desc, d, desc->force_enable, 0);
302
303 BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
304
305 /* register the vectors one by one */
306 for (i = 0; i < hw->nr_vectors; i++) {
307 struct intc_vect *vect = hw->vectors + i;
308 unsigned int irq = evt2irq(vect->vect);
309 int res;
310
311 if (!vect->enum_id)
312 continue;
313
314 res = irq_alloc_desc_at(irq, numa_node_id());
315 if (res != irq && res != -EEXIST) {
316 pr_err("can't get irq_desc for %d\n", irq);
317 continue;
318 }
319
320 intc_irq_xlate_set(irq, vect->enum_id, d);
321 intc_register_irq(desc, d, vect->enum_id, irq);
322
323 for (k = i + 1; k < hw->nr_vectors; k++) {
324 struct intc_vect *vect2 = hw->vectors + k;
325 unsigned int irq2 = evt2irq(vect2->vect);
326
327 if (vect->enum_id != vect2->enum_id)
328 continue;
329
330 /*
331 * In the case of multi-evt handling and sparse
332 * IRQ support, each vector still needs to have
333 * its own backing irq_desc.
334 */
335 res = irq_alloc_desc_at(irq2, numa_node_id());
336 if (res != irq2 && res != -EEXIST) {
337 pr_err("can't get irq_desc for %d\n", irq2);
338 continue;
339 }
340
341 vect2->enum_id = 0;
342
343 /* redirect this interrupts to the first one */
344 irq_set_chip(irq2, &dummy_irq_chip);
345 irq_set_chained_handler(irq2, intc_redirect_irq);
346 irq_set_handler_data(irq2, (void *)irq);
347 }
348 }
349
350 intc_subgroup_init(desc, d);
351
352 /* enable bits matching force_enable after registering irqs */
353 if (desc->force_enable)
354 intc_enable_disable_enum(desc, d, desc->force_enable, 1);
355
356 nr_intc_controllers++;
357
358 return 0;
359 err5:
360 kfree(d->prio);
361 err4:
362 #ifdef CONFIG_SMP
363 kfree(d->smp);
364 err3:
365 #endif
366 kfree(d->reg);
367 err2:
368 for (k = 0; k < d->nr_windows; k++)
369 if (d->window[k].virt)
370 iounmap(d->window[k].virt);
371
372 kfree(d->window);
373 err1:
374 kfree(d);
375 err0:
376 pr_err("unable to allocate INTC memory\n");
377
378 return -ENOMEM;
379 }
380
381 static int intc_suspend(void)
382 {
383 struct intc_desc_int *d;
384
385 list_for_each_entry(d, &intc_list, list) {
386 int irq;
387
388 /* enable wakeup irqs belonging to this intc controller */
389 for_each_active_irq(irq) {
390 struct irq_data *data;
391 struct irq_chip *chip;
392
393 data = irq_get_irq_data(irq);
394 chip = irq_data_get_irq_chip(data);
395 if (chip != &d->chip)
396 continue;
397 if (irqd_is_wakeup_set(data))
398 chip->irq_enable(data);
399 }
400 }
401 return 0;
402 }
403
404 static void intc_resume(void)
405 {
406 struct intc_desc_int *d;
407
408 list_for_each_entry(d, &intc_list, list) {
409 int irq;
410
411 for_each_active_irq(irq) {
412 struct irq_data *data;
413 struct irq_chip *chip;
414
415 data = irq_get_irq_data(irq);
416 chip = irq_data_get_irq_chip(data);
417 /*
418 * This will catch the redirect and VIRQ cases
419 * due to the dummy_irq_chip being inserted.
420 */
421 if (chip != &d->chip)
422 continue;
423 if (irqd_irq_disabled(data))
424 chip->irq_disable(data);
425 else
426 chip->irq_enable(data);
427 }
428 }
429 }
430
431 struct syscore_ops intc_syscore_ops = {
432 .suspend = intc_suspend,
433 .resume = intc_resume,
434 };
435
436 struct sysdev_class intc_sysdev_class = {
437 .name = "intc",
438 };
439
440 static ssize_t
441 show_intc_name(struct sys_device *dev, struct sysdev_attribute *attr, char *buf)
442 {
443 struct intc_desc_int *d;
444
445 d = container_of(dev, struct intc_desc_int, sysdev);
446
447 return sprintf(buf, "%s\n", d->chip.name);
448 }
449
450 static SYSDEV_ATTR(name, S_IRUGO, show_intc_name, NULL);
451
452 static int __init register_intc_sysdevs(void)
453 {
454 struct intc_desc_int *d;
455 int error;
456
457 register_syscore_ops(&intc_syscore_ops);
458
459 error = sysdev_class_register(&intc_sysdev_class);
460 if (!error) {
461 list_for_each_entry(d, &intc_list, list) {
462 d->sysdev.id = d->index;
463 d->sysdev.cls = &intc_sysdev_class;
464 error = sysdev_register(&d->sysdev);
465 if (error == 0)
466 error = sysdev_create_file(&d->sysdev,
467 &attr_name);
468 if (error)
469 break;
470 }
471 }
472
473 if (error)
474 pr_err("sysdev registration error\n");
475
476 return error;
477 }
478 device_initcall(register_intc_sysdevs);
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