Add linux-next specific files for 20110831
[linux-2.6/next.git] / drivers / spi / spi-pl022.c
blob078338f59481ad5068bae19640721fc0d15aa55e
1 /*
2 * A driver for the ARM PL022 PrimeCell SSP/SPI bus master.
4 * Copyright (C) 2008-2009 ST-Ericsson AB
5 * Copyright (C) 2006 STMicroelectronics Pvt. Ltd.
7 * Author: Linus Walleij <linus.walleij@stericsson.com>
9 * Initial version inspired by:
10 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
11 * Initial adoption to PL022 by:
12 * Sachin Verma <sachin.verma@st.com>
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/device.h>
28 #include <linux/ioport.h>
29 #include <linux/errno.h>
30 #include <linux/interrupt.h>
31 #include <linux/spi/spi.h>
32 #include <linux/workqueue.h>
33 #include <linux/delay.h>
34 #include <linux/clk.h>
35 #include <linux/err.h>
36 #include <linux/amba/bus.h>
37 #include <linux/amba/pl022.h>
38 #include <linux/io.h>
39 #include <linux/slab.h>
40 #include <linux/dmaengine.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/scatterlist.h>
43 #include <linux/pm_runtime.h>
46 * This macro is used to define some register default values.
47 * reg is masked with mask, the OR:ed with an (again masked)
48 * val shifted sb steps to the left.
50 #define SSP_WRITE_BITS(reg, val, mask, sb) \
51 ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask))))
54 * This macro is also used to define some default values.
55 * It will just shift val by sb steps to the left and mask
56 * the result with mask.
58 #define GEN_MASK_BITS(val, mask, sb) \
59 (((val)<<(sb)) & (mask))
61 #define DRIVE_TX 0
62 #define DO_NOT_DRIVE_TX 1
64 #define DO_NOT_QUEUE_DMA 0
65 #define QUEUE_DMA 1
67 #define RX_TRANSFER 1
68 #define TX_TRANSFER 2
71 * Macros to access SSP Registers with their offsets
73 #define SSP_CR0(r) (r + 0x000)
74 #define SSP_CR1(r) (r + 0x004)
75 #define SSP_DR(r) (r + 0x008)
76 #define SSP_SR(r) (r + 0x00C)
77 #define SSP_CPSR(r) (r + 0x010)
78 #define SSP_IMSC(r) (r + 0x014)
79 #define SSP_RIS(r) (r + 0x018)
80 #define SSP_MIS(r) (r + 0x01C)
81 #define SSP_ICR(r) (r + 0x020)
82 #define SSP_DMACR(r) (r + 0x024)
83 #define SSP_ITCR(r) (r + 0x080)
84 #define SSP_ITIP(r) (r + 0x084)
85 #define SSP_ITOP(r) (r + 0x088)
86 #define SSP_TDR(r) (r + 0x08C)
88 #define SSP_PID0(r) (r + 0xFE0)
89 #define SSP_PID1(r) (r + 0xFE4)
90 #define SSP_PID2(r) (r + 0xFE8)
91 #define SSP_PID3(r) (r + 0xFEC)
93 #define SSP_CID0(r) (r + 0xFF0)
94 #define SSP_CID1(r) (r + 0xFF4)
95 #define SSP_CID2(r) (r + 0xFF8)
96 #define SSP_CID3(r) (r + 0xFFC)
99 * SSP Control Register 0 - SSP_CR0
101 #define SSP_CR0_MASK_DSS (0x0FUL << 0)
102 #define SSP_CR0_MASK_FRF (0x3UL << 4)
103 #define SSP_CR0_MASK_SPO (0x1UL << 6)
104 #define SSP_CR0_MASK_SPH (0x1UL << 7)
105 #define SSP_CR0_MASK_SCR (0xFFUL << 8)
108 * The ST version of this block moves som bits
109 * in SSP_CR0 and extends it to 32 bits
111 #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0)
112 #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5)
113 #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16)
114 #define SSP_CR0_MASK_FRF_ST (0x3UL << 21)
118 * SSP Control Register 0 - SSP_CR1
120 #define SSP_CR1_MASK_LBM (0x1UL << 0)
121 #define SSP_CR1_MASK_SSE (0x1UL << 1)
122 #define SSP_CR1_MASK_MS (0x1UL << 2)
123 #define SSP_CR1_MASK_SOD (0x1UL << 3)
126 * The ST version of this block adds some bits
127 * in SSP_CR1
129 #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4)
130 #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5)
131 #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6)
132 #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7)
133 #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10)
134 /* This one is only in the PL023 variant */
135 #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13)
138 * SSP Status Register - SSP_SR
140 #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */
141 #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */
142 #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */
143 #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */
144 #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */
147 * SSP Clock Prescale Register - SSP_CPSR
149 #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0)
152 * SSP Interrupt Mask Set/Clear Register - SSP_IMSC
154 #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */
155 #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */
156 #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */
157 #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */
160 * SSP Raw Interrupt Status Register - SSP_RIS
162 /* Receive Overrun Raw Interrupt status */
163 #define SSP_RIS_MASK_RORRIS (0x1UL << 0)
164 /* Receive Timeout Raw Interrupt status */
165 #define SSP_RIS_MASK_RTRIS (0x1UL << 1)
166 /* Receive FIFO Raw Interrupt status */
167 #define SSP_RIS_MASK_RXRIS (0x1UL << 2)
168 /* Transmit FIFO Raw Interrupt status */
169 #define SSP_RIS_MASK_TXRIS (0x1UL << 3)
172 * SSP Masked Interrupt Status Register - SSP_MIS
174 /* Receive Overrun Masked Interrupt status */
175 #define SSP_MIS_MASK_RORMIS (0x1UL << 0)
176 /* Receive Timeout Masked Interrupt status */
177 #define SSP_MIS_MASK_RTMIS (0x1UL << 1)
178 /* Receive FIFO Masked Interrupt status */
179 #define SSP_MIS_MASK_RXMIS (0x1UL << 2)
180 /* Transmit FIFO Masked Interrupt status */
181 #define SSP_MIS_MASK_TXMIS (0x1UL << 3)
184 * SSP Interrupt Clear Register - SSP_ICR
186 /* Receive Overrun Raw Clear Interrupt bit */
187 #define SSP_ICR_MASK_RORIC (0x1UL << 0)
188 /* Receive Timeout Clear Interrupt bit */
189 #define SSP_ICR_MASK_RTIC (0x1UL << 1)
192 * SSP DMA Control Register - SSP_DMACR
194 /* Receive DMA Enable bit */
195 #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0)
196 /* Transmit DMA Enable bit */
197 #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1)
200 * SSP Integration Test control Register - SSP_ITCR
202 #define SSP_ITCR_MASK_ITEN (0x1UL << 0)
203 #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1)
206 * SSP Integration Test Input Register - SSP_ITIP
208 #define ITIP_MASK_SSPRXD (0x1UL << 0)
209 #define ITIP_MASK_SSPFSSIN (0x1UL << 1)
210 #define ITIP_MASK_SSPCLKIN (0x1UL << 2)
211 #define ITIP_MASK_RXDMAC (0x1UL << 3)
212 #define ITIP_MASK_TXDMAC (0x1UL << 4)
213 #define ITIP_MASK_SSPTXDIN (0x1UL << 5)
216 * SSP Integration Test output Register - SSP_ITOP
218 #define ITOP_MASK_SSPTXD (0x1UL << 0)
219 #define ITOP_MASK_SSPFSSOUT (0x1UL << 1)
220 #define ITOP_MASK_SSPCLKOUT (0x1UL << 2)
221 #define ITOP_MASK_SSPOEn (0x1UL << 3)
222 #define ITOP_MASK_SSPCTLOEn (0x1UL << 4)
223 #define ITOP_MASK_RORINTR (0x1UL << 5)
224 #define ITOP_MASK_RTINTR (0x1UL << 6)
225 #define ITOP_MASK_RXINTR (0x1UL << 7)
226 #define ITOP_MASK_TXINTR (0x1UL << 8)
227 #define ITOP_MASK_INTR (0x1UL << 9)
228 #define ITOP_MASK_RXDMABREQ (0x1UL << 10)
229 #define ITOP_MASK_RXDMASREQ (0x1UL << 11)
230 #define ITOP_MASK_TXDMABREQ (0x1UL << 12)
231 #define ITOP_MASK_TXDMASREQ (0x1UL << 13)
234 * SSP Test Data Register - SSP_TDR
236 #define TDR_MASK_TESTDATA (0xFFFFFFFF)
239 * Message State
240 * we use the spi_message.state (void *) pointer to
241 * hold a single state value, that's why all this
242 * (void *) casting is done here.
244 #define STATE_START ((void *) 0)
245 #define STATE_RUNNING ((void *) 1)
246 #define STATE_DONE ((void *) 2)
247 #define STATE_ERROR ((void *) -1)
250 * SSP State - Whether Enabled or Disabled
252 #define SSP_DISABLED (0)
253 #define SSP_ENABLED (1)
256 * SSP DMA State - Whether DMA Enabled or Disabled
258 #define SSP_DMA_DISABLED (0)
259 #define SSP_DMA_ENABLED (1)
262 * SSP Clock Defaults
264 #define SSP_DEFAULT_CLKRATE 0x2
265 #define SSP_DEFAULT_PRESCALE 0x40
268 * SSP Clock Parameter ranges
270 #define CPSDVR_MIN 0x02
271 #define CPSDVR_MAX 0xFE
272 #define SCR_MIN 0x00
273 #define SCR_MAX 0xFF
276 * SSP Interrupt related Macros
278 #define DEFAULT_SSP_REG_IMSC 0x0UL
279 #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC
280 #define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC)
282 #define CLEAR_ALL_INTERRUPTS 0x3
284 #define SPI_POLLING_TIMEOUT 1000
288 * The type of reading going on on this chip
290 enum ssp_reading {
291 READING_NULL,
292 READING_U8,
293 READING_U16,
294 READING_U32
298 * The type of writing going on on this chip
300 enum ssp_writing {
301 WRITING_NULL,
302 WRITING_U8,
303 WRITING_U16,
304 WRITING_U32
308 * struct vendor_data - vendor-specific config parameters
309 * for PL022 derivates
310 * @fifodepth: depth of FIFOs (both)
311 * @max_bpw: maximum number of bits per word
312 * @unidir: supports unidirection transfers
313 * @extended_cr: 32 bit wide control register 0 with extra
314 * features and extra features in CR1 as found in the ST variants
315 * @pl023: supports a subset of the ST extensions called "PL023"
317 struct vendor_data {
318 int fifodepth;
319 int max_bpw;
320 bool unidir;
321 bool extended_cr;
322 bool pl023;
323 bool loopback;
327 * struct pl022 - This is the private SSP driver data structure
328 * @adev: AMBA device model hookup
329 * @vendor: vendor data for the IP block
330 * @phybase: the physical memory where the SSP device resides
331 * @virtbase: the virtual memory where the SSP is mapped
332 * @clk: outgoing clock "SPICLK" for the SPI bus
333 * @master: SPI framework hookup
334 * @master_info: controller-specific data from machine setup
335 * @workqueue: a workqueue on which any spi_message request is queued
336 * @pump_messages: work struct for scheduling work to the workqueue
337 * @queue_lock: spinlock to syncronise access to message queue
338 * @queue: message queue
339 * @busy: workqueue is busy
340 * @running: workqueue is running
341 * @pump_transfers: Tasklet used in Interrupt Transfer mode
342 * @cur_msg: Pointer to current spi_message being processed
343 * @cur_transfer: Pointer to current spi_transfer
344 * @cur_chip: pointer to current clients chip(assigned from controller_state)
345 * @tx: current position in TX buffer to be read
346 * @tx_end: end position in TX buffer to be read
347 * @rx: current position in RX buffer to be written
348 * @rx_end: end position in RX buffer to be written
349 * @read: the type of read currently going on
350 * @write: the type of write currently going on
351 * @exp_fifo_level: expected FIFO level
352 * @dma_rx_channel: optional channel for RX DMA
353 * @dma_tx_channel: optional channel for TX DMA
354 * @sgt_rx: scattertable for the RX transfer
355 * @sgt_tx: scattertable for the TX transfer
356 * @dummypage: a dummy page used for driving data on the bus with DMA
358 struct pl022 {
359 struct amba_device *adev;
360 struct vendor_data *vendor;
361 resource_size_t phybase;
362 void __iomem *virtbase;
363 struct clk *clk;
364 struct spi_master *master;
365 struct pl022_ssp_controller *master_info;
366 /* Driver message queue */
367 struct workqueue_struct *workqueue;
368 struct work_struct pump_messages;
369 spinlock_t queue_lock;
370 struct list_head queue;
371 bool busy;
372 bool running;
373 /* Message transfer pump */
374 struct tasklet_struct pump_transfers;
375 struct spi_message *cur_msg;
376 struct spi_transfer *cur_transfer;
377 struct chip_data *cur_chip;
378 void *tx;
379 void *tx_end;
380 void *rx;
381 void *rx_end;
382 enum ssp_reading read;
383 enum ssp_writing write;
384 u32 exp_fifo_level;
385 enum ssp_rx_level_trig rx_lev_trig;
386 enum ssp_tx_level_trig tx_lev_trig;
387 /* DMA settings */
388 #ifdef CONFIG_DMA_ENGINE
389 struct dma_chan *dma_rx_channel;
390 struct dma_chan *dma_tx_channel;
391 struct sg_table sgt_rx;
392 struct sg_table sgt_tx;
393 char *dummypage;
394 #endif
398 * struct chip_data - To maintain runtime state of SSP for each client chip
399 * @cr0: Value of control register CR0 of SSP - on later ST variants this
400 * register is 32 bits wide rather than just 16
401 * @cr1: Value of control register CR1 of SSP
402 * @dmacr: Value of DMA control Register of SSP
403 * @cpsr: Value of Clock prescale register
404 * @n_bytes: how many bytes(power of 2) reqd for a given data width of client
405 * @enable_dma: Whether to enable DMA or not
406 * @read: function ptr to be used to read when doing xfer for this chip
407 * @write: function ptr to be used to write when doing xfer for this chip
408 * @cs_control: chip select callback provided by chip
409 * @xfer_type: polling/interrupt/DMA
411 * Runtime state of the SSP controller, maintained per chip,
412 * This would be set according to the current message that would be served
414 struct chip_data {
415 u32 cr0;
416 u16 cr1;
417 u16 dmacr;
418 u16 cpsr;
419 u8 n_bytes;
420 bool enable_dma;
421 enum ssp_reading read;
422 enum ssp_writing write;
423 void (*cs_control) (u32 command);
424 int xfer_type;
428 * null_cs_control - Dummy chip select function
429 * @command: select/delect the chip
431 * If no chip select function is provided by client this is used as dummy
432 * chip select
434 static void null_cs_control(u32 command)
436 pr_debug("pl022: dummy chip select control, CS=0x%x\n", command);
440 * giveback - current spi_message is over, schedule next message and call
441 * callback of this message. Assumes that caller already
442 * set message->status; dma and pio irqs are blocked
443 * @pl022: SSP driver private data structure
445 static void giveback(struct pl022 *pl022)
447 struct spi_transfer *last_transfer;
448 unsigned long flags;
449 struct spi_message *msg;
450 void (*curr_cs_control) (u32 command);
453 * This local reference to the chip select function
454 * is needed because we set curr_chip to NULL
455 * as a step toward termininating the message.
457 curr_cs_control = pl022->cur_chip->cs_control;
458 spin_lock_irqsave(&pl022->queue_lock, flags);
459 msg = pl022->cur_msg;
460 pl022->cur_msg = NULL;
461 pl022->cur_transfer = NULL;
462 pl022->cur_chip = NULL;
463 queue_work(pl022->workqueue, &pl022->pump_messages);
464 spin_unlock_irqrestore(&pl022->queue_lock, flags);
466 last_transfer = list_entry(msg->transfers.prev,
467 struct spi_transfer,
468 transfer_list);
470 /* Delay if requested before any change in chip select */
471 if (last_transfer->delay_usecs)
473 * FIXME: This runs in interrupt context.
474 * Is this really smart?
476 udelay(last_transfer->delay_usecs);
479 * Drop chip select UNLESS cs_change is true or we are returning
480 * a message with an error, or next message is for another chip
482 if (!last_transfer->cs_change)
483 curr_cs_control(SSP_CHIP_DESELECT);
484 else {
485 struct spi_message *next_msg;
487 /* Holding of cs was hinted, but we need to make sure
488 * the next message is for the same chip. Don't waste
489 * time with the following tests unless this was hinted.
491 * We cannot postpone this until pump_messages, because
492 * after calling msg->complete (below) the driver that
493 * sent the current message could be unloaded, which
494 * could invalidate the cs_control() callback...
497 /* get a pointer to the next message, if any */
498 spin_lock_irqsave(&pl022->queue_lock, flags);
499 if (list_empty(&pl022->queue))
500 next_msg = NULL;
501 else
502 next_msg = list_entry(pl022->queue.next,
503 struct spi_message, queue);
504 spin_unlock_irqrestore(&pl022->queue_lock, flags);
506 /* see if the next and current messages point
507 * to the same chip
509 if (next_msg && next_msg->spi != msg->spi)
510 next_msg = NULL;
511 if (!next_msg || msg->state == STATE_ERROR)
512 curr_cs_control(SSP_CHIP_DESELECT);
514 msg->state = NULL;
515 if (msg->complete)
516 msg->complete(msg->context);
517 /* This message is completed, so let's turn off the clocks & power */
518 pm_runtime_put(&pl022->adev->dev);
522 * flush - flush the FIFO to reach a clean state
523 * @pl022: SSP driver private data structure
525 static int flush(struct pl022 *pl022)
527 unsigned long limit = loops_per_jiffy << 1;
529 dev_dbg(&pl022->adev->dev, "flush\n");
530 do {
531 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
532 readw(SSP_DR(pl022->virtbase));
533 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--);
535 pl022->exp_fifo_level = 0;
537 return limit;
541 * restore_state - Load configuration of current chip
542 * @pl022: SSP driver private data structure
544 static void restore_state(struct pl022 *pl022)
546 struct chip_data *chip = pl022->cur_chip;
548 if (pl022->vendor->extended_cr)
549 writel(chip->cr0, SSP_CR0(pl022->virtbase));
550 else
551 writew(chip->cr0, SSP_CR0(pl022->virtbase));
552 writew(chip->cr1, SSP_CR1(pl022->virtbase));
553 writew(chip->dmacr, SSP_DMACR(pl022->virtbase));
554 writew(chip->cpsr, SSP_CPSR(pl022->virtbase));
555 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
556 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
560 * Default SSP Register Values
562 #define DEFAULT_SSP_REG_CR0 ( \
563 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \
564 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \
565 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
566 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
567 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
570 /* ST versions have slightly different bit layout */
571 #define DEFAULT_SSP_REG_CR0_ST ( \
572 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
573 GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \
574 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
575 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
576 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \
577 GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \
578 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \
581 /* The PL023 version is slightly different again */
582 #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \
583 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
584 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
585 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
586 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
589 #define DEFAULT_SSP_REG_CR1 ( \
590 GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \
591 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
592 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
593 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \
596 /* ST versions extend this register to use all 16 bits */
597 #define DEFAULT_SSP_REG_CR1_ST ( \
598 DEFAULT_SSP_REG_CR1 | \
599 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
600 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
601 GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\
602 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
603 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \
607 * The PL023 variant has further differences: no loopback mode, no microwire
608 * support, and a new clock feedback delay setting.
610 #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \
611 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
612 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
613 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \
614 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
615 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
616 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
617 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \
618 GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \
621 #define DEFAULT_SSP_REG_CPSR ( \
622 GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \
625 #define DEFAULT_SSP_REG_DMACR (\
626 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \
627 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \
631 * load_ssp_default_config - Load default configuration for SSP
632 * @pl022: SSP driver private data structure
634 static void load_ssp_default_config(struct pl022 *pl022)
636 if (pl022->vendor->pl023) {
637 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase));
638 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase));
639 } else if (pl022->vendor->extended_cr) {
640 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase));
641 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase));
642 } else {
643 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase));
644 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase));
646 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase));
647 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase));
648 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
649 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
653 * This will write to TX and read from RX according to the parameters
654 * set in pl022.
656 static void readwriter(struct pl022 *pl022)
660 * The FIFO depth is different between primecell variants.
661 * I believe filling in too much in the FIFO might cause
662 * errons in 8bit wide transfers on ARM variants (just 8 words
663 * FIFO, means only 8x8 = 64 bits in FIFO) at least.
665 * To prevent this issue, the TX FIFO is only filled to the
666 * unused RX FIFO fill length, regardless of what the TX
667 * FIFO status flag indicates.
669 dev_dbg(&pl022->adev->dev,
670 "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n",
671 __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end);
673 /* Read as much as you can */
674 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
675 && (pl022->rx < pl022->rx_end)) {
676 switch (pl022->read) {
677 case READING_NULL:
678 readw(SSP_DR(pl022->virtbase));
679 break;
680 case READING_U8:
681 *(u8 *) (pl022->rx) =
682 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
683 break;
684 case READING_U16:
685 *(u16 *) (pl022->rx) =
686 (u16) readw(SSP_DR(pl022->virtbase));
687 break;
688 case READING_U32:
689 *(u32 *) (pl022->rx) =
690 readl(SSP_DR(pl022->virtbase));
691 break;
693 pl022->rx += (pl022->cur_chip->n_bytes);
694 pl022->exp_fifo_level--;
697 * Write as much as possible up to the RX FIFO size
699 while ((pl022->exp_fifo_level < pl022->vendor->fifodepth)
700 && (pl022->tx < pl022->tx_end)) {
701 switch (pl022->write) {
702 case WRITING_NULL:
703 writew(0x0, SSP_DR(pl022->virtbase));
704 break;
705 case WRITING_U8:
706 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase));
707 break;
708 case WRITING_U16:
709 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase));
710 break;
711 case WRITING_U32:
712 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase));
713 break;
715 pl022->tx += (pl022->cur_chip->n_bytes);
716 pl022->exp_fifo_level++;
718 * This inner reader takes care of things appearing in the RX
719 * FIFO as we're transmitting. This will happen a lot since the
720 * clock starts running when you put things into the TX FIFO,
721 * and then things are continuously clocked into the RX FIFO.
723 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
724 && (pl022->rx < pl022->rx_end)) {
725 switch (pl022->read) {
726 case READING_NULL:
727 readw(SSP_DR(pl022->virtbase));
728 break;
729 case READING_U8:
730 *(u8 *) (pl022->rx) =
731 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
732 break;
733 case READING_U16:
734 *(u16 *) (pl022->rx) =
735 (u16) readw(SSP_DR(pl022->virtbase));
736 break;
737 case READING_U32:
738 *(u32 *) (pl022->rx) =
739 readl(SSP_DR(pl022->virtbase));
740 break;
742 pl022->rx += (pl022->cur_chip->n_bytes);
743 pl022->exp_fifo_level--;
747 * When we exit here the TX FIFO should be full and the RX FIFO
748 * should be empty
754 * next_transfer - Move to the Next transfer in the current spi message
755 * @pl022: SSP driver private data structure
757 * This function moves though the linked list of spi transfers in the
758 * current spi message and returns with the state of current spi
759 * message i.e whether its last transfer is done(STATE_DONE) or
760 * Next transfer is ready(STATE_RUNNING)
762 static void *next_transfer(struct pl022 *pl022)
764 struct spi_message *msg = pl022->cur_msg;
765 struct spi_transfer *trans = pl022->cur_transfer;
767 /* Move to next transfer */
768 if (trans->transfer_list.next != &msg->transfers) {
769 pl022->cur_transfer =
770 list_entry(trans->transfer_list.next,
771 struct spi_transfer, transfer_list);
772 return STATE_RUNNING;
774 return STATE_DONE;
778 * This DMA functionality is only compiled in if we have
779 * access to the generic DMA devices/DMA engine.
781 #ifdef CONFIG_DMA_ENGINE
782 static void unmap_free_dma_scatter(struct pl022 *pl022)
784 /* Unmap and free the SG tables */
785 dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl,
786 pl022->sgt_tx.nents, DMA_TO_DEVICE);
787 dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl,
788 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
789 sg_free_table(&pl022->sgt_rx);
790 sg_free_table(&pl022->sgt_tx);
793 static void dma_callback(void *data)
795 struct pl022 *pl022 = data;
796 struct spi_message *msg = pl022->cur_msg;
798 BUG_ON(!pl022->sgt_rx.sgl);
800 #ifdef VERBOSE_DEBUG
802 * Optionally dump out buffers to inspect contents, this is
803 * good if you want to convince yourself that the loopback
804 * read/write contents are the same, when adopting to a new
805 * DMA engine.
808 struct scatterlist *sg;
809 unsigned int i;
811 dma_sync_sg_for_cpu(&pl022->adev->dev,
812 pl022->sgt_rx.sgl,
813 pl022->sgt_rx.nents,
814 DMA_FROM_DEVICE);
816 for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) {
817 dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i);
818 print_hex_dump(KERN_ERR, "SPI RX: ",
819 DUMP_PREFIX_OFFSET,
822 sg_virt(sg),
823 sg_dma_len(sg),
826 for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) {
827 dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i);
828 print_hex_dump(KERN_ERR, "SPI TX: ",
829 DUMP_PREFIX_OFFSET,
832 sg_virt(sg),
833 sg_dma_len(sg),
837 #endif
839 unmap_free_dma_scatter(pl022);
841 /* Update total bytes transferred */
842 msg->actual_length += pl022->cur_transfer->len;
843 if (pl022->cur_transfer->cs_change)
844 pl022->cur_chip->
845 cs_control(SSP_CHIP_DESELECT);
847 /* Move to next transfer */
848 msg->state = next_transfer(pl022);
849 tasklet_schedule(&pl022->pump_transfers);
852 static void setup_dma_scatter(struct pl022 *pl022,
853 void *buffer,
854 unsigned int length,
855 struct sg_table *sgtab)
857 struct scatterlist *sg;
858 int bytesleft = length;
859 void *bufp = buffer;
860 int mapbytes;
861 int i;
863 if (buffer) {
864 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
866 * If there are less bytes left than what fits
867 * in the current page (plus page alignment offset)
868 * we just feed in this, else we stuff in as much
869 * as we can.
871 if (bytesleft < (PAGE_SIZE - offset_in_page(bufp)))
872 mapbytes = bytesleft;
873 else
874 mapbytes = PAGE_SIZE - offset_in_page(bufp);
875 sg_set_page(sg, virt_to_page(bufp),
876 mapbytes, offset_in_page(bufp));
877 bufp += mapbytes;
878 bytesleft -= mapbytes;
879 dev_dbg(&pl022->adev->dev,
880 "set RX/TX target page @ %p, %d bytes, %d left\n",
881 bufp, mapbytes, bytesleft);
883 } else {
884 /* Map the dummy buffer on every page */
885 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
886 if (bytesleft < PAGE_SIZE)
887 mapbytes = bytesleft;
888 else
889 mapbytes = PAGE_SIZE;
890 sg_set_page(sg, virt_to_page(pl022->dummypage),
891 mapbytes, 0);
892 bytesleft -= mapbytes;
893 dev_dbg(&pl022->adev->dev,
894 "set RX/TX to dummy page %d bytes, %d left\n",
895 mapbytes, bytesleft);
899 BUG_ON(bytesleft);
903 * configure_dma - configures the channels for the next transfer
904 * @pl022: SSP driver's private data structure
906 static int configure_dma(struct pl022 *pl022)
908 struct dma_slave_config rx_conf = {
909 .src_addr = SSP_DR(pl022->phybase),
910 .direction = DMA_FROM_DEVICE,
912 struct dma_slave_config tx_conf = {
913 .dst_addr = SSP_DR(pl022->phybase),
914 .direction = DMA_TO_DEVICE,
916 unsigned int pages;
917 int ret;
918 int rx_sglen, tx_sglen;
919 struct dma_chan *rxchan = pl022->dma_rx_channel;
920 struct dma_chan *txchan = pl022->dma_tx_channel;
921 struct dma_async_tx_descriptor *rxdesc;
922 struct dma_async_tx_descriptor *txdesc;
924 /* Check that the channels are available */
925 if (!rxchan || !txchan)
926 return -ENODEV;
929 * If supplied, the DMA burstsize should equal the FIFO trigger level.
930 * Notice that the DMA engine uses one-to-one mapping. Since we can
931 * not trigger on 2 elements this needs explicit mapping rather than
932 * calculation.
934 switch (pl022->rx_lev_trig) {
935 case SSP_RX_1_OR_MORE_ELEM:
936 rx_conf.src_maxburst = 1;
937 break;
938 case SSP_RX_4_OR_MORE_ELEM:
939 rx_conf.src_maxburst = 4;
940 break;
941 case SSP_RX_8_OR_MORE_ELEM:
942 rx_conf.src_maxburst = 8;
943 break;
944 case SSP_RX_16_OR_MORE_ELEM:
945 rx_conf.src_maxburst = 16;
946 break;
947 case SSP_RX_32_OR_MORE_ELEM:
948 rx_conf.src_maxburst = 32;
949 break;
950 default:
951 rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1;
952 break;
955 switch (pl022->tx_lev_trig) {
956 case SSP_TX_1_OR_MORE_EMPTY_LOC:
957 tx_conf.dst_maxburst = 1;
958 break;
959 case SSP_TX_4_OR_MORE_EMPTY_LOC:
960 tx_conf.dst_maxburst = 4;
961 break;
962 case SSP_TX_8_OR_MORE_EMPTY_LOC:
963 tx_conf.dst_maxburst = 8;
964 break;
965 case SSP_TX_16_OR_MORE_EMPTY_LOC:
966 tx_conf.dst_maxburst = 16;
967 break;
968 case SSP_TX_32_OR_MORE_EMPTY_LOC:
969 tx_conf.dst_maxburst = 32;
970 break;
971 default:
972 tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1;
973 break;
976 switch (pl022->read) {
977 case READING_NULL:
978 /* Use the same as for writing */
979 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
980 break;
981 case READING_U8:
982 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
983 break;
984 case READING_U16:
985 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
986 break;
987 case READING_U32:
988 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
989 break;
992 switch (pl022->write) {
993 case WRITING_NULL:
994 /* Use the same as for reading */
995 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
996 break;
997 case WRITING_U8:
998 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
999 break;
1000 case WRITING_U16:
1001 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1002 break;
1003 case WRITING_U32:
1004 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1005 break;
1008 /* SPI pecularity: we need to read and write the same width */
1009 if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
1010 rx_conf.src_addr_width = tx_conf.dst_addr_width;
1011 if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
1012 tx_conf.dst_addr_width = rx_conf.src_addr_width;
1013 BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width);
1015 dmaengine_slave_config(rxchan, &rx_conf);
1016 dmaengine_slave_config(txchan, &tx_conf);
1018 /* Create sglists for the transfers */
1019 pages = (pl022->cur_transfer->len >> PAGE_SHIFT) + 1;
1020 dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages);
1022 ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_KERNEL);
1023 if (ret)
1024 goto err_alloc_rx_sg;
1026 ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_KERNEL);
1027 if (ret)
1028 goto err_alloc_tx_sg;
1030 /* Fill in the scatterlists for the RX+TX buffers */
1031 setup_dma_scatter(pl022, pl022->rx,
1032 pl022->cur_transfer->len, &pl022->sgt_rx);
1033 setup_dma_scatter(pl022, pl022->tx,
1034 pl022->cur_transfer->len, &pl022->sgt_tx);
1036 /* Map DMA buffers */
1037 rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
1038 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
1039 if (!rx_sglen)
1040 goto err_rx_sgmap;
1042 tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl,
1043 pl022->sgt_tx.nents, DMA_TO_DEVICE);
1044 if (!tx_sglen)
1045 goto err_tx_sgmap;
1047 /* Send both scatterlists */
1048 rxdesc = rxchan->device->device_prep_slave_sg(rxchan,
1049 pl022->sgt_rx.sgl,
1050 rx_sglen,
1051 DMA_FROM_DEVICE,
1052 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1053 if (!rxdesc)
1054 goto err_rxdesc;
1056 txdesc = txchan->device->device_prep_slave_sg(txchan,
1057 pl022->sgt_tx.sgl,
1058 tx_sglen,
1059 DMA_TO_DEVICE,
1060 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1061 if (!txdesc)
1062 goto err_txdesc;
1064 /* Put the callback on the RX transfer only, that should finish last */
1065 rxdesc->callback = dma_callback;
1066 rxdesc->callback_param = pl022;
1068 /* Submit and fire RX and TX with TX last so we're ready to read! */
1069 dmaengine_submit(rxdesc);
1070 dmaengine_submit(txdesc);
1071 dma_async_issue_pending(rxchan);
1072 dma_async_issue_pending(txchan);
1074 return 0;
1076 err_txdesc:
1077 dmaengine_terminate_all(txchan);
1078 err_rxdesc:
1079 dmaengine_terminate_all(rxchan);
1080 dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl,
1081 pl022->sgt_tx.nents, DMA_TO_DEVICE);
1082 err_tx_sgmap:
1083 dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
1084 pl022->sgt_tx.nents, DMA_FROM_DEVICE);
1085 err_rx_sgmap:
1086 sg_free_table(&pl022->sgt_tx);
1087 err_alloc_tx_sg:
1088 sg_free_table(&pl022->sgt_rx);
1089 err_alloc_rx_sg:
1090 return -ENOMEM;
1093 static int __init pl022_dma_probe(struct pl022 *pl022)
1095 dma_cap_mask_t mask;
1097 /* Try to acquire a generic DMA engine slave channel */
1098 dma_cap_zero(mask);
1099 dma_cap_set(DMA_SLAVE, mask);
1101 * We need both RX and TX channels to do DMA, else do none
1102 * of them.
1104 pl022->dma_rx_channel = dma_request_channel(mask,
1105 pl022->master_info->dma_filter,
1106 pl022->master_info->dma_rx_param);
1107 if (!pl022->dma_rx_channel) {
1108 dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n");
1109 goto err_no_rxchan;
1112 pl022->dma_tx_channel = dma_request_channel(mask,
1113 pl022->master_info->dma_filter,
1114 pl022->master_info->dma_tx_param);
1115 if (!pl022->dma_tx_channel) {
1116 dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n");
1117 goto err_no_txchan;
1120 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
1121 if (!pl022->dummypage) {
1122 dev_dbg(&pl022->adev->dev, "no DMA dummypage!\n");
1123 goto err_no_dummypage;
1126 dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n",
1127 dma_chan_name(pl022->dma_rx_channel),
1128 dma_chan_name(pl022->dma_tx_channel));
1130 return 0;
1132 err_no_dummypage:
1133 dma_release_channel(pl022->dma_tx_channel);
1134 err_no_txchan:
1135 dma_release_channel(pl022->dma_rx_channel);
1136 pl022->dma_rx_channel = NULL;
1137 err_no_rxchan:
1138 dev_err(&pl022->adev->dev,
1139 "Failed to work in dma mode, work without dma!\n");
1140 return -ENODEV;
1143 static void terminate_dma(struct pl022 *pl022)
1145 struct dma_chan *rxchan = pl022->dma_rx_channel;
1146 struct dma_chan *txchan = pl022->dma_tx_channel;
1148 dmaengine_terminate_all(rxchan);
1149 dmaengine_terminate_all(txchan);
1150 unmap_free_dma_scatter(pl022);
1153 static void pl022_dma_remove(struct pl022 *pl022)
1155 if (pl022->busy)
1156 terminate_dma(pl022);
1157 if (pl022->dma_tx_channel)
1158 dma_release_channel(pl022->dma_tx_channel);
1159 if (pl022->dma_rx_channel)
1160 dma_release_channel(pl022->dma_rx_channel);
1161 kfree(pl022->dummypage);
1164 #else
1165 static inline int configure_dma(struct pl022 *pl022)
1167 return -ENODEV;
1170 static inline int pl022_dma_probe(struct pl022 *pl022)
1172 return 0;
1175 static inline void pl022_dma_remove(struct pl022 *pl022)
1178 #endif
1181 * pl022_interrupt_handler - Interrupt handler for SSP controller
1183 * This function handles interrupts generated for an interrupt based transfer.
1184 * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the
1185 * current message's state as STATE_ERROR and schedule the tasklet
1186 * pump_transfers which will do the postprocessing of the current message by
1187 * calling giveback(). Otherwise it reads data from RX FIFO till there is no
1188 * more data, and writes data in TX FIFO till it is not full. If we complete
1189 * the transfer we move to the next transfer and schedule the tasklet.
1191 static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id)
1193 struct pl022 *pl022 = dev_id;
1194 struct spi_message *msg = pl022->cur_msg;
1195 u16 irq_status = 0;
1196 u16 flag = 0;
1198 if (unlikely(!msg)) {
1199 dev_err(&pl022->adev->dev,
1200 "bad message state in interrupt handler");
1201 /* Never fail */
1202 return IRQ_HANDLED;
1205 /* Read the Interrupt Status Register */
1206 irq_status = readw(SSP_MIS(pl022->virtbase));
1208 if (unlikely(!irq_status))
1209 return IRQ_NONE;
1212 * This handles the FIFO interrupts, the timeout
1213 * interrupts are flatly ignored, they cannot be
1214 * trusted.
1216 if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) {
1218 * Overrun interrupt - bail out since our Data has been
1219 * corrupted
1221 dev_err(&pl022->adev->dev, "FIFO overrun\n");
1222 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF)
1223 dev_err(&pl022->adev->dev,
1224 "RXFIFO is full\n");
1225 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF)
1226 dev_err(&pl022->adev->dev,
1227 "TXFIFO is full\n");
1230 * Disable and clear interrupts, disable SSP,
1231 * mark message with bad status so it can be
1232 * retried.
1234 writew(DISABLE_ALL_INTERRUPTS,
1235 SSP_IMSC(pl022->virtbase));
1236 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1237 writew((readw(SSP_CR1(pl022->virtbase)) &
1238 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
1239 msg->state = STATE_ERROR;
1241 /* Schedule message queue handler */
1242 tasklet_schedule(&pl022->pump_transfers);
1243 return IRQ_HANDLED;
1246 readwriter(pl022);
1248 if ((pl022->tx == pl022->tx_end) && (flag == 0)) {
1249 flag = 1;
1250 /* Disable Transmit interrupt */
1251 writew(readw(SSP_IMSC(pl022->virtbase)) &
1252 (~SSP_IMSC_MASK_TXIM),
1253 SSP_IMSC(pl022->virtbase));
1257 * Since all transactions must write as much as shall be read,
1258 * we can conclude the entire transaction once RX is complete.
1259 * At this point, all TX will always be finished.
1261 if (pl022->rx >= pl022->rx_end) {
1262 writew(DISABLE_ALL_INTERRUPTS,
1263 SSP_IMSC(pl022->virtbase));
1264 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1265 if (unlikely(pl022->rx > pl022->rx_end)) {
1266 dev_warn(&pl022->adev->dev, "read %u surplus "
1267 "bytes (did you request an odd "
1268 "number of bytes on a 16bit bus?)\n",
1269 (u32) (pl022->rx - pl022->rx_end));
1271 /* Update total bytes transferred */
1272 msg->actual_length += pl022->cur_transfer->len;
1273 if (pl022->cur_transfer->cs_change)
1274 pl022->cur_chip->
1275 cs_control(SSP_CHIP_DESELECT);
1276 /* Move to next transfer */
1277 msg->state = next_transfer(pl022);
1278 tasklet_schedule(&pl022->pump_transfers);
1279 return IRQ_HANDLED;
1282 return IRQ_HANDLED;
1286 * This sets up the pointers to memory for the next message to
1287 * send out on the SPI bus.
1289 static int set_up_next_transfer(struct pl022 *pl022,
1290 struct spi_transfer *transfer)
1292 int residue;
1294 /* Sanity check the message for this bus width */
1295 residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes;
1296 if (unlikely(residue != 0)) {
1297 dev_err(&pl022->adev->dev,
1298 "message of %u bytes to transmit but the current "
1299 "chip bus has a data width of %u bytes!\n",
1300 pl022->cur_transfer->len,
1301 pl022->cur_chip->n_bytes);
1302 dev_err(&pl022->adev->dev, "skipping this message\n");
1303 return -EIO;
1305 pl022->tx = (void *)transfer->tx_buf;
1306 pl022->tx_end = pl022->tx + pl022->cur_transfer->len;
1307 pl022->rx = (void *)transfer->rx_buf;
1308 pl022->rx_end = pl022->rx + pl022->cur_transfer->len;
1309 pl022->write =
1310 pl022->tx ? pl022->cur_chip->write : WRITING_NULL;
1311 pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL;
1312 return 0;
1316 * pump_transfers - Tasklet function which schedules next transfer
1317 * when running in interrupt or DMA transfer mode.
1318 * @data: SSP driver private data structure
1321 static void pump_transfers(unsigned long data)
1323 struct pl022 *pl022 = (struct pl022 *) data;
1324 struct spi_message *message = NULL;
1325 struct spi_transfer *transfer = NULL;
1326 struct spi_transfer *previous = NULL;
1328 /* Get current state information */
1329 message = pl022->cur_msg;
1330 transfer = pl022->cur_transfer;
1332 /* Handle for abort */
1333 if (message->state == STATE_ERROR) {
1334 message->status = -EIO;
1335 giveback(pl022);
1336 return;
1339 /* Handle end of message */
1340 if (message->state == STATE_DONE) {
1341 message->status = 0;
1342 giveback(pl022);
1343 return;
1346 /* Delay if requested at end of transfer before CS change */
1347 if (message->state == STATE_RUNNING) {
1348 previous = list_entry(transfer->transfer_list.prev,
1349 struct spi_transfer,
1350 transfer_list);
1351 if (previous->delay_usecs)
1353 * FIXME: This runs in interrupt context.
1354 * Is this really smart?
1356 udelay(previous->delay_usecs);
1358 /* Drop chip select only if cs_change is requested */
1359 if (previous->cs_change)
1360 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
1361 } else {
1362 /* STATE_START */
1363 message->state = STATE_RUNNING;
1366 if (set_up_next_transfer(pl022, transfer)) {
1367 message->state = STATE_ERROR;
1368 message->status = -EIO;
1369 giveback(pl022);
1370 return;
1372 /* Flush the FIFOs and let's go! */
1373 flush(pl022);
1375 if (pl022->cur_chip->enable_dma) {
1376 if (configure_dma(pl022)) {
1377 dev_dbg(&pl022->adev->dev,
1378 "configuration of DMA failed, fall back to interrupt mode\n");
1379 goto err_config_dma;
1381 return;
1384 err_config_dma:
1385 writew(ENABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
1388 static void do_interrupt_dma_transfer(struct pl022 *pl022)
1390 u32 irqflags = ENABLE_ALL_INTERRUPTS;
1392 /* Enable target chip */
1393 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
1394 if (set_up_next_transfer(pl022, pl022->cur_transfer)) {
1395 /* Error path */
1396 pl022->cur_msg->state = STATE_ERROR;
1397 pl022->cur_msg->status = -EIO;
1398 giveback(pl022);
1399 return;
1401 /* If we're using DMA, set up DMA here */
1402 if (pl022->cur_chip->enable_dma) {
1403 /* Configure DMA transfer */
1404 if (configure_dma(pl022)) {
1405 dev_dbg(&pl022->adev->dev,
1406 "configuration of DMA failed, fall back to interrupt mode\n");
1407 goto err_config_dma;
1409 /* Disable interrupts in DMA mode, IRQ from DMA controller */
1410 irqflags = DISABLE_ALL_INTERRUPTS;
1412 err_config_dma:
1413 /* Enable SSP, turn on interrupts */
1414 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1415 SSP_CR1(pl022->virtbase));
1416 writew(irqflags, SSP_IMSC(pl022->virtbase));
1419 static void do_polling_transfer(struct pl022 *pl022)
1421 struct spi_message *message = NULL;
1422 struct spi_transfer *transfer = NULL;
1423 struct spi_transfer *previous = NULL;
1424 struct chip_data *chip;
1425 unsigned long time, timeout;
1427 chip = pl022->cur_chip;
1428 message = pl022->cur_msg;
1430 while (message->state != STATE_DONE) {
1431 /* Handle for abort */
1432 if (message->state == STATE_ERROR)
1433 break;
1434 transfer = pl022->cur_transfer;
1436 /* Delay if requested at end of transfer */
1437 if (message->state == STATE_RUNNING) {
1438 previous =
1439 list_entry(transfer->transfer_list.prev,
1440 struct spi_transfer, transfer_list);
1441 if (previous->delay_usecs)
1442 udelay(previous->delay_usecs);
1443 if (previous->cs_change)
1444 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
1445 } else {
1446 /* STATE_START */
1447 message->state = STATE_RUNNING;
1448 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
1451 /* Configuration Changing Per Transfer */
1452 if (set_up_next_transfer(pl022, transfer)) {
1453 /* Error path */
1454 message->state = STATE_ERROR;
1455 break;
1457 /* Flush FIFOs and enable SSP */
1458 flush(pl022);
1459 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1460 SSP_CR1(pl022->virtbase));
1462 dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n");
1464 timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT);
1465 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) {
1466 time = jiffies;
1467 readwriter(pl022);
1468 if (time_after(time, timeout)) {
1469 dev_warn(&pl022->adev->dev,
1470 "%s: timeout!\n", __func__);
1471 message->state = STATE_ERROR;
1472 goto out;
1474 cpu_relax();
1477 /* Update total byte transferred */
1478 message->actual_length += pl022->cur_transfer->len;
1479 if (pl022->cur_transfer->cs_change)
1480 pl022->cur_chip->cs_control(SSP_CHIP_DESELECT);
1481 /* Move to next transfer */
1482 message->state = next_transfer(pl022);
1484 out:
1485 /* Handle end of message */
1486 if (message->state == STATE_DONE)
1487 message->status = 0;
1488 else
1489 message->status = -EIO;
1491 giveback(pl022);
1492 return;
1496 * pump_messages - Workqueue function which processes spi message queue
1497 * @data: pointer to private data of SSP driver
1499 * This function checks if there is any spi message in the queue that
1500 * needs processing and delegate control to appropriate function
1501 * do_polling_transfer()/do_interrupt_dma_transfer()
1502 * based on the kind of the transfer
1505 static void pump_messages(struct work_struct *work)
1507 struct pl022 *pl022 =
1508 container_of(work, struct pl022, pump_messages);
1509 unsigned long flags;
1511 /* Lock queue and check for queue work */
1512 spin_lock_irqsave(&pl022->queue_lock, flags);
1513 if (list_empty(&pl022->queue) || !pl022->running) {
1514 pl022->busy = false;
1515 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1516 return;
1518 /* Make sure we are not already running a message */
1519 if (pl022->cur_msg) {
1520 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1521 return;
1523 /* Extract head of queue */
1524 pl022->cur_msg =
1525 list_entry(pl022->queue.next, struct spi_message, queue);
1527 list_del_init(&pl022->cur_msg->queue);
1528 pl022->busy = true;
1529 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1531 /* Initial message state */
1532 pl022->cur_msg->state = STATE_START;
1533 pl022->cur_transfer = list_entry(pl022->cur_msg->transfers.next,
1534 struct spi_transfer,
1535 transfer_list);
1537 /* Setup the SPI using the per chip configuration */
1538 pl022->cur_chip = spi_get_ctldata(pl022->cur_msg->spi);
1540 * We enable the core voltage and clocks here, then the clocks
1541 * and core will be disabled when giveback() is called in each method
1542 * (poll/interrupt/DMA)
1544 pm_runtime_get_sync(&pl022->adev->dev);
1545 restore_state(pl022);
1546 flush(pl022);
1548 if (pl022->cur_chip->xfer_type == POLLING_TRANSFER)
1549 do_polling_transfer(pl022);
1550 else
1551 do_interrupt_dma_transfer(pl022);
1555 static int __init init_queue(struct pl022 *pl022)
1557 INIT_LIST_HEAD(&pl022->queue);
1558 spin_lock_init(&pl022->queue_lock);
1560 pl022->running = false;
1561 pl022->busy = false;
1563 tasklet_init(&pl022->pump_transfers,
1564 pump_transfers, (unsigned long)pl022);
1566 INIT_WORK(&pl022->pump_messages, pump_messages);
1567 pl022->workqueue = create_singlethread_workqueue(
1568 dev_name(pl022->master->dev.parent));
1569 if (pl022->workqueue == NULL)
1570 return -EBUSY;
1572 return 0;
1576 static int start_queue(struct pl022 *pl022)
1578 unsigned long flags;
1580 spin_lock_irqsave(&pl022->queue_lock, flags);
1582 if (pl022->running || pl022->busy) {
1583 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1584 return -EBUSY;
1587 pl022->running = true;
1588 pl022->cur_msg = NULL;
1589 pl022->cur_transfer = NULL;
1590 pl022->cur_chip = NULL;
1591 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1593 queue_work(pl022->workqueue, &pl022->pump_messages);
1595 return 0;
1599 static int stop_queue(struct pl022 *pl022)
1601 unsigned long flags;
1602 unsigned limit = 500;
1603 int status = 0;
1605 spin_lock_irqsave(&pl022->queue_lock, flags);
1607 /* This is a bit lame, but is optimized for the common execution path.
1608 * A wait_queue on the pl022->busy could be used, but then the common
1609 * execution path (pump_messages) would be required to call wake_up or
1610 * friends on every SPI message. Do this instead */
1611 while ((!list_empty(&pl022->queue) || pl022->busy) && limit--) {
1612 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1613 msleep(10);
1614 spin_lock_irqsave(&pl022->queue_lock, flags);
1617 if (!list_empty(&pl022->queue) || pl022->busy)
1618 status = -EBUSY;
1619 else
1620 pl022->running = false;
1622 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1624 return status;
1627 static int destroy_queue(struct pl022 *pl022)
1629 int status;
1631 status = stop_queue(pl022);
1632 /* we are unloading the module or failing to load (only two calls
1633 * to this routine), and neither call can handle a return value.
1634 * However, destroy_workqueue calls flush_workqueue, and that will
1635 * block until all work is done. If the reason that stop_queue
1636 * timed out is that the work will never finish, then it does no
1637 * good to call destroy_workqueue, so return anyway. */
1638 if (status != 0)
1639 return status;
1641 destroy_workqueue(pl022->workqueue);
1643 return 0;
1646 static int verify_controller_parameters(struct pl022 *pl022,
1647 struct pl022_config_chip const *chip_info)
1649 if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI)
1650 || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) {
1651 dev_err(&pl022->adev->dev,
1652 "interface is configured incorrectly\n");
1653 return -EINVAL;
1655 if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) &&
1656 (!pl022->vendor->unidir)) {
1657 dev_err(&pl022->adev->dev,
1658 "unidirectional mode not supported in this "
1659 "hardware version\n");
1660 return -EINVAL;
1662 if ((chip_info->hierarchy != SSP_MASTER)
1663 && (chip_info->hierarchy != SSP_SLAVE)) {
1664 dev_err(&pl022->adev->dev,
1665 "hierarchy is configured incorrectly\n");
1666 return -EINVAL;
1668 if ((chip_info->com_mode != INTERRUPT_TRANSFER)
1669 && (chip_info->com_mode != DMA_TRANSFER)
1670 && (chip_info->com_mode != POLLING_TRANSFER)) {
1671 dev_err(&pl022->adev->dev,
1672 "Communication mode is configured incorrectly\n");
1673 return -EINVAL;
1675 switch (chip_info->rx_lev_trig) {
1676 case SSP_RX_1_OR_MORE_ELEM:
1677 case SSP_RX_4_OR_MORE_ELEM:
1678 case SSP_RX_8_OR_MORE_ELEM:
1679 /* These are always OK, all variants can handle this */
1680 break;
1681 case SSP_RX_16_OR_MORE_ELEM:
1682 if (pl022->vendor->fifodepth < 16) {
1683 dev_err(&pl022->adev->dev,
1684 "RX FIFO Trigger Level is configured incorrectly\n");
1685 return -EINVAL;
1687 break;
1688 case SSP_RX_32_OR_MORE_ELEM:
1689 if (pl022->vendor->fifodepth < 32) {
1690 dev_err(&pl022->adev->dev,
1691 "RX FIFO Trigger Level is configured incorrectly\n");
1692 return -EINVAL;
1694 break;
1695 default:
1696 dev_err(&pl022->adev->dev,
1697 "RX FIFO Trigger Level is configured incorrectly\n");
1698 return -EINVAL;
1699 break;
1701 switch (chip_info->tx_lev_trig) {
1702 case SSP_TX_1_OR_MORE_EMPTY_LOC:
1703 case SSP_TX_4_OR_MORE_EMPTY_LOC:
1704 case SSP_TX_8_OR_MORE_EMPTY_LOC:
1705 /* These are always OK, all variants can handle this */
1706 break;
1707 case SSP_TX_16_OR_MORE_EMPTY_LOC:
1708 if (pl022->vendor->fifodepth < 16) {
1709 dev_err(&pl022->adev->dev,
1710 "TX FIFO Trigger Level is configured incorrectly\n");
1711 return -EINVAL;
1713 break;
1714 case SSP_TX_32_OR_MORE_EMPTY_LOC:
1715 if (pl022->vendor->fifodepth < 32) {
1716 dev_err(&pl022->adev->dev,
1717 "TX FIFO Trigger Level is configured incorrectly\n");
1718 return -EINVAL;
1720 break;
1721 default:
1722 dev_err(&pl022->adev->dev,
1723 "TX FIFO Trigger Level is configured incorrectly\n");
1724 return -EINVAL;
1725 break;
1727 if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) {
1728 if ((chip_info->ctrl_len < SSP_BITS_4)
1729 || (chip_info->ctrl_len > SSP_BITS_32)) {
1730 dev_err(&pl022->adev->dev,
1731 "CTRL LEN is configured incorrectly\n");
1732 return -EINVAL;
1734 if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO)
1735 && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) {
1736 dev_err(&pl022->adev->dev,
1737 "Wait State is configured incorrectly\n");
1738 return -EINVAL;
1740 /* Half duplex is only available in the ST Micro version */
1741 if (pl022->vendor->extended_cr) {
1742 if ((chip_info->duplex !=
1743 SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
1744 && (chip_info->duplex !=
1745 SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) {
1746 dev_err(&pl022->adev->dev,
1747 "Microwire duplex mode is configured incorrectly\n");
1748 return -EINVAL;
1750 } else {
1751 if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
1752 dev_err(&pl022->adev->dev,
1753 "Microwire half duplex mode requested,"
1754 " but this is only available in the"
1755 " ST version of PL022\n");
1756 return -EINVAL;
1759 return 0;
1763 * pl022_transfer - transfer function registered to SPI master framework
1764 * @spi: spi device which is requesting transfer
1765 * @msg: spi message which is to handled is queued to driver queue
1767 * This function is registered to the SPI framework for this SPI master
1768 * controller. It will queue the spi_message in the queue of driver if
1769 * the queue is not stopped and return.
1771 static int pl022_transfer(struct spi_device *spi, struct spi_message *msg)
1773 struct pl022 *pl022 = spi_master_get_devdata(spi->master);
1774 unsigned long flags;
1776 spin_lock_irqsave(&pl022->queue_lock, flags);
1778 if (!pl022->running) {
1779 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1780 return -ESHUTDOWN;
1782 msg->actual_length = 0;
1783 msg->status = -EINPROGRESS;
1784 msg->state = STATE_START;
1786 list_add_tail(&msg->queue, &pl022->queue);
1787 if (pl022->running && !pl022->busy)
1788 queue_work(pl022->workqueue, &pl022->pump_messages);
1790 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1791 return 0;
1794 static int calculate_effective_freq(struct pl022 *pl022,
1795 int freq,
1796 struct ssp_clock_params *clk_freq)
1798 /* Lets calculate the frequency parameters */
1799 u16 cpsdvsr = 2;
1800 u16 scr = 0;
1801 bool freq_found = false;
1802 u32 rate;
1803 u32 max_tclk;
1804 u32 min_tclk;
1806 rate = clk_get_rate(pl022->clk);
1807 /* cpsdvscr = 2 & scr 0 */
1808 max_tclk = (rate / (CPSDVR_MIN * (1 + SCR_MIN)));
1809 /* cpsdvsr = 254 & scr = 255 */
1810 min_tclk = (rate / (CPSDVR_MAX * (1 + SCR_MAX)));
1812 if ((freq <= max_tclk) && (freq >= min_tclk)) {
1813 while (cpsdvsr <= CPSDVR_MAX && !freq_found) {
1814 while (scr <= SCR_MAX && !freq_found) {
1815 if ((rate /
1816 (cpsdvsr * (1 + scr))) > freq)
1817 scr += 1;
1818 else {
1820 * This bool is made true when
1821 * effective frequency >=
1822 * target frequency is found
1824 freq_found = true;
1825 if ((rate /
1826 (cpsdvsr * (1 + scr))) != freq) {
1827 if (scr == SCR_MIN) {
1828 cpsdvsr -= 2;
1829 scr = SCR_MAX;
1830 } else
1831 scr -= 1;
1835 if (!freq_found) {
1836 cpsdvsr += 2;
1837 scr = SCR_MIN;
1840 if (cpsdvsr != 0) {
1841 dev_dbg(&pl022->adev->dev,
1842 "SSP Effective Frequency is %u\n",
1843 (rate / (cpsdvsr * (1 + scr))));
1844 clk_freq->cpsdvsr = (u8) (cpsdvsr & 0xFF);
1845 clk_freq->scr = (u8) (scr & 0xFF);
1846 dev_dbg(&pl022->adev->dev,
1847 "SSP cpsdvsr = %d, scr = %d\n",
1848 clk_freq->cpsdvsr, clk_freq->scr);
1850 } else {
1851 dev_err(&pl022->adev->dev,
1852 "controller data is incorrect: out of range frequency");
1853 return -EINVAL;
1855 return 0;
1860 * A piece of default chip info unless the platform
1861 * supplies it.
1863 static const struct pl022_config_chip pl022_default_chip_info = {
1864 .com_mode = POLLING_TRANSFER,
1865 .iface = SSP_INTERFACE_MOTOROLA_SPI,
1866 .hierarchy = SSP_SLAVE,
1867 .slave_tx_disable = DO_NOT_DRIVE_TX,
1868 .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,
1869 .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,
1870 .ctrl_len = SSP_BITS_8,
1871 .wait_state = SSP_MWIRE_WAIT_ZERO,
1872 .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
1873 .cs_control = null_cs_control,
1878 * pl022_setup - setup function registered to SPI master framework
1879 * @spi: spi device which is requesting setup
1881 * This function is registered to the SPI framework for this SPI master
1882 * controller. If it is the first time when setup is called by this device,
1883 * this function will initialize the runtime state for this chip and save
1884 * the same in the device structure. Else it will update the runtime info
1885 * with the updated chip info. Nothing is really being written to the
1886 * controller hardware here, that is not done until the actual transfer
1887 * commence.
1889 static int pl022_setup(struct spi_device *spi)
1891 struct pl022_config_chip const *chip_info;
1892 struct chip_data *chip;
1893 struct ssp_clock_params clk_freq = {0, };
1894 int status = 0;
1895 struct pl022 *pl022 = spi_master_get_devdata(spi->master);
1896 unsigned int bits = spi->bits_per_word;
1897 u32 tmp;
1899 if (!spi->max_speed_hz)
1900 return -EINVAL;
1902 /* Get controller_state if one is supplied */
1903 chip = spi_get_ctldata(spi);
1905 if (chip == NULL) {
1906 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1907 if (!chip) {
1908 dev_err(&spi->dev,
1909 "cannot allocate controller state\n");
1910 return -ENOMEM;
1912 dev_dbg(&spi->dev,
1913 "allocated memory for controller's runtime state\n");
1916 /* Get controller data if one is supplied */
1917 chip_info = spi->controller_data;
1919 if (chip_info == NULL) {
1920 chip_info = &pl022_default_chip_info;
1921 /* spi_board_info.controller_data not is supplied */
1922 dev_dbg(&spi->dev,
1923 "using default controller_data settings\n");
1924 } else
1925 dev_dbg(&spi->dev,
1926 "using user supplied controller_data settings\n");
1929 * We can override with custom divisors, else we use the board
1930 * frequency setting
1932 if ((0 == chip_info->clk_freq.cpsdvsr)
1933 && (0 == chip_info->clk_freq.scr)) {
1934 status = calculate_effective_freq(pl022,
1935 spi->max_speed_hz,
1936 &clk_freq);
1937 if (status < 0)
1938 goto err_config_params;
1939 } else {
1940 memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq));
1941 if ((clk_freq.cpsdvsr % 2) != 0)
1942 clk_freq.cpsdvsr =
1943 clk_freq.cpsdvsr - 1;
1945 if ((clk_freq.cpsdvsr < CPSDVR_MIN)
1946 || (clk_freq.cpsdvsr > CPSDVR_MAX)) {
1947 status = -EINVAL;
1948 dev_err(&spi->dev,
1949 "cpsdvsr is configured incorrectly\n");
1950 goto err_config_params;
1954 status = verify_controller_parameters(pl022, chip_info);
1955 if (status) {
1956 dev_err(&spi->dev, "controller data is incorrect");
1957 goto err_config_params;
1960 pl022->rx_lev_trig = chip_info->rx_lev_trig;
1961 pl022->tx_lev_trig = chip_info->tx_lev_trig;
1963 /* Now set controller state based on controller data */
1964 chip->xfer_type = chip_info->com_mode;
1965 if (!chip_info->cs_control) {
1966 chip->cs_control = null_cs_control;
1967 dev_warn(&spi->dev,
1968 "chip select function is NULL for this chip\n");
1969 } else
1970 chip->cs_control = chip_info->cs_control;
1972 if (bits <= 3) {
1973 /* PL022 doesn't support less than 4-bits */
1974 status = -ENOTSUPP;
1975 goto err_config_params;
1976 } else if (bits <= 8) {
1977 dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n");
1978 chip->n_bytes = 1;
1979 chip->read = READING_U8;
1980 chip->write = WRITING_U8;
1981 } else if (bits <= 16) {
1982 dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n");
1983 chip->n_bytes = 2;
1984 chip->read = READING_U16;
1985 chip->write = WRITING_U16;
1986 } else {
1987 if (pl022->vendor->max_bpw >= 32) {
1988 dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n");
1989 chip->n_bytes = 4;
1990 chip->read = READING_U32;
1991 chip->write = WRITING_U32;
1992 } else {
1993 dev_err(&spi->dev,
1994 "illegal data size for this controller!\n");
1995 dev_err(&spi->dev,
1996 "a standard pl022 can only handle "
1997 "1 <= n <= 16 bit words\n");
1998 status = -ENOTSUPP;
1999 goto err_config_params;
2003 /* Now Initialize all register settings required for this chip */
2004 chip->cr0 = 0;
2005 chip->cr1 = 0;
2006 chip->dmacr = 0;
2007 chip->cpsr = 0;
2008 if ((chip_info->com_mode == DMA_TRANSFER)
2009 && ((pl022->master_info)->enable_dma)) {
2010 chip->enable_dma = true;
2011 dev_dbg(&spi->dev, "DMA mode set in controller state\n");
2012 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
2013 SSP_DMACR_MASK_RXDMAE, 0);
2014 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
2015 SSP_DMACR_MASK_TXDMAE, 1);
2016 } else {
2017 chip->enable_dma = false;
2018 dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n");
2019 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
2020 SSP_DMACR_MASK_RXDMAE, 0);
2021 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
2022 SSP_DMACR_MASK_TXDMAE, 1);
2025 chip->cpsr = clk_freq.cpsdvsr;
2027 /* Special setup for the ST micro extended control registers */
2028 if (pl022->vendor->extended_cr) {
2029 u32 etx;
2031 if (pl022->vendor->pl023) {
2032 /* These bits are only in the PL023 */
2033 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay,
2034 SSP_CR1_MASK_FBCLKDEL_ST, 13);
2035 } else {
2036 /* These bits are in the PL022 but not PL023 */
2037 SSP_WRITE_BITS(chip->cr0, chip_info->duplex,
2038 SSP_CR0_MASK_HALFDUP_ST, 5);
2039 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len,
2040 SSP_CR0_MASK_CSS_ST, 16);
2041 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
2042 SSP_CR0_MASK_FRF_ST, 21);
2043 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state,
2044 SSP_CR1_MASK_MWAIT_ST, 6);
2046 SSP_WRITE_BITS(chip->cr0, bits - 1,
2047 SSP_CR0_MASK_DSS_ST, 0);
2049 if (spi->mode & SPI_LSB_FIRST) {
2050 tmp = SSP_RX_LSB;
2051 etx = SSP_TX_LSB;
2052 } else {
2053 tmp = SSP_RX_MSB;
2054 etx = SSP_TX_MSB;
2056 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4);
2057 SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5);
2058 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig,
2059 SSP_CR1_MASK_RXIFLSEL_ST, 7);
2060 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig,
2061 SSP_CR1_MASK_TXIFLSEL_ST, 10);
2062 } else {
2063 SSP_WRITE_BITS(chip->cr0, bits - 1,
2064 SSP_CR0_MASK_DSS, 0);
2065 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
2066 SSP_CR0_MASK_FRF, 4);
2069 /* Stuff that is common for all versions */
2070 if (spi->mode & SPI_CPOL)
2071 tmp = SSP_CLK_POL_IDLE_HIGH;
2072 else
2073 tmp = SSP_CLK_POL_IDLE_LOW;
2074 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6);
2076 if (spi->mode & SPI_CPHA)
2077 tmp = SSP_CLK_SECOND_EDGE;
2078 else
2079 tmp = SSP_CLK_FIRST_EDGE;
2080 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7);
2082 SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8);
2083 /* Loopback is available on all versions except PL023 */
2084 if (pl022->vendor->loopback) {
2085 if (spi->mode & SPI_LOOP)
2086 tmp = LOOPBACK_ENABLED;
2087 else
2088 tmp = LOOPBACK_DISABLED;
2089 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0);
2091 SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1);
2092 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2);
2093 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, 3);
2095 /* Save controller_state */
2096 spi_set_ctldata(spi, chip);
2097 return status;
2098 err_config_params:
2099 spi_set_ctldata(spi, NULL);
2100 kfree(chip);
2101 return status;
2105 * pl022_cleanup - cleanup function registered to SPI master framework
2106 * @spi: spi device which is requesting cleanup
2108 * This function is registered to the SPI framework for this SPI master
2109 * controller. It will free the runtime state of chip.
2111 static void pl022_cleanup(struct spi_device *spi)
2113 struct chip_data *chip = spi_get_ctldata(spi);
2115 spi_set_ctldata(spi, NULL);
2116 kfree(chip);
2120 static int __devinit
2121 pl022_probe(struct amba_device *adev, const struct amba_id *id)
2123 struct device *dev = &adev->dev;
2124 struct pl022_ssp_controller *platform_info = adev->dev.platform_data;
2125 struct spi_master *master;
2126 struct pl022 *pl022 = NULL; /*Data for this driver */
2127 int status = 0;
2129 dev_info(&adev->dev,
2130 "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid);
2131 if (platform_info == NULL) {
2132 dev_err(&adev->dev, "probe - no platform data supplied\n");
2133 status = -ENODEV;
2134 goto err_no_pdata;
2137 /* Allocate master with space for data */
2138 master = spi_alloc_master(dev, sizeof(struct pl022));
2139 if (master == NULL) {
2140 dev_err(&adev->dev, "probe - cannot alloc SPI master\n");
2141 status = -ENOMEM;
2142 goto err_no_master;
2145 pl022 = spi_master_get_devdata(master);
2146 pl022->master = master;
2147 pl022->master_info = platform_info;
2148 pl022->adev = adev;
2149 pl022->vendor = id->data;
2152 * Bus Number Which has been Assigned to this SSP controller
2153 * on this board
2155 master->bus_num = platform_info->bus_id;
2156 master->num_chipselect = platform_info->num_chipselect;
2157 master->cleanup = pl022_cleanup;
2158 master->setup = pl022_setup;
2159 master->transfer = pl022_transfer;
2162 * Supports mode 0-3, loopback, and active low CS. Transfers are
2163 * always MS bit first on the original pl022.
2165 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
2166 if (pl022->vendor->extended_cr)
2167 master->mode_bits |= SPI_LSB_FIRST;
2169 dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num);
2171 status = amba_request_regions(adev, NULL);
2172 if (status)
2173 goto err_no_ioregion;
2175 pl022->phybase = adev->res.start;
2176 pl022->virtbase = ioremap(adev->res.start, resource_size(&adev->res));
2177 if (pl022->virtbase == NULL) {
2178 status = -ENOMEM;
2179 goto err_no_ioremap;
2181 printk(KERN_INFO "pl022: mapped registers from 0x%08x to %p\n",
2182 adev->res.start, pl022->virtbase);
2184 pl022->clk = clk_get(&adev->dev, NULL);
2185 if (IS_ERR(pl022->clk)) {
2186 status = PTR_ERR(pl022->clk);
2187 dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n");
2188 goto err_no_clk;
2190 /* Disable SSP */
2191 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)),
2192 SSP_CR1(pl022->virtbase));
2193 load_ssp_default_config(pl022);
2195 status = request_irq(adev->irq[0], pl022_interrupt_handler, 0, "pl022",
2196 pl022);
2197 if (status < 0) {
2198 dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status);
2199 goto err_no_irq;
2202 /* Get DMA channels */
2203 if (platform_info->enable_dma) {
2204 status = pl022_dma_probe(pl022);
2205 if (status != 0)
2206 platform_info->enable_dma = 0;
2209 /* Initialize and start queue */
2210 status = init_queue(pl022);
2211 if (status != 0) {
2212 dev_err(&adev->dev, "probe - problem initializing queue\n");
2213 goto err_init_queue;
2215 status = start_queue(pl022);
2216 if (status != 0) {
2217 dev_err(&adev->dev, "probe - problem starting queue\n");
2218 goto err_start_queue;
2220 /* Register with the SPI framework */
2221 amba_set_drvdata(adev, pl022);
2222 status = spi_register_master(master);
2223 if (status != 0) {
2224 dev_err(&adev->dev,
2225 "probe - problem registering spi master\n");
2226 goto err_spi_register;
2228 dev_dbg(dev, "probe succeeded\n");
2230 /* let runtime pm put suspend */
2231 pm_runtime_put(dev);
2232 return 0;
2234 err_spi_register:
2235 err_start_queue:
2236 err_init_queue:
2237 destroy_queue(pl022);
2238 pl022_dma_remove(pl022);
2239 free_irq(adev->irq[0], pl022);
2240 err_no_irq:
2241 clk_put(pl022->clk);
2242 err_no_clk:
2243 iounmap(pl022->virtbase);
2244 err_no_ioremap:
2245 amba_release_regions(adev);
2246 err_no_ioregion:
2247 spi_master_put(master);
2248 err_no_master:
2249 err_no_pdata:
2250 return status;
2253 static int __devexit
2254 pl022_remove(struct amba_device *adev)
2256 struct pl022 *pl022 = amba_get_drvdata(adev);
2258 if (!pl022)
2259 return 0;
2262 * undo pm_runtime_put() in probe. I assume that we're not
2263 * accessing the primecell here.
2265 pm_runtime_get_noresume(&adev->dev);
2267 /* Remove the queue */
2268 if (destroy_queue(pl022) != 0)
2269 dev_err(&adev->dev, "queue remove failed\n");
2270 load_ssp_default_config(pl022);
2271 pl022_dma_remove(pl022);
2272 free_irq(adev->irq[0], pl022);
2273 clk_disable(pl022->clk);
2274 clk_put(pl022->clk);
2275 iounmap(pl022->virtbase);
2276 amba_release_regions(adev);
2277 tasklet_disable(&pl022->pump_transfers);
2278 spi_unregister_master(pl022->master);
2279 spi_master_put(pl022->master);
2280 amba_set_drvdata(adev, NULL);
2281 return 0;
2284 #ifdef CONFIG_SUSPEND
2285 static int pl011_suspend(struct device *dev)
2287 struct pl022 *pl022 = dev_get_drvdata(dev);
2288 int status = 0;
2290 status = stop_queue(pl022);
2291 if (status) {
2292 dev_warn(&adev->dev, "suspend cannot stop queue\n");
2293 return status;
2296 amba_vcore_enable(pl022->adev);
2297 amba_pclk_enable(pl022->adev);
2298 load_ssp_default_config(pl022);
2299 amba_pclk_disable(pl022->adev);
2300 amba_vcore_disable(pl022->adev);
2301 dev_dbg(&adev->dev, "suspended\n");
2302 return 0;
2305 static int pl022_resume(struct device *dev)
2307 struct pl022 *pl022 = dev_get_drvdata(dev);
2308 int status = 0;
2310 /* Start the queue running */
2311 status = start_queue(pl022);
2312 if (status)
2313 dev_err(dev, "problem starting queue (%d)\n", status);
2314 else
2315 dev_dbg(dev, "resumed\n");
2317 return status;
2319 #endif /* CONFIG_PM */
2321 #ifdef CONFIG_PM_RUNTIME
2322 static int pl022_runtime_suspend(struct device *dev)
2324 struct pl022 *pl022 = dev_get_drvdata(dev);
2326 clk_disable(pl022->clk);
2327 amba_vcore_disable(pl022->adev);
2329 return 0;
2332 static int pl022_runtime_resume(struct device *dev)
2334 struct pl022 *pl022 = dev_get_drvdata(dev);
2336 amba_vcore_enable(pl022->adev);
2337 clk_enable(pl022->clk);
2339 return 0;
2341 #endif
2343 static const struct dev_pm_ops pl022_dev_pm_ops = {
2344 SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume)
2345 SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL)
2348 static struct vendor_data vendor_arm = {
2349 .fifodepth = 8,
2350 .max_bpw = 16,
2351 .unidir = false,
2352 .extended_cr = false,
2353 .pl023 = false,
2354 .loopback = true,
2358 static struct vendor_data vendor_st = {
2359 .fifodepth = 32,
2360 .max_bpw = 32,
2361 .unidir = false,
2362 .extended_cr = true,
2363 .pl023 = false,
2364 .loopback = true,
2367 static struct vendor_data vendor_st_pl023 = {
2368 .fifodepth = 32,
2369 .max_bpw = 32,
2370 .unidir = false,
2371 .extended_cr = true,
2372 .pl023 = true,
2373 .loopback = false,
2376 static struct vendor_data vendor_db5500_pl023 = {
2377 .fifodepth = 32,
2378 .max_bpw = 32,
2379 .unidir = false,
2380 .extended_cr = true,
2381 .pl023 = true,
2382 .loopback = true,
2385 static struct amba_id pl022_ids[] = {
2388 * ARM PL022 variant, this has a 16bit wide
2389 * and 8 locations deep TX/RX FIFO
2391 .id = 0x00041022,
2392 .mask = 0x000fffff,
2393 .data = &vendor_arm,
2397 * ST Micro derivative, this has 32bit wide
2398 * and 32 locations deep TX/RX FIFO
2400 .id = 0x01080022,
2401 .mask = 0xffffffff,
2402 .data = &vendor_st,
2406 * ST-Ericsson derivative "PL023" (this is not
2407 * an official ARM number), this is a PL022 SSP block
2408 * stripped to SPI mode only, it has 32bit wide
2409 * and 32 locations deep TX/RX FIFO but no extended
2410 * CR0/CR1 register
2412 .id = 0x00080023,
2413 .mask = 0xffffffff,
2414 .data = &vendor_st_pl023,
2417 .id = 0x10080023,
2418 .mask = 0xffffffff,
2419 .data = &vendor_db5500_pl023,
2421 { 0, 0 },
2424 static struct amba_driver pl022_driver = {
2425 .drv = {
2426 .name = "ssp-pl022",
2427 .pm = &pl022_dev_pm_ops,
2429 .id_table = pl022_ids,
2430 .probe = pl022_probe,
2431 .remove = __devexit_p(pl022_remove),
2435 static int __init pl022_init(void)
2437 return amba_driver_register(&pl022_driver);
2440 subsys_initcall(pl022_init);
2442 static void __exit pl022_exit(void)
2444 amba_driver_unregister(&pl022_driver);
2447 module_exit(pl022_exit);
2449 MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
2450 MODULE_DESCRIPTION("PL022 SSP Controller Driver");
2451 MODULE_LICENSE("GPL");