| blob | 1c1c228352d10cb85e96436a9520c2fbf7185d58 |
1 /*
2 * Driver for the Conexant CX25821 PCIe bridge
3 *
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 *
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
23 #ifndef __MEDUSA_REGISTERS__
24 #define __MEDUSA_REGISTERS__
26 /* Serial Slave Registers */
27 #define HOST_REGISTER1 0x0000
28 #define HOST_REGISTER2 0x0001
30 /* Chip Configuration Registers */
31 #define CHIP_CTRL 0x0100
32 #define AFE_AB_CTRL 0x0104
33 #define AFE_CD_CTRL 0x0108
34 #define AFE_EF_CTRL 0x010C
35 #define AFE_GH_CTRL 0x0110
36 #define DENC_AB_CTRL 0x0114
37 #define BYP_AB_CTRL 0x0118
38 #define MON_A_CTRL 0x011C
39 #define DISP_SEQ_A 0x0120
40 #define DISP_SEQ_B 0x0124
41 #define DISP_AB_CNT 0x0128
42 #define DISP_CD_CNT 0x012C
43 #define DISP_EF_CNT 0x0130
44 #define DISP_GH_CNT 0x0134
45 #define DISP_IJ_CNT 0x0138
46 #define PIN_OE_CTRL 0x013C
47 #define PIN_SPD_CTRL 0x0140
48 #define PIN_SPD_CTRL2 0x0144
49 #define IRQ_STAT_CTRL 0x0148
50 #define POWER_CTRL_AB 0x014C
51 #define POWER_CTRL_CD 0x0150
52 #define POWER_CTRL_EF 0x0154
53 #define POWER_CTRL_GH 0x0158
54 #define TUNE_CTRL 0x015C
55 #define BIAS_CTRL 0x0160
56 #define AFE_AB_DIAG_CTRL 0x0164
57 #define AFE_CD_DIAG_CTRL 0x0168
58 #define AFE_EF_DIAG_CTRL 0x016C
59 #define AFE_GH_DIAG_CTRL 0x0170
60 #define PLL_AB_DIAG_CTRL 0x0174
61 #define PLL_CD_DIAG_CTRL 0x0178
62 #define PLL_EF_DIAG_CTRL 0x017C
63 #define PLL_GH_DIAG_CTRL 0x0180
64 #define TEST_CTRL 0x0184
65 #define BIST_STAT 0x0188
66 #define BIST_STAT2 0x018C
67 #define BIST_VID_PLL_AB_STAT 0x0190
68 #define BIST_VID_PLL_CD_STAT 0x0194
69 #define BIST_VID_PLL_EF_STAT 0x0198
70 #define BIST_VID_PLL_GH_STAT 0x019C
71 #define DLL_DIAG_CTRL 0x01A0
72 #define DEV_CH_ID_CTRL 0x01A4
73 #define ABIST_CTRL_STATUS 0x01A8
74 #define ABIST_FREQ 0x01AC
75 #define ABIST_GOERT_SHIFT 0x01B0
76 #define ABIST_COEF12 0x01B4
77 #define ABIST_COEF34 0x01B8
78 #define ABIST_COEF56 0x01BC
79 #define ABIST_COEF7_SNR 0x01C0
80 #define ABIST_ADC_CAL 0x01C4
81 #define ABIST_BIN1_VGA0 0x01C8
82 #define ABIST_BIN2_VGA1 0x01CC
83 #define ABIST_BIN3_VGA2 0x01D0
84 #define ABIST_BIN4_VGA3 0x01D4
85 #define ABIST_BIN5_VGA4 0x01D8
86 #define ABIST_BIN6_VGA5 0x01DC
87 #define ABIST_BIN7_VGA6 0x0x1E0
88 #define ABIST_CLAMP_A 0x0x1E4
89 #define ABIST_CLAMP_B 0x0x1E8
90 #define ABIST_CLAMP_C 0x01EC
91 #define ABIST_CLAMP_D 0x01F0
92 #define ABIST_CLAMP_E 0x01F4
93 #define ABIST_CLAMP_F 0x01F8
95 /* Digital Video Encoder A Registers */
96 #define DENC_A_REG_1 0x0200
97 #define DENC_A_REG_2 0x0204
98 #define DENC_A_REG_3 0x0208
99 #define DENC_A_REG_4 0x020C
100 #define DENC_A_REG_5 0x0210
101 #define DENC_A_REG_6 0x0214
102 #define DENC_A_REG_7 0x0218
103 #define DENC_A_REG_8 0x021C
105 /* Digital Video Encoder B Registers */
106 #define DENC_B_REG_1 0x0300
107 #define DENC_B_REG_2 0x0304
108 #define DENC_B_REG_3 0x0308
109 #define DENC_B_REG_4 0x030C
110 #define DENC_B_REG_5 0x0310
111 #define DENC_B_REG_6 0x0314
112 #define DENC_B_REG_7 0x0318
113 #define DENC_B_REG_8 0x031C
115 /* Video Decoder A Registers */
116 #define MODE_CTRL 0x1000
117 #define OUT_CTRL1 0x1004
118 #define OUT_CTRL_NS 0x1008
119 #define GEN_STAT 0x100C
120 #define INT_STAT_MASK 0x1010
121 #define LUMA_CTRL 0x1014
122 #define CHROMA_CTRL 0x1018
123 #define CRUSH_CTRL 0x101C
124 #define HORIZ_TIM_CTRL 0x1020
125 #define VERT_TIM_CTRL 0x1024
126 #define MISC_TIM_CTRL 0x1028
127 #define FIELD_COUNT 0x102C
128 #define HSCALE_CTRL 0x1030
129 #define VSCALE_CTRL 0x1034
130 #define MAN_VGA_CTRL 0x1038
131 #define MAN_AGC_CTRL 0x103C
132 #define DFE_CTRL1 0x1040
133 #define DFE_CTRL2 0x1044
134 #define DFE_CTRL3 0x1048
135 #define PLL_CTRL 0x104C
136 #define PLL_CTRL_FAST 0x1050
137 #define HTL_CTRL 0x1054
138 #define SRC_CFG 0x1058
139 #define SC_STEP_SIZE 0x105C
140 #define SC_CONVERGE_CTRL 0x1060
141 #define SC_LOOP_CTRL 0x1064
142 #define COMB_2D_HFS_CFG 0x1068
143 #define COMB_2D_HFD_CFG 0x106C
144 #define COMB_2D_LF_CFG 0x1070
145 #define COMB_2D_BLEND 0x1074
146 #define COMB_MISC_CTRL 0x1078
147 #define COMB_FLAT_THRESH_CTRL 0x107C
148 #define COMB_TEST 0x1080
149 #define BP_MISC_CTRL 0x1084
150 #define VCR_DET_CTRL 0x1088
151 #define NOISE_DET_CTRL 0x108C
152 #define COMB_FLAT_NOISE_CTRL 0x1090
153 #define VERSION 0x11F8
154 #define SOFT_RST_CTRL 0x11FC
156 /* Video Decoder B Registers */
157 #define VDEC_B_MODE_CTRL 0x1200
158 #define VDEC_B_OUT_CTRL1 0x1204
159 #define VDEC_B_OUT_CTRL_NS 0x1208
160 #define VDEC_B_GEN_STAT 0x120C
161 #define VDEC_B_INT_STAT_MASK 0x1210
162 #define VDEC_B_LUMA_CTRL 0x1214
163 #define VDEC_B_CHROMA_CTRL 0x1218
164 #define VDEC_B_CRUSH_CTRL 0x121C
165 #define VDEC_B_HORIZ_TIM_CTRL 0x1220
166 #define VDEC_B_VERT_TIM_CTRL 0x1224
167 #define VDEC_B_MISC_TIM_CTRL 0x1228
168 #define VDEC_B_FIELD_COUNT 0x122C
169 #define VDEC_B_HSCALE_CTRL 0x1230
170 #define VDEC_B_VSCALE_CTRL 0x1234
171 #define VDEC_B_MAN_VGA_CTRL 0x1238
172 #define VDEC_B_MAN_AGC_CTRL 0x123C
173 #define VDEC_B_DFE_CTRL1 0x1240
174 #define VDEC_B_DFE_CTRL2 0x1244
175 #define VDEC_B_DFE_CTRL3 0x1248
176 #define VDEC_B_PLL_CTRL 0x124C
177 #define VDEC_B_PLL_CTRL_FAST 0x1250
178 #define VDEC_B_HTL_CTRL 0x1254
179 #define VDEC_B_SRC_CFG 0x1258
180 #define VDEC_B_SC_STEP_SIZE 0x125C
181 #define VDEC_B_SC_CONVERGE_CTRL 0x1260
182 #define VDEC_B_SC_LOOP_CTRL 0x1264
183 #define VDEC_B_COMB_2D_HFS_CFG 0x1268
184 #define VDEC_B_COMB_2D_HFD_CFG 0x126C
185 #define VDEC_B_COMB_2D_LF_CFG 0x1270
186 #define VDEC_B_COMB_2D_BLEND 0x1274
187 #define VDEC_B_COMB_MISC_CTRL 0x1278
188 #define VDEC_B_COMB_FLAT_THRESH_CTRL 0x127C
189 #define VDEC_B_COMB_TEST 0x1280
190 #define VDEC_B_BP_MISC_CTRL 0x1284
191 #define VDEC_B_VCR_DET_CTRL 0x1288
192 #define VDEC_B_NOISE_DET_CTRL 0x128C
193 #define VDEC_B_COMB_FLAT_NOISE_CTRL 0x1290
194 #define VDEC_B_VERSION 0x13F8
195 #define VDEC_B_SOFT_RST_CTRL 0x13FC
197 /* Video Decoder C Registers */
198 #define VDEC_C_MODE_CTRL 0x1400
199 #define VDEC_C_OUT_CTRL1 0x1404
200 #define VDEC_C_OUT_CTRL_NS 0x1408
201 #define VDEC_C_GEN_STAT 0x140C
202 #define VDEC_C_INT_STAT_MASK 0x1410
203 #define VDEC_C_LUMA_CTRL 0x1414
204 #define VDEC_C_CHROMA_CTRL 0x1418
205 #define VDEC_C_CRUSH_CTRL 0x141C
206 #define VDEC_C_HORIZ_TIM_CTRL 0x1420
207 #define VDEC_C_VERT_TIM_CTRL 0x1424
208 #define VDEC_C_MISC_TIM_CTRL 0x1428
209 #define VDEC_C_FIELD_COUNT 0x142C
210 #define VDEC_C_HSCALE_CTRL 0x1430
211 #define VDEC_C_VSCALE_CTRL 0x1434
212 #define VDEC_C_MAN_VGA_CTRL 0x1438
213 #define VDEC_C_MAN_AGC_CTRL 0x143C
214 #define VDEC_C_DFE_CTRL1 0x1440
215 #define VDEC_C_DFE_CTRL2 0x1444
216 #define VDEC_C_DFE_CTRL3 0x1448
217 #define VDEC_C_PLL_CTRL 0x144C
218 #define VDEC_C_PLL_CTRL_FAST 0x1450
219 #define VDEC_C_HTL_CTRL 0x1454
220 #define VDEC_C_SRC_CFG 0x1458
221 #define VDEC_C_SC_STEP_SIZE 0x145C
222 #define VDEC_C_SC_CONVERGE_CTRL 0x1460
223 #define VDEC_C_SC_LOOP_CTRL 0x1464
224 #define VDEC_C_COMB_2D_HFS_CFG 0x1468
225 #define VDEC_C_COMB_2D_HFD_CFG 0x146C
226 #define VDEC_C_COMB_2D_LF_CFG 0x1470
227 #define VDEC_C_COMB_2D_BLEND 0x1474
228 #define VDEC_C_COMB_MISC_CTRL 0x1478
229 #define VDEC_C_COMB_FLAT_THRESH_CTRL 0x147C
230 #define VDEC_C_COMB_TEST 0x1480
231 #define VDEC_C_BP_MISC_CTRL 0x1484
232 #define VDEC_C_VCR_DET_CTRL 0x1488
233 #define VDEC_C_NOISE_DET_CTRL 0x148C
234 #define VDEC_C_COMB_FLAT_NOISE_CTRL 0x1490
235 #define VDEC_C_VERSION 0x15F8
236 #define VDEC_C_SOFT_RST_CTRL 0x15FC
238 /* Video Decoder D Registers */
239 #define VDEC_D_MODE_CTRL 0x1600
240 #define VDEC_D_OUT_CTRL1 0x1604
241 #define VDEC_D_OUT_CTRL_NS 0x1608
242 #define VDEC_D_GEN_STAT 0x160C
243 #define VDEC_D_INT_STAT_MASK 0x1610
244 #define VDEC_D_LUMA_CTRL 0x1614
245 #define VDEC_D_CHROMA_CTRL 0x1618
246 #define VDEC_D_CRUSH_CTRL 0x161C
247 #define VDEC_D_HORIZ_TIM_CTRL 0x1620
248 #define VDEC_D_VERT_TIM_CTRL 0x1624
249 #define VDEC_D_MISC_TIM_CTRL 0x1628
250 #define VDEC_D_FIELD_COUNT 0x162C
251 #define VDEC_D_HSCALE_CTRL 0x1630
252 #define VDEC_D_VSCALE_CTRL 0x1634
253 #define VDEC_D_MAN_VGA_CTRL 0x1638
254 #define VDEC_D_MAN_AGC_CTRL 0x163C
255 #define VDEC_D_DFE_CTRL1 0x1640
256 #define VDEC_D_DFE_CTRL2 0x1644
257 #define VDEC_D_DFE_CTRL3 0x1648
258 #define VDEC_D_PLL_CTRL 0x164C
259 #define VDEC_D_PLL_CTRL_FAST 0x1650
260 #define VDEC_D_HTL_CTRL 0x1654
261 #define VDEC_D_SRC_CFG 0x1658
262 #define VDEC_D_SC_STEP_SIZE 0x165C
263 #define VDEC_D_SC_CONVERGE_CTRL 0x1660
264 #define VDEC_D_SC_LOOP_CTRL 0x1664
265 #define VDEC_D_COMB_2D_HFS_CFG 0x1668
266 #define VDEC_D_COMB_2D_HFD_CFG 0x166C
267 #define VDEC_D_COMB_2D_LF_CFG 0x1670
268 #define VDEC_D_COMB_2D_BLEND 0x1674
269 #define VDEC_D_COMB_MISC_CTRL 0x1678
270 #define VDEC_D_COMB_FLAT_THRESH_CTRL 0x167C
271 #define VDEC_D_COMB_TEST 0x1680
272 #define VDEC_D_BP_MISC_CTRL 0x1684
273 #define VDEC_D_VCR_DET_CTRL 0x1688
274 #define VDEC_D_NOISE_DET_CTRL 0x168C
275 #define VDEC_D_COMB_FLAT_NOISE_CTRL 0x1690
276 #define VDEC_D_VERSION 0x17F8
277 #define VDEC_D_SOFT_RST_CTRL 0x17FC
279 /* Video Decoder E Registers */
280 #define VDEC_E_MODE_CTRL 0x1800
281 #define VDEC_E_OUT_CTRL1 0x1804
282 #define VDEC_E_OUT_CTRL_NS 0x1808
283 #define VDEC_E_GEN_STAT 0x180C
284 #define VDEC_E_INT_STAT_MASK 0x1810
285 #define VDEC_E_LUMA_CTRL 0x1814
286 #define VDEC_E_CHROMA_CTRL 0x1818
287 #define VDEC_E_CRUSH_CTRL 0x181C
288 #define VDEC_E_HORIZ_TIM_CTRL 0x1820
289 #define VDEC_E_VERT_TIM_CTRL 0x1824
290 #define VDEC_E_MISC_TIM_CTRL 0x1828
291 #define VDEC_E_FIELD_COUNT 0x182C
292 #define VDEC_E_HSCALE_CTRL 0x1830
293 #define VDEC_E_VSCALE_CTRL 0x1834
294 #define VDEC_E_MAN_VGA_CTRL 0x1838
295 #define VDEC_E_MAN_AGC_CTRL 0x183C
296 #define VDEC_E_DFE_CTRL1 0x1840
297 #define VDEC_E_DFE_CTRL2 0x1844
298 #define VDEC_E_DFE_CTRL3 0x1848
299 #define VDEC_E_PLL_CTRL 0x184C
300 #define VDEC_E_PLL_CTRL_FAST 0x1850
301 #define VDEC_E_HTL_CTRL 0x1854
302 #define VDEC_E_SRC_CFG 0x1858
303 #define VDEC_E_SC_STEP_SIZE 0x185C
304 #define VDEC_E_SC_CONVERGE_CTRL 0x1860
305 #define VDEC_E_SC_LOOP_CTRL 0x1864
306 #define VDEC_E_COMB_2D_HFS_CFG 0x1868
307 #define VDEC_E_COMB_2D_HFD_CFG 0x186C
308 #define VDEC_E_COMB_2D_LF_CFG 0x1870
309 #define VDEC_E_COMB_2D_BLEND 0x1874
310 #define VDEC_E_COMB_MISC_CTRL 0x1878
311 #define VDEC_E_COMB_FLAT_THRESH_CTRL 0x187C
312 #define VDEC_E_COMB_TEST 0x1880
313 #define VDEC_E_BP_MISC_CTRL 0x1884
314 #define VDEC_E_VCR_DET_CTRL 0x1888
315 #define VDEC_E_NOISE_DET_CTRL 0x188C
316 #define VDEC_E_COMB_FLAT_NOISE_CTRL 0x1890
317 #define VDEC_E_VERSION 0x19F8
318 #define VDEC_E_SOFT_RST_CTRL 0x19FC
320 /* Video Decoder F Registers */
321 #define VDEC_F_MODE_CTRL 0x1A00
322 #define VDEC_F_OUT_CTRL1 0x1A04
323 #define VDEC_F_OUT_CTRL_NS 0x1A08
324 #define VDEC_F_GEN_STAT 0x1A0C
325 #define VDEC_F_INT_STAT_MASK 0x1A10
326 #define VDEC_F_LUMA_CTRL 0x1A14
327 #define VDEC_F_CHROMA_CTRL 0x1A18
328 #define VDEC_F_CRUSH_CTRL 0x1A1C
329 #define VDEC_F_HORIZ_TIM_CTRL 0x1A20
330 #define VDEC_F_VERT_TIM_CTRL 0x1A24
331 #define VDEC_F_MISC_TIM_CTRL 0x1A28
332 #define VDEC_F_FIELD_COUNT 0x1A2C
333 #define VDEC_F_HSCALE_CTRL 0x1A30
334 #define VDEC_F_VSCALE_CTRL 0x1A34
335 #define VDEC_F_MAN_VGA_CTRL 0x1A38
336 #define VDEC_F_MAN_AGC_CTRL 0x1A3C
337 #define VDEC_F_DFE_CTRL1 0x1A40
338 #define VDEC_F_DFE_CTRL2 0x1A44
339 #define VDEC_F_DFE_CTRL3 0x1A48
340 #define VDEC_F_PLL_CTRL 0x1A4C
341 #define VDEC_F_PLL_CTRL_FAST 0x1A50
342 #define VDEC_F_HTL_CTRL 0x1A54
343 #define VDEC_F_SRC_CFG 0x1A58
344 #define VDEC_F_SC_STEP_SIZE 0x1A5C
345 #define VDEC_F_SC_CONVERGE_CTRL 0x1A60
346 #define VDEC_F_SC_LOOP_CTRL 0x1A64
347 #define VDEC_F_COMB_2D_HFS_CFG 0x1A68
348 #define VDEC_F_COMB_2D_HFD_CFG 0x1A6C
349 #define VDEC_F_COMB_2D_LF_CFG 0x1A70
350 #define VDEC_F_COMB_2D_BLEND 0x1A74
351 #define VDEC_F_COMB_MISC_CTRL 0x1A78
352 #define VDEC_F_COMB_FLAT_THRESH_CTRL 0x1A7C
353 #define VDEC_F_COMB_TEST 0x1A80
354 #define VDEC_F_BP_MISC_CTRL 0x1A84
355 #define VDEC_F_VCR_DET_CTRL 0x1A88
356 #define VDEC_F_NOISE_DET_CTRL 0x1A8C
357 #define VDEC_F_COMB_FLAT_NOISE_CTRL 0x1A90
358 #define VDEC_F_VERSION 0x1BF8
359 #define VDEC_F_SOFT_RST_CTRL 0x1BFC
361 /* Video Decoder G Registers */
362 #define VDEC_G_MODE_CTRL 0x1C00
363 #define VDEC_G_OUT_CTRL1 0x1C04
364 #define VDEC_G_OUT_CTRL_NS 0x1C08
365 #define VDEC_G_GEN_STAT 0x1C0C
366 #define VDEC_G_INT_STAT_MASK 0x1C10
367 #define VDEC_G_LUMA_CTRL 0x1C14
368 #define VDEC_G_CHROMA_CTRL 0x1C18
369 #define VDEC_G_CRUSH_CTRL 0x1C1C
370 #define VDEC_G_HORIZ_TIM_CTRL 0x1C20
371 #define VDEC_G_VERT_TIM_CTRL 0x1C24
372 #define VDEC_G_MISC_TIM_CTRL 0x1C28
373 #define VDEC_G_FIELD_COUNT 0x1C2C
374 #define VDEC_G_HSCALE_CTRL 0x1C30
375 #define VDEC_G_VSCALE_CTRL 0x1C34
376 #define VDEC_G_MAN_VGA_CTRL 0x1C38
377 #define VDEC_G_MAN_AGC_CTRL 0x1C3C
378 #define VDEC_G_DFE_CTRL1 0x1C40
379 #define VDEC_G_DFE_CTRL2 0x1C44
380 #define VDEC_G_DFE_CTRL3 0x1C48
381 #define VDEC_G_PLL_CTRL 0x1C4C
382 #define VDEC_G_PLL_CTRL_FAST 0x1C50
383 #define VDEC_G_HTL_CTRL 0x1C54
384 #define VDEC_G_SRC_CFG 0x1C58
385 #define VDEC_G_SC_STEP_SIZE 0x1C5C
386 #define VDEC_G_SC_CONVERGE_CTRL 0x1C60
387 #define VDEC_G_SC_LOOP_CTRL 0x1C64
388 #define VDEC_G_COMB_2D_HFS_CFG 0x1C68
389 #define VDEC_G_COMB_2D_HFD_CFG 0x1C6C
390 #define VDEC_G_COMB_2D_LF_CFG 0x1C70
391 #define VDEC_G_COMB_2D_BLEND 0x1C74
392 #define VDEC_G_COMB_MISC_CTRL 0x1C78
393 #define VDEC_G_COMB_FLAT_THRESH_CTRL 0x1C7C
394 #define VDEC_G_COMB_TEST 0x1C80
395 #define VDEC_G_BP_MISC_CTRL 0x1C84
396 #define VDEC_G_VCR_DET_CTRL 0x1C88
397 #define VDEC_G_NOISE_DET_CTRL 0x1C8C
398 #define VDEC_G_COMB_FLAT_NOISE_CTRL 0x1C90
399 #define VDEC_G_VERSION 0x1DF8
400 #define VDEC_G_SOFT_RST_CTRL 0x1DFC
402 /* Video Decoder H Registers */
403 #define VDEC_H_MODE_CTRL 0x1E00
404 #define VDEC_H_OUT_CTRL1 0x1E04
405 #define VDEC_H_OUT_CTRL_NS 0x1E08
406 #define VDEC_H_GEN_STAT 0x1E0C
407 #define VDEC_H_INT_STAT_MASK 0x1E1E
408 #define VDEC_H_LUMA_CTRL 0x1E14
409 #define VDEC_H_CHROMA_CTRL 0x1E18
410 #define VDEC_H_CRUSH_CTRL 0x1E1C
411 #define VDEC_H_HORIZ_TIM_CTRL 0x1E20
412 #define VDEC_H_VERT_TIM_CTRL 0x1E24
413 #define VDEC_H_MISC_TIM_CTRL 0x1E28
414 #define VDEC_H_FIELD_COUNT 0x1E2C
415 #define VDEC_H_HSCALE_CTRL 0x1E30
416 #define VDEC_H_VSCALE_CTRL 0x1E34
417 #define VDEC_H_MAN_VGA_CTRL 0x1E38
418 #define VDEC_H_MAN_AGC_CTRL 0x1E3C
419 #define VDEC_H_DFE_CTRL1 0x1E40
420 #define VDEC_H_DFE_CTRL2 0x1E44
421 #define VDEC_H_DFE_CTRL3 0x1E48
422 #define VDEC_H_PLL_CTRL 0x1E4C
423 #define VDEC_H_PLL_CTRL_FAST 0x1E50
424 #define VDEC_H_HTL_CTRL 0x1E54
425 #define VDEC_H_SRC_CFG 0x1E58
426 #define VDEC_H_SC_STEP_SIZE 0x1E5C
427 #define VDEC_H_SC_CONVERGE_CTRL 0x1E60
428 #define VDEC_H_SC_LOOP_CTRL 0x1E64
429 #define VDEC_H_COMB_2D_HFS_CFG 0x1E68
430 #define VDEC_H_COMB_2D_HFD_CFG 0x1E6C
431 #define VDEC_H_COMB_2D_LF_CFG 0x1E70
432 #define VDEC_H_COMB_2D_BLEND 0x1E74
433 #define VDEC_H_COMB_MISC_CTRL 0x1E78
434 #define VDEC_H_COMB_FLAT_THRESH_CTRL 0x1E7C
435 #define VDEC_H_COMB_TEST 0x1E80
436 #define VDEC_H_BP_MISC_CTRL 0x1E84
437 #define VDEC_H_VCR_DET_CTRL 0x1E88
438 #define VDEC_H_NOISE_DET_CTRL 0x1E8C
439 #define VDEC_H_COMB_FLAT_NOISE_CTRL 0x1E90
440 #define VDEC_H_VERSION 0x1FF8
441 #define VDEC_H_SOFT_RST_CTRL 0x1FFC
443 /*****************************************************************************/
444 /* LUMA_CTRL register fields */
445 #define VDEC_A_BRITE_CTRL 0x1014
446 #define VDEC_A_CNTRST_CTRL 0x1015
447 #define VDEC_A_PEAK_SEL 0x1016
449 /*****************************************************************************/
450 /* CHROMA_CTRL register fields */
451 #define VDEC_A_USAT_CTRL 0x1018
452 #define VDEC_A_VSAT_CTRL 0x1019
453 #define VDEC_A_HUE_CTRL 0x101A
455 #endif