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Add linux-next specific files for 20110831
[linux-2.6/next.git] / drivers / tty / serial / 8250.c
blob454fc9241dcd931ffa4cea917f4df9f8941a23f3
1 /*
2 * Driver for 8250/16550-type serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * A note about mapbase / membase
14 *
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
17 */
18
19 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20 #define SUPPORT_SYSRQ
21 #endif
22
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/ioport.h>
26 #include <linux/init.h>
27 #include <linux/console.h>
28 #include <linux/sysrq.h>
29 #include <linux/delay.h>
30 #include <linux/platform_device.h>
31 #include <linux/tty.h>
32 #include <linux/ratelimit.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial_reg.h>
35 #include <linux/serial_core.h>
36 #include <linux/serial.h>
37 #include <linux/serial_8250.h>
38 #include <linux/nmi.h>
39 #include <linux/mutex.h>
40 #include <linux/slab.h>
41
42 #include <asm/io.h>
43 #include <asm/irq.h>
44
45 #include "8250.h"
46
47 #ifdef CONFIG_SPARC
48 #include "suncore.h"
49 #endif
50
51 /*
52 * Configuration:
53 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
54 * is unsafe when used on edge-triggered interrupts.
55 */
56 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
57
58 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
59
60 static struct uart_driver serial8250_reg;
61
62 static int serial_index(struct uart_port *port)
63 {
64 return (serial8250_reg.minor - 64) + port->line;
65 }
66
67 static unsigned int skip_txen_test; /* force skip of txen test at init time */
68
69 /*
70 * Debugging.
71 */
72 #if 0
73 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
74 #else
75 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
76 #endif
77
78 #if 0
79 #define DEBUG_INTR(fmt...) printk(fmt)
80 #else
81 #define DEBUG_INTR(fmt...) do { } while (0)
82 #endif
83
84 #define PASS_LIMIT 512
85
86 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
87
88
89 /*
90 * We default to IRQ0 for the "no irq" hack. Some
91 * machine types want others as well - they're free
92 * to redefine this in their header file.
93 */
94 #define is_real_interrupt(irq) ((irq) != 0)
95
96 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
97 #define CONFIG_SERIAL_DETECT_IRQ 1
98 #endif
99 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
100 #define CONFIG_SERIAL_MANY_PORTS 1
101 #endif
102
103 /*
104 * HUB6 is always on. This will be removed once the header
105 * files have been cleaned.
106 */
107 #define CONFIG_HUB6 1
108
109 #include <asm/serial.h>
110 /*
111 * SERIAL_PORT_DFNS tells us about built-in ports that have no
112 * standard enumeration mechanism. Platforms that can find all
113 * serial ports via mechanisms like ACPI or PCI need not supply it.
114 */
115 #ifndef SERIAL_PORT_DFNS
116 #define SERIAL_PORT_DFNS
117 #endif
118
119 static const struct old_serial_port old_serial_port[] = {
120 SERIAL_PORT_DFNS /* defined in asm/serial.h */
121 };
122
123 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
124
125 #ifdef CONFIG_SERIAL_8250_RSA
126
127 #define PORT_RSA_MAX 4
128 static unsigned long probe_rsa[PORT_RSA_MAX];
129 static unsigned int probe_rsa_count;
130 #endif /* CONFIG_SERIAL_8250_RSA */
131
132 struct uart_8250_port {
133 struct uart_port port;
134 struct timer_list timer; /* "no irq" timer */
135 struct list_head list; /* ports on this IRQ */
136 unsigned short capabilities; /* port capabilities */
137 unsigned short bugs; /* port bugs */
138 unsigned int tx_loadsz; /* transmit fifo load size */
139 unsigned char acr;
140 unsigned char ier;
141 unsigned char lcr;
142 unsigned char mcr;
143 unsigned char mcr_mask; /* mask of user bits */
144 unsigned char mcr_force; /* mask of forced bits */
145 unsigned char cur_iotype; /* Running I/O type */
146
147 /*
148 * Some bits in registers are cleared on a read, so they must
149 * be saved whenever the register is read but the bits will not
150 * be immediately processed.
151 */
152 #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
153 unsigned char lsr_saved_flags;
154 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
155 unsigned char msr_saved_flags;
156 };
157
158 struct irq_info {
159 struct hlist_node node;
160 int irq;
161 spinlock_t lock; /* Protects list not the hash */
162 struct list_head *head;
163 };
164
165 #define NR_IRQ_HASH 32 /* Can be adjusted later */
166 static struct hlist_head irq_lists[NR_IRQ_HASH];
167 static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
168
169 /*
170 * Here we define the default xmit fifo size used for each type of UART.
171 */
172 static const struct serial8250_config uart_config[] = {
173 [PORT_UNKNOWN] = {
174 .name = "unknown",
175 .fifo_size = 1,
176 .tx_loadsz = 1,
177 },
178 [PORT_8250] = {
179 .name = "8250",
180 .fifo_size = 1,
181 .tx_loadsz = 1,
182 },
183 [PORT_16450] = {
184 .name = "16450",
185 .fifo_size = 1,
186 .tx_loadsz = 1,
187 },
188 [PORT_16550] = {
189 .name = "16550",
190 .fifo_size = 1,
191 .tx_loadsz = 1,
192 },
193 [PORT_16550A] = {
194 .name = "16550A",
195 .fifo_size = 16,
196 .tx_loadsz = 16,
197 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
198 .flags = UART_CAP_FIFO,
199 },
200 [PORT_CIRRUS] = {
201 .name = "Cirrus",
202 .fifo_size = 1,
203 .tx_loadsz = 1,
204 },
205 [PORT_16650] = {
206 .name = "ST16650",
207 .fifo_size = 1,
208 .tx_loadsz = 1,
209 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
210 },
211 [PORT_16650V2] = {
212 .name = "ST16650V2",
213 .fifo_size = 32,
214 .tx_loadsz = 16,
215 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
216 UART_FCR_T_TRIG_00,
217 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
218 },
219 [PORT_16750] = {
220 .name = "TI16750",
221 .fifo_size = 64,
222 .tx_loadsz = 64,
223 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
224 UART_FCR7_64BYTE,
225 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
226 },
227 [PORT_STARTECH] = {
228 .name = "Startech",
229 .fifo_size = 1,
230 .tx_loadsz = 1,
231 },
232 [PORT_16C950] = {
233 .name = "16C950/954",
234 .fifo_size = 128,
235 .tx_loadsz = 128,
236 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
237 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
238 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
239 },
240 [PORT_16654] = {
241 .name = "ST16654",
242 .fifo_size = 64,
243 .tx_loadsz = 32,
244 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
245 UART_FCR_T_TRIG_10,
246 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
247 },
248 [PORT_16850] = {
249 .name = "XR16850",
250 .fifo_size = 128,
251 .tx_loadsz = 128,
252 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
253 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
254 },
255 [PORT_RSA] = {
256 .name = "RSA",
257 .fifo_size = 2048,
258 .tx_loadsz = 2048,
259 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
260 .flags = UART_CAP_FIFO,
261 },
262 [PORT_NS16550A] = {
263 .name = "NS16550A",
264 .fifo_size = 16,
265 .tx_loadsz = 16,
266 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
267 .flags = UART_CAP_FIFO | UART_NATSEMI,
268 },
269 [PORT_XSCALE] = {
270 .name = "XScale",
271 .fifo_size = 32,
272 .tx_loadsz = 32,
273 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
274 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
275 },
276 [PORT_RM9000] = {
277 .name = "RM9000",
278 .fifo_size = 16,
279 .tx_loadsz = 16,
280 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
281 .flags = UART_CAP_FIFO,
282 },
283 [PORT_OCTEON] = {
284 .name = "OCTEON",
285 .fifo_size = 64,
286 .tx_loadsz = 64,
287 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
288 .flags = UART_CAP_FIFO,
289 },
290 [PORT_AR7] = {
291 .name = "AR7",
292 .fifo_size = 16,
293 .tx_loadsz = 16,
294 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
295 .flags = UART_CAP_FIFO | UART_CAP_AFE,
296 },
297 [PORT_U6_16550A] = {
298 .name = "U6_16550A",
299 .fifo_size = 64,
300 .tx_loadsz = 64,
301 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
302 .flags = UART_CAP_FIFO | UART_CAP_AFE,
303 },
304 [PORT_TEGRA] = {
305 .name = "Tegra",
306 .fifo_size = 32,
307 .tx_loadsz = 8,
308 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
309 UART_FCR_T_TRIG_01,
310 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
311 },
312 };
313
314 #if defined(CONFIG_MIPS_ALCHEMY)
315
316 /* Au1x00 UART hardware has a weird register layout */
317 static const u8 au_io_in_map[] = {
318 [UART_RX] = 0,
319 [UART_IER] = 2,
320 [UART_IIR] = 3,
321 [UART_LCR] = 5,
322 [UART_MCR] = 6,
323 [UART_LSR] = 7,
324 [UART_MSR] = 8,
325 };
326
327 static const u8 au_io_out_map[] = {
328 [UART_TX] = 1,
329 [UART_IER] = 2,
330 [UART_FCR] = 4,
331 [UART_LCR] = 5,
332 [UART_MCR] = 6,
333 };
334
335 /* sane hardware needs no mapping */
336 static inline int map_8250_in_reg(struct uart_port *p, int offset)
337 {
338 if (p->iotype != UPIO_AU)
339 return offset;
340 return au_io_in_map[offset];
341 }
342
343 static inline int map_8250_out_reg(struct uart_port *p, int offset)
344 {
345 if (p->iotype != UPIO_AU)
346 return offset;
347 return au_io_out_map[offset];
348 }
349
350 #elif defined(CONFIG_SERIAL_8250_RM9K)
351
352 static const u8
353 regmap_in[8] = {
354 [UART_RX] = 0x00,
355 [UART_IER] = 0x0c,
356 [UART_IIR] = 0x14,
357 [UART_LCR] = 0x1c,
358 [UART_MCR] = 0x20,
359 [UART_LSR] = 0x24,
360 [UART_MSR] = 0x28,
361 [UART_SCR] = 0x2c
362 },
363 regmap_out[8] = {
364 [UART_TX] = 0x04,
365 [UART_IER] = 0x0c,
366 [UART_FCR] = 0x18,
367 [UART_LCR] = 0x1c,
368 [UART_MCR] = 0x20,
369 [UART_LSR] = 0x24,
370 [UART_MSR] = 0x28,
371 [UART_SCR] = 0x2c
372 };
373
374 static inline int map_8250_in_reg(struct uart_port *p, int offset)
375 {
376 if (p->iotype != UPIO_RM9000)
377 return offset;
378 return regmap_in[offset];
379 }
380
381 static inline int map_8250_out_reg(struct uart_port *p, int offset)
382 {
383 if (p->iotype != UPIO_RM9000)
384 return offset;
385 return regmap_out[offset];
386 }
387
388 #else
389
390 /* sane hardware needs no mapping */
391 #define map_8250_in_reg(up, offset) (offset)
392 #define map_8250_out_reg(up, offset) (offset)
393
394 #endif
395
396 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
397 {
398 offset = map_8250_in_reg(p, offset) << p->regshift;
399 outb(p->hub6 - 1 + offset, p->iobase);
400 return inb(p->iobase + 1);
401 }
402
403 static void hub6_serial_out(struct uart_port *p, int offset, int value)
404 {
405 offset = map_8250_out_reg(p, offset) << p->regshift;
406 outb(p->hub6 - 1 + offset, p->iobase);
407 outb(value, p->iobase + 1);
408 }
409
410 static unsigned int mem_serial_in(struct uart_port *p, int offset)
411 {
412 offset = map_8250_in_reg(p, offset) << p->regshift;
413 return readb(p->membase + offset);
414 }
415
416 static void mem_serial_out(struct uart_port *p, int offset, int value)
417 {
418 offset = map_8250_out_reg(p, offset) << p->regshift;
419 writeb(value, p->membase + offset);
420 }
421
422 static void mem32_serial_out(struct uart_port *p, int offset, int value)
423 {
424 offset = map_8250_out_reg(p, offset) << p->regshift;
425 writel(value, p->membase + offset);
426 }
427
428 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
429 {
430 offset = map_8250_in_reg(p, offset) << p->regshift;
431 return readl(p->membase + offset);
432 }
433
434 static unsigned int au_serial_in(struct uart_port *p, int offset)
435 {
436 offset = map_8250_in_reg(p, offset) << p->regshift;
437 return __raw_readl(p->membase + offset);
438 }
439
440 static void au_serial_out(struct uart_port *p, int offset, int value)
441 {
442 offset = map_8250_out_reg(p, offset) << p->regshift;
443 __raw_writel(value, p->membase + offset);
444 }
445
446 static unsigned int tsi_serial_in(struct uart_port *p, int offset)
447 {
448 unsigned int tmp;
449 offset = map_8250_in_reg(p, offset) << p->regshift;
450 if (offset == UART_IIR) {
451 tmp = readl(p->membase + (UART_IIR & ~3));
452 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
453 } else
454 return readb(p->membase + offset);
455 }
456
457 static void tsi_serial_out(struct uart_port *p, int offset, int value)
458 {
459 offset = map_8250_out_reg(p, offset) << p->regshift;
460 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
461 writeb(value, p->membase + offset);
462 }
463
464 static unsigned int io_serial_in(struct uart_port *p, int offset)
465 {
466 offset = map_8250_in_reg(p, offset) << p->regshift;
467 return inb(p->iobase + offset);
468 }
469
470 static void io_serial_out(struct uart_port *p, int offset, int value)
471 {
472 offset = map_8250_out_reg(p, offset) << p->regshift;
473 outb(value, p->iobase + offset);
474 }
475
476 static int serial8250_default_handle_irq(struct uart_port *port);
477
478 static void set_io_from_upio(struct uart_port *p)
479 {
480 struct uart_8250_port *up =
481 container_of(p, struct uart_8250_port, port);
482 switch (p->iotype) {
483 case UPIO_HUB6:
484 p->serial_in = hub6_serial_in;
485 p->serial_out = hub6_serial_out;
486 break;
487
488 case UPIO_MEM:
489 p->serial_in = mem_serial_in;
490 p->serial_out = mem_serial_out;
491 break;
492
493 case UPIO_RM9000:
494 case UPIO_MEM32:
495 p->serial_in = mem32_serial_in;
496 p->serial_out = mem32_serial_out;
497 break;
498
499 case UPIO_AU:
500 p->serial_in = au_serial_in;
501 p->serial_out = au_serial_out;
502 break;
503
504 case UPIO_TSI:
505 p->serial_in = tsi_serial_in;
506 p->serial_out = tsi_serial_out;
507 break;
508
509 default:
510 p->serial_in = io_serial_in;
511 p->serial_out = io_serial_out;
512 break;
513 }
514 /* Remember loaded iotype */
515 up->cur_iotype = p->iotype;
516 p->handle_irq = serial8250_default_handle_irq;
517 }
518
519 static void
520 serial_out_sync(struct uart_8250_port *up, int offset, int value)
521 {
522 struct uart_port *p = &up->port;
523 switch (p->iotype) {
524 case UPIO_MEM:
525 case UPIO_MEM32:
526 case UPIO_AU:
527 p->serial_out(p, offset, value);
528 p->serial_in(p, UART_LCR); /* safe, no side-effects */
529 break;
530 default:
531 p->serial_out(p, offset, value);
532 }
533 }
534
535 #define serial_in(up, offset) \
536 (up->port.serial_in(&(up)->port, (offset)))
537 #define serial_out(up, offset, value) \
538 (up->port.serial_out(&(up)->port, (offset), (value)))
539 /*
540 * We used to support using pause I/O for certain machines. We
541 * haven't supported this for a while, but just in case it's badly
542 * needed for certain old 386 machines, I've left these #define's
543 * in....
544 */
545 #define serial_inp(up, offset) serial_in(up, offset)
546 #define serial_outp(up, offset, value) serial_out(up, offset, value)
547
548 /* Uart divisor latch read */
549 static inline int _serial_dl_read(struct uart_8250_port *up)
550 {
551 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
552 }
553
554 /* Uart divisor latch write */
555 static inline void _serial_dl_write(struct uart_8250_port *up, int value)
556 {
557 serial_outp(up, UART_DLL, value & 0xff);
558 serial_outp(up, UART_DLM, value >> 8 & 0xff);
559 }
560
561 #if defined(CONFIG_MIPS_ALCHEMY)
562 /* Au1x00 haven't got a standard divisor latch */
563 static int serial_dl_read(struct uart_8250_port *up)
564 {
565 if (up->port.iotype == UPIO_AU)
566 return __raw_readl(up->port.membase + 0x28);
567 else
568 return _serial_dl_read(up);
569 }
570
571 static void serial_dl_write(struct uart_8250_port *up, int value)
572 {
573 if (up->port.iotype == UPIO_AU)
574 __raw_writel(value, up->port.membase + 0x28);
575 else
576 _serial_dl_write(up, value);
577 }
578 #elif defined(CONFIG_SERIAL_8250_RM9K)
579 static int serial_dl_read(struct uart_8250_port *up)
580 {
581 return (up->port.iotype == UPIO_RM9000) ?
582 (((__raw_readl(up->port.membase + 0x10) << 8) |
583 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
584 _serial_dl_read(up);
585 }
586
587 static void serial_dl_write(struct uart_8250_port *up, int value)
588 {
589 if (up->port.iotype == UPIO_RM9000) {
590 __raw_writel(value, up->port.membase + 0x08);
591 __raw_writel(value >> 8, up->port.membase + 0x10);
592 } else {
593 _serial_dl_write(up, value);
594 }
595 }
596 #else
597 #define serial_dl_read(up) _serial_dl_read(up)
598 #define serial_dl_write(up, value) _serial_dl_write(up, value)
599 #endif
600
601 /*
602 * For the 16C950
603 */
604 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
605 {
606 serial_out(up, UART_SCR, offset);
607 serial_out(up, UART_ICR, value);
608 }
609
610 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
611 {
612 unsigned int value;
613
614 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
615 serial_out(up, UART_SCR, offset);
616 value = serial_in(up, UART_ICR);
617 serial_icr_write(up, UART_ACR, up->acr);
618
619 return value;
620 }
621
622 /*
623 * FIFO support.
624 */
625 static void serial8250_clear_fifos(struct uart_8250_port *p)
626 {
627 if (p->capabilities & UART_CAP_FIFO) {
628 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
629 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
630 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
631 serial_outp(p, UART_FCR, 0);
632 }
633 }
634
635 /*
636 * IER sleep support. UARTs which have EFRs need the "extended
637 * capability" bit enabled. Note that on XR16C850s, we need to
638 * reset LCR to write to IER.
639 */
640 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
641 {
642 if (p->capabilities & UART_CAP_SLEEP) {
643 if (p->capabilities & UART_CAP_EFR) {
644 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
645 serial_outp(p, UART_EFR, UART_EFR_ECB);
646 serial_outp(p, UART_LCR, 0);
647 }
648 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
649 if (p->capabilities & UART_CAP_EFR) {
650 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
651 serial_outp(p, UART_EFR, 0);
652 serial_outp(p, UART_LCR, 0);
653 }
654 }
655 }
656
657 #ifdef CONFIG_SERIAL_8250_RSA
658 /*
659 * Attempts to turn on the RSA FIFO. Returns zero on failure.
660 * We set the port uart clock rate if we succeed.
661 */
662 static int __enable_rsa(struct uart_8250_port *up)
663 {
664 unsigned char mode;
665 int result;
666
667 mode = serial_inp(up, UART_RSA_MSR);
668 result = mode & UART_RSA_MSR_FIFO;
669
670 if (!result) {
671 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
672 mode = serial_inp(up, UART_RSA_MSR);
673 result = mode & UART_RSA_MSR_FIFO;
674 }
675
676 if (result)
677 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
678
679 return result;
680 }
681
682 static void enable_rsa(struct uart_8250_port *up)
683 {
684 if (up->port.type == PORT_RSA) {
685 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
686 spin_lock_irq(&up->port.lock);
687 __enable_rsa(up);
688 spin_unlock_irq(&up->port.lock);
689 }
690 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
691 serial_outp(up, UART_RSA_FRR, 0);
692 }
693 }
694
695 /*
696 * Attempts to turn off the RSA FIFO. Returns zero on failure.
697 * It is unknown why interrupts were disabled in here. However,
698 * the caller is expected to preserve this behaviour by grabbing
699 * the spinlock before calling this function.
700 */
701 static void disable_rsa(struct uart_8250_port *up)
702 {
703 unsigned char mode;
704 int result;
705
706 if (up->port.type == PORT_RSA &&
707 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
708 spin_lock_irq(&up->port.lock);
709
710 mode = serial_inp(up, UART_RSA_MSR);
711 result = !(mode & UART_RSA_MSR_FIFO);
712
713 if (!result) {
714 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
715 mode = serial_inp(up, UART_RSA_MSR);
716 result = !(mode & UART_RSA_MSR_FIFO);
717 }
718
719 if (result)
720 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
721 spin_unlock_irq(&up->port.lock);
722 }
723 }
724 #endif /* CONFIG_SERIAL_8250_RSA */
725
726 /*
727 * This is a quickie test to see how big the FIFO is.
728 * It doesn't work at all the time, more's the pity.
729 */
730 static int size_fifo(struct uart_8250_port *up)
731 {
732 unsigned char old_fcr, old_mcr, old_lcr;
733 unsigned short old_dl;
734 int count;
735
736 old_lcr = serial_inp(up, UART_LCR);
737 serial_outp(up, UART_LCR, 0);
738 old_fcr = serial_inp(up, UART_FCR);
739 old_mcr = serial_inp(up, UART_MCR);
740 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
741 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
742 serial_outp(up, UART_MCR, UART_MCR_LOOP);
743 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
744 old_dl = serial_dl_read(up);
745 serial_dl_write(up, 0x0001);
746 serial_outp(up, UART_LCR, 0x03);
747 for (count = 0; count < 256; count++)
748 serial_outp(up, UART_TX, count);
749 mdelay(20);/* FIXME - schedule_timeout */
750 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
751 (count < 256); count++)
752 serial_inp(up, UART_RX);
753 serial_outp(up, UART_FCR, old_fcr);
754 serial_outp(up, UART_MCR, old_mcr);
755 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
756 serial_dl_write(up, old_dl);
757 serial_outp(up, UART_LCR, old_lcr);
758
759 return count;
760 }
761
762 /*
763 * Read UART ID using the divisor method - set DLL and DLM to zero
764 * and the revision will be in DLL and device type in DLM. We
765 * preserve the device state across this.
766 */
767 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
768 {
769 unsigned char old_dll, old_dlm, old_lcr;
770 unsigned int id;
771
772 old_lcr = serial_inp(p, UART_LCR);
773 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_A);
774
775 old_dll = serial_inp(p, UART_DLL);
776 old_dlm = serial_inp(p, UART_DLM);
777
778 serial_outp(p, UART_DLL, 0);
779 serial_outp(p, UART_DLM, 0);
780
781 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
782
783 serial_outp(p, UART_DLL, old_dll);
784 serial_outp(p, UART_DLM, old_dlm);
785 serial_outp(p, UART_LCR, old_lcr);
786
787 return id;
788 }
789
790 /*
791 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
792 * When this function is called we know it is at least a StarTech
793 * 16650 V2, but it might be one of several StarTech UARTs, or one of
794 * its clones. (We treat the broken original StarTech 16650 V1 as a
795 * 16550, and why not? Startech doesn't seem to even acknowledge its
796 * existence.)
797 *
798 * What evil have men's minds wrought...
799 */
800 static void autoconfig_has_efr(struct uart_8250_port *up)
801 {
802 unsigned int id1, id2, id3, rev;
803
804 /*
805 * Everything with an EFR has SLEEP
806 */
807 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
808
809 /*
810 * First we check to see if it's an Oxford Semiconductor UART.
811 *
812 * If we have to do this here because some non-National
813 * Semiconductor clone chips lock up if you try writing to the
814 * LSR register (which serial_icr_read does)
815 */
816
817 /*
818 * Check for Oxford Semiconductor 16C950.
819 *
820 * EFR [4] must be set else this test fails.
821 *
822 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
823 * claims that it's needed for 952 dual UART's (which are not
824 * recommended for new designs).
825 */
826 up->acr = 0;
827 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
828 serial_out(up, UART_EFR, UART_EFR_ECB);
829 serial_out(up, UART_LCR, 0x00);
830 id1 = serial_icr_read(up, UART_ID1);
831 id2 = serial_icr_read(up, UART_ID2);
832 id3 = serial_icr_read(up, UART_ID3);
833 rev = serial_icr_read(up, UART_REV);
834
835 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
836
837 if (id1 == 0x16 && id2 == 0xC9 &&
838 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
839 up->port.type = PORT_16C950;
840
841 /*
842 * Enable work around for the Oxford Semiconductor 952 rev B
843 * chip which causes it to seriously miscalculate baud rates
844 * when DLL is 0.
845 */
846 if (id3 == 0x52 && rev == 0x01)
847 up->bugs |= UART_BUG_QUOT;
848 return;
849 }
850
851 /*
852 * We check for a XR16C850 by setting DLL and DLM to 0, and then
853 * reading back DLL and DLM. The chip type depends on the DLM
854 * value read back:
855 * 0x10 - XR16C850 and the DLL contains the chip revision.
856 * 0x12 - XR16C2850.
857 * 0x14 - XR16C854.
858 */
859 id1 = autoconfig_read_divisor_id(up);
860 DEBUG_AUTOCONF("850id=%04x ", id1);
861
862 id2 = id1 >> 8;
863 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
864 up->port.type = PORT_16850;
865 return;
866 }
867
868 /*
869 * It wasn't an XR16C850.
870 *
871 * We distinguish between the '654 and the '650 by counting
872 * how many bytes are in the FIFO. I'm using this for now,
873 * since that's the technique that was sent to me in the
874 * serial driver update, but I'm not convinced this works.
875 * I've had problems doing this in the past. -TYT
876 */
877 if (size_fifo(up) == 64)
878 up->port.type = PORT_16654;
879 else
880 up->port.type = PORT_16650V2;
881 }
882
883 /*
884 * We detected a chip without a FIFO. Only two fall into
885 * this category - the original 8250 and the 16450. The
886 * 16450 has a scratch register (accessible with LCR=0)
887 */
888 static void autoconfig_8250(struct uart_8250_port *up)
889 {
890 unsigned char scratch, status1, status2;
891
892 up->port.type = PORT_8250;
893
894 scratch = serial_in(up, UART_SCR);
895 serial_outp(up, UART_SCR, 0xa5);
896 status1 = serial_in(up, UART_SCR);
897 serial_outp(up, UART_SCR, 0x5a);
898 status2 = serial_in(up, UART_SCR);
899 serial_outp(up, UART_SCR, scratch);
900
901 if (status1 == 0xa5 && status2 == 0x5a)
902 up->port.type = PORT_16450;
903 }
904
905 static int broken_efr(struct uart_8250_port *up)
906 {
907 /*
908 * Exar ST16C2550 "A2" devices incorrectly detect as
909 * having an EFR, and report an ID of 0x0201. See
910 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
911 */
912 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
913 return 1;
914
915 return 0;
916 }
917
918 static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
919 {
920 unsigned char status;
921
922 status = serial_in(up, 0x04); /* EXCR2 */
923 #define PRESL(x) ((x) & 0x30)
924 if (PRESL(status) == 0x10) {
925 /* already in high speed mode */
926 return 0;
927 } else {
928 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
929 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
930 serial_outp(up, 0x04, status);
931 }
932 return 1;
933 }
934
935 /*
936 * We know that the chip has FIFOs. Does it have an EFR? The
937 * EFR is located in the same register position as the IIR and
938 * we know the top two bits of the IIR are currently set. The
939 * EFR should contain zero. Try to read the EFR.
940 */
941 static void autoconfig_16550a(struct uart_8250_port *up)
942 {
943 unsigned char status1, status2;
944 unsigned int iersave;
945
946 up->port.type = PORT_16550A;
947 up->capabilities |= UART_CAP_FIFO;
948
949 /*
950 * Check for presence of the EFR when DLAB is set.
951 * Only ST16C650V1 UARTs pass this test.
952 */
953 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
954 if (serial_in(up, UART_EFR) == 0) {
955 serial_outp(up, UART_EFR, 0xA8);
956 if (serial_in(up, UART_EFR) != 0) {
957 DEBUG_AUTOCONF("EFRv1 ");
958 up->port.type = PORT_16650;
959 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
960 } else {
961 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
962 }
963 serial_outp(up, UART_EFR, 0);
964 return;
965 }
966
967 /*
968 * Maybe it requires 0xbf to be written to the LCR.
969 * (other ST16C650V2 UARTs, TI16C752A, etc)
970 */
971 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
972 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
973 DEBUG_AUTOCONF("EFRv2 ");
974 autoconfig_has_efr(up);
975 return;
976 }
977
978 /*
979 * Check for a National Semiconductor SuperIO chip.
980 * Attempt to switch to bank 2, read the value of the LOOP bit
981 * from EXCR1. Switch back to bank 0, change it in MCR. Then
982 * switch back to bank 2, read it from EXCR1 again and check
983 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
984 */
985 serial_outp(up, UART_LCR, 0);
986 status1 = serial_in(up, UART_MCR);
987 serial_outp(up, UART_LCR, 0xE0);
988 status2 = serial_in(up, 0x02); /* EXCR1 */
989
990 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
991 serial_outp(up, UART_LCR, 0);
992 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
993 serial_outp(up, UART_LCR, 0xE0);
994 status2 = serial_in(up, 0x02); /* EXCR1 */
995 serial_outp(up, UART_LCR, 0);
996 serial_outp(up, UART_MCR, status1);
997
998 if ((status2 ^ status1) & UART_MCR_LOOP) {
999 unsigned short quot;
1000
1001 serial_outp(up, UART_LCR, 0xE0);
1002
1003 quot = serial_dl_read(up);
1004 quot <<= 3;
1005
1006 if (ns16550a_goto_highspeed(up))
1007 serial_dl_write(up, quot);
1008
1009 serial_outp(up, UART_LCR, 0);
1010
1011 up->port.uartclk = 921600*16;
1012 up->port.type = PORT_NS16550A;
1013 up->capabilities |= UART_NATSEMI;
1014 return;
1015 }
1016 }
1017
1018 /*
1019 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1020 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1021 * Try setting it with and without DLAB set. Cheap clones
1022 * set bit 5 without DLAB set.
1023 */
1024 serial_outp(up, UART_LCR, 0);
1025 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1026 status1 = serial_in(up, UART_IIR) >> 5;
1027 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1028 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
1029 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1030 status2 = serial_in(up, UART_IIR) >> 5;
1031 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1032 serial_outp(up, UART_LCR, 0);
1033
1034 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1035
1036 if (status1 == 6 && status2 == 7) {
1037 up->port.type = PORT_16750;
1038 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1039 return;
1040 }
1041
1042 /*
1043 * Try writing and reading the UART_IER_UUE bit (b6).
1044 * If it works, this is probably one of the Xscale platform's
1045 * internal UARTs.
1046 * We're going to explicitly set the UUE bit to 0 before
1047 * trying to write and read a 1 just to make sure it's not
1048 * already a 1 and maybe locked there before we even start start.
1049 */
1050 iersave = serial_in(up, UART_IER);
1051 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1052 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1053 /*
1054 * OK it's in a known zero state, try writing and reading
1055 * without disturbing the current state of the other bits.
1056 */
1057 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1058 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1059 /*
1060 * It's an Xscale.
1061 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1062 */
1063 DEBUG_AUTOCONF("Xscale ");
1064 up->port.type = PORT_XSCALE;
1065 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1066 return;
1067 }
1068 } else {
1069 /*
1070 * If we got here we couldn't force the IER_UUE bit to 0.
1071 * Log it and continue.
1072 */
1073 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1074 }
1075 serial_outp(up, UART_IER, iersave);
1076
1077 /*
1078 * We distinguish between 16550A and U6 16550A by counting
1079 * how many bytes are in the FIFO.
1080 */
1081 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1082 up->port.type = PORT_U6_16550A;
1083 up->capabilities |= UART_CAP_AFE;
1084 }
1085 }
1086
1087 /*
1088 * This routine is called by rs_init() to initialize a specific serial
1089 * port. It determines what type of UART chip this serial port is
1090 * using: 8250, 16450, 16550, 16550A. The important question is
1091 * whether or not this UART is a 16550A or not, since this will
1092 * determine whether or not we can use its FIFO features or not.
1093 */
1094 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1095 {
1096 unsigned char status1, scratch, scratch2, scratch3;
1097 unsigned char save_lcr, save_mcr;
1098 unsigned long flags;
1099
1100 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1101 return;
1102
1103 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1104 serial_index(&up->port), up->port.iobase, up->port.membase);
1105
1106 /*
1107 * We really do need global IRQs disabled here - we're going to
1108 * be frobbing the chips IRQ enable register to see if it exists.
1109 */
1110 spin_lock_irqsave(&up->port.lock, flags);
1111
1112 up->capabilities = 0;
1113 up->bugs = 0;
1114
1115 if (!(up->port.flags & UPF_BUGGY_UART)) {
1116 /*
1117 * Do a simple existence test first; if we fail this,
1118 * there's no point trying anything else.
1119 *
1120 * 0x80 is used as a nonsense port to prevent against
1121 * false positives due to ISA bus float. The
1122 * assumption is that 0x80 is a non-existent port;
1123 * which should be safe since include/asm/io.h also
1124 * makes this assumption.
1125 *
1126 * Note: this is safe as long as MCR bit 4 is clear
1127 * and the device is in "PC" mode.
1128 */
1129 scratch = serial_inp(up, UART_IER);
1130 serial_outp(up, UART_IER, 0);
1131 #ifdef __i386__
1132 outb(0xff, 0x080);
1133 #endif
1134 /*
1135 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1136 * 16C754B) allow only to modify them if an EFR bit is set.
1137 */
1138 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1139 serial_outp(up, UART_IER, 0x0F);
1140 #ifdef __i386__
1141 outb(0, 0x080);
1142 #endif
1143 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1144 serial_outp(up, UART_IER, scratch);
1145 if (scratch2 != 0 || scratch3 != 0x0F) {
1146 /*
1147 * We failed; there's nothing here
1148 */
1149 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1150 scratch2, scratch3);
1151 goto out;
1152 }
1153 }
1154
1155 save_mcr = serial_in(up, UART_MCR);
1156 save_lcr = serial_in(up, UART_LCR);
1157
1158 /*
1159 * Check to see if a UART is really there. Certain broken
1160 * internal modems based on the Rockwell chipset fail this
1161 * test, because they apparently don't implement the loopback
1162 * test mode. So this test is skipped on the COM 1 through
1163 * COM 4 ports. This *should* be safe, since no board
1164 * manufacturer would be stupid enough to design a board
1165 * that conflicts with COM 1-4 --- we hope!
1166 */
1167 if (!(up->port.flags & UPF_SKIP_TEST)) {
1168 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1169 status1 = serial_inp(up, UART_MSR) & 0xF0;
1170 serial_outp(up, UART_MCR, save_mcr);
1171 if (status1 != 0x90) {
1172 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1173 status1);
1174 goto out;
1175 }
1176 }
1177
1178 /*
1179 * We're pretty sure there's a port here. Lets find out what
1180 * type of port it is. The IIR top two bits allows us to find
1181 * out if it's 8250 or 16450, 16550, 16550A or later. This
1182 * determines what we test for next.
1183 *
1184 * We also initialise the EFR (if any) to zero for later. The
1185 * EFR occupies the same register location as the FCR and IIR.
1186 */
1187 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1188 serial_outp(up, UART_EFR, 0);
1189 serial_outp(up, UART_LCR, 0);
1190
1191 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1192 scratch = serial_in(up, UART_IIR) >> 6;
1193
1194 DEBUG_AUTOCONF("iir=%d ", scratch);
1195
1196 switch (scratch) {
1197 case 0:
1198 autoconfig_8250(up);
1199 break;
1200 case 1:
1201 up->port.type = PORT_UNKNOWN;
1202 break;
1203 case 2:
1204 up->port.type = PORT_16550;
1205 break;
1206 case 3:
1207 autoconfig_16550a(up);
1208 break;
1209 }
1210
1211 #ifdef CONFIG_SERIAL_8250_RSA
1212 /*
1213 * Only probe for RSA ports if we got the region.
1214 */
1215 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1216 int i;
1217
1218 for (i = 0 ; i < probe_rsa_count; ++i) {
1219 if (probe_rsa[i] == up->port.iobase &&
1220 __enable_rsa(up)) {
1221 up->port.type = PORT_RSA;
1222 break;
1223 }
1224 }
1225 }
1226 #endif
1227
1228 serial_outp(up, UART_LCR, save_lcr);
1229
1230 if (up->capabilities != uart_config[up->port.type].flags) {
1231 printk(KERN_WARNING
1232 "ttyS%d: detected caps %08x should be %08x\n",
1233 serial_index(&up->port), up->capabilities,
1234 uart_config[up->port.type].flags);
1235 }
1236
1237 up->port.fifosize = uart_config[up->port.type].fifo_size;
1238 up->capabilities = uart_config[up->port.type].flags;
1239 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1240
1241 if (up->port.type == PORT_UNKNOWN)
1242 goto out;
1243
1244 /*
1245 * Reset the UART.
1246 */
1247 #ifdef CONFIG_SERIAL_8250_RSA
1248 if (up->port.type == PORT_RSA)
1249 serial_outp(up, UART_RSA_FRR, 0);
1250 #endif
1251 serial_outp(up, UART_MCR, save_mcr);
1252 serial8250_clear_fifos(up);
1253 serial_in(up, UART_RX);
1254 if (up->capabilities & UART_CAP_UUE)
1255 serial_outp(up, UART_IER, UART_IER_UUE);
1256 else
1257 serial_outp(up, UART_IER, 0);
1258
1259 out:
1260 spin_unlock_irqrestore(&up->port.lock, flags);
1261 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1262 }
1263
1264 static void autoconfig_irq(struct uart_8250_port *up)
1265 {
1266 unsigned char save_mcr, save_ier;
1267 unsigned char save_ICP = 0;
1268 unsigned int ICP = 0;
1269 unsigned long irqs;
1270 int irq;
1271
1272 if (up->port.flags & UPF_FOURPORT) {
1273 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1274 save_ICP = inb_p(ICP);
1275 outb_p(0x80, ICP);
1276 (void) inb_p(ICP);
1277 }
1278
1279 /* forget possible initially masked and pending IRQ */
1280 probe_irq_off(probe_irq_on());
1281 save_mcr = serial_inp(up, UART_MCR);
1282 save_ier = serial_inp(up, UART_IER);
1283 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1284
1285 irqs = probe_irq_on();
1286 serial_outp(up, UART_MCR, 0);
1287 udelay(10);
1288 if (up->port.flags & UPF_FOURPORT) {
1289 serial_outp(up, UART_MCR,
1290 UART_MCR_DTR | UART_MCR_RTS);
1291 } else {
1292 serial_outp(up, UART_MCR,
1293 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1294 }
1295 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1296 (void)serial_inp(up, UART_LSR);
1297 (void)serial_inp(up, UART_RX);
1298 (void)serial_inp(up, UART_IIR);
1299 (void)serial_inp(up, UART_MSR);
1300 serial_outp(up, UART_TX, 0xFF);
1301 udelay(20);
1302 irq = probe_irq_off(irqs);
1303
1304 serial_outp(up, UART_MCR, save_mcr);
1305 serial_outp(up, UART_IER, save_ier);
1306
1307 if (up->port.flags & UPF_FOURPORT)
1308 outb_p(save_ICP, ICP);
1309
1310 up->port.irq = (irq > 0) ? irq : 0;
1311 }
1312
1313 static inline void __stop_tx(struct uart_8250_port *p)
1314 {
1315 if (p->ier & UART_IER_THRI) {
1316 p->ier &= ~UART_IER_THRI;
1317 serial_out(p, UART_IER, p->ier);
1318 }
1319 }
1320
1321 static void serial8250_stop_tx(struct uart_port *port)
1322 {
1323 struct uart_8250_port *up =
1324 container_of(port, struct uart_8250_port, port);
1325
1326 __stop_tx(up);
1327
1328 /*
1329 * We really want to stop the transmitter from sending.
1330 */
1331 if (up->port.type == PORT_16C950) {
1332 up->acr |= UART_ACR_TXDIS;
1333 serial_icr_write(up, UART_ACR, up->acr);
1334 }
1335 }
1336
1337 static void transmit_chars(struct uart_8250_port *up);
1338
1339 static void serial8250_start_tx(struct uart_port *port)
1340 {
1341 struct uart_8250_port *up =
1342 container_of(port, struct uart_8250_port, port);
1343
1344 if (!(up->ier & UART_IER_THRI)) {
1345 up->ier |= UART_IER_THRI;
1346 serial_out(up, UART_IER, up->ier);
1347
1348 if (up->bugs & UART_BUG_TXEN) {
1349 unsigned char lsr;
1350 lsr = serial_in(up, UART_LSR);
1351 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1352 if ((up->port.type == PORT_RM9000) ?
1353 (lsr & UART_LSR_THRE) :
1354 (lsr & UART_LSR_TEMT))
1355 transmit_chars(up);
1356 }
1357 }
1358
1359 /*
1360 * Re-enable the transmitter if we disabled it.
1361 */
1362 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1363 up->acr &= ~UART_ACR_TXDIS;
1364 serial_icr_write(up, UART_ACR, up->acr);
1365 }
1366 }
1367
1368 static void serial8250_stop_rx(struct uart_port *port)
1369 {
1370 struct uart_8250_port *up =
1371 container_of(port, struct uart_8250_port, port);
1372
1373 up->ier &= ~UART_IER_RLSI;
1374 up->port.read_status_mask &= ~UART_LSR_DR;
1375 serial_out(up, UART_IER, up->ier);
1376 }
1377
1378 static void serial8250_enable_ms(struct uart_port *port)
1379 {
1380 struct uart_8250_port *up =
1381 container_of(port, struct uart_8250_port, port);
1382
1383 /* no MSR capabilities */
1384 if (up->bugs & UART_BUG_NOMSR)
1385 return;
1386
1387 up->ier |= UART_IER_MSI;
1388 serial_out(up, UART_IER, up->ier);
1389 }
1390
1391 /*
1392 * Clear the Tegra rx fifo after a break
1393 *
1394 * FIXME: This needs to become a port specific callback once we have a
1395 * framework for this
1396 */
1397 static void clear_rx_fifo(struct uart_8250_port *up)
1398 {
1399 unsigned int status, tmout = 10000;
1400 do {
1401 status = serial_in(up, UART_LSR);
1402 if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
1403 status = serial_in(up, UART_RX);
1404 else
1405 break;
1406 if (--tmout == 0)
1407 break;
1408 udelay(1);
1409 } while (1);
1410 }
1411
1412 static void
1413 receive_chars(struct uart_8250_port *up, unsigned int *status)
1414 {
1415 struct tty_struct *tty = up->port.state->port.tty;
1416 unsigned char ch, lsr = *status;
1417 int max_count = 256;
1418 char flag;
1419
1420 do {
1421 if (likely(lsr & UART_LSR_DR))
1422 ch = serial_inp(up, UART_RX);
1423 else
1424 /*
1425 * Intel 82571 has a Serial Over Lan device that will
1426 * set UART_LSR_BI without setting UART_LSR_DR when
1427 * it receives a break. To avoid reading from the
1428 * receive buffer without UART_LSR_DR bit set, we
1429 * just force the read character to be 0
1430 */
1431 ch = 0;
1432
1433 flag = TTY_NORMAL;
1434 up->port.icount.rx++;
1435
1436 lsr |= up->lsr_saved_flags;
1437 up->lsr_saved_flags = 0;
1438
1439 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1440 /*
1441 * For statistics only
1442 */
1443 if (lsr & UART_LSR_BI) {
1444 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1445 up->port.icount.brk++;
1446 /*
1447 * If tegra port then clear the rx fifo to
1448 * accept another break/character.
1449 */
1450 if (up->port.type == PORT_TEGRA)
1451 clear_rx_fifo(up);
1452
1453 /*
1454 * We do the SysRQ and SAK checking
1455 * here because otherwise the break
1456 * may get masked by ignore_status_mask
1457 * or read_status_mask.
1458 */
1459 if (uart_handle_break(&up->port))
1460 goto ignore_char;
1461 } else if (lsr & UART_LSR_PE)
1462 up->port.icount.parity++;
1463 else if (lsr & UART_LSR_FE)
1464 up->port.icount.frame++;
1465 if (lsr & UART_LSR_OE)
1466 up->port.icount.overrun++;
1467
1468 /*
1469 * Mask off conditions which should be ignored.
1470 */
1471 lsr &= up->port.read_status_mask;
1472
1473 if (lsr & UART_LSR_BI) {
1474 DEBUG_INTR("handling break....");
1475 flag = TTY_BREAK;
1476 } else if (lsr & UART_LSR_PE)
1477 flag = TTY_PARITY;
1478 else if (lsr & UART_LSR_FE)
1479 flag = TTY_FRAME;
1480 }
1481 if (uart_handle_sysrq_char(&up->port, ch))
1482 goto ignore_char;
1483
1484 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1485
1486 ignore_char:
1487 lsr = serial_inp(up, UART_LSR);
1488 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1489 spin_unlock(&up->port.lock);
1490 tty_flip_buffer_push(tty);
1491 spin_lock(&up->port.lock);
1492 *status = lsr;
1493 }
1494
1495 static void transmit_chars(struct uart_8250_port *up)
1496 {
1497 struct circ_buf *xmit = &up->port.state->xmit;
1498 int count;
1499
1500 if (up->port.x_char) {
1501 serial_outp(up, UART_TX, up->port.x_char);
1502 up->port.icount.tx++;
1503 up->port.x_char = 0;
1504 return;
1505 }
1506 if (uart_tx_stopped(&up->port)) {
1507 serial8250_stop_tx(&up->port);
1508 return;
1509 }
1510 if (uart_circ_empty(xmit)) {
1511 __stop_tx(up);
1512 return;
1513 }
1514
1515 count = up->tx_loadsz;
1516 do {
1517 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1518 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1519 up->port.icount.tx++;
1520 if (uart_circ_empty(xmit))
1521 break;
1522 } while (--count > 0);
1523
1524 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1525 uart_write_wakeup(&up->port);
1526
1527 DEBUG_INTR("THRE...");
1528
1529 if (uart_circ_empty(xmit))
1530 __stop_tx(up);
1531 }
1532
1533 static unsigned int check_modem_status(struct uart_8250_port *up)
1534 {
1535 unsigned int status = serial_in(up, UART_MSR);
1536
1537 status |= up->msr_saved_flags;
1538 up->msr_saved_flags = 0;
1539 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1540 up->port.state != NULL) {
1541 if (status & UART_MSR_TERI)
1542 up->port.icount.rng++;
1543 if (status & UART_MSR_DDSR)
1544 up->port.icount.dsr++;
1545 if (status & UART_MSR_DDCD)
1546 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1547 if (status & UART_MSR_DCTS)
1548 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1549
1550 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
1551 }
1552
1553 return status;
1554 }
1555
1556 /*
1557 * This handles the interrupt from one port.
1558 */
1559 static void serial8250_handle_port(struct uart_8250_port *up)
1560 {
1561 unsigned int status;
1562 unsigned long flags;
1563
1564 spin_lock_irqsave(&up->port.lock, flags);
1565
1566 status = serial_inp(up, UART_LSR);
1567
1568 DEBUG_INTR("status = %x...", status);
1569
1570 if (status & (UART_LSR_DR | UART_LSR_BI))
1571 receive_chars(up, &status);
1572 check_modem_status(up);
1573 if (status & UART_LSR_THRE)
1574 transmit_chars(up);
1575
1576 spin_unlock_irqrestore(&up->port.lock, flags);
1577 }
1578
1579 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1580 {
1581 struct uart_8250_port *up =
1582 container_of(port, struct uart_8250_port, port);
1583
1584 if (!(iir & UART_IIR_NO_INT)) {
1585 serial8250_handle_port(up);
1586 return 1;
1587 }
1588
1589 return 0;
1590 }
1591 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1592
1593 static int serial8250_default_handle_irq(struct uart_port *port)
1594 {
1595 struct uart_8250_port *up =
1596 container_of(port, struct uart_8250_port, port);
1597 unsigned int iir = serial_in(up, UART_IIR);
1598
1599 return serial8250_handle_irq(port, iir);
1600 }
1601
1602 /*
1603 * This is the serial driver's interrupt routine.
1604 *
1605 * Arjan thinks the old way was overly complex, so it got simplified.
1606 * Alan disagrees, saying that need the complexity to handle the weird
1607 * nature of ISA shared interrupts. (This is a special exception.)
1608 *
1609 * In order to handle ISA shared interrupts properly, we need to check
1610 * that all ports have been serviced, and therefore the ISA interrupt
1611 * line has been de-asserted.
1612 *
1613 * This means we need to loop through all ports. checking that they
1614 * don't have an interrupt pending.
1615 */
1616 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1617 {
1618 struct irq_info *i = dev_id;
1619 struct list_head *l, *end = NULL;
1620 int pass_counter = 0, handled = 0;
1621
1622 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1623
1624 spin_lock(&i->lock);
1625
1626 l = i->head;
1627 do {
1628 struct uart_8250_port *up;
1629 struct uart_port *port;
1630
1631 up = list_entry(l, struct uart_8250_port, list);
1632 port = &up->port;
1633
1634 if (port->handle_irq(port)) {
1635 handled = 1;
1636 end = NULL;
1637 } else if (end == NULL)
1638 end = l;
1639
1640 l = l->next;
1641
1642 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1643 /* If we hit this, we're dead. */
1644 printk_ratelimited(KERN_ERR
1645 "serial8250: too much work for irq%d\n", irq);
1646 break;
1647 }
1648 } while (l != end);
1649
1650 spin_unlock(&i->lock);
1651
1652 DEBUG_INTR("end.\n");
1653
1654 return IRQ_RETVAL(handled);
1655 }
1656
1657 /*
1658 * To support ISA shared interrupts, we need to have one interrupt
1659 * handler that ensures that the IRQ line has been deasserted
1660 * before returning. Failing to do this will result in the IRQ
1661 * line being stuck active, and, since ISA irqs are edge triggered,
1662 * no more IRQs will be seen.
1663 */
1664 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1665 {
1666 spin_lock_irq(&i->lock);
1667
1668 if (!list_empty(i->head)) {
1669 if (i->head == &up->list)
1670 i->head = i->head->next;
1671 list_del(&up->list);
1672 } else {
1673 BUG_ON(i->head != &up->list);
1674 i->head = NULL;
1675 }
1676 spin_unlock_irq(&i->lock);
1677 /* List empty so throw away the hash node */
1678 if (i->head == NULL) {
1679 hlist_del(&i->node);
1680 kfree(i);
1681 }
1682 }
1683
1684 static int serial_link_irq_chain(struct uart_8250_port *up)
1685 {
1686 struct hlist_head *h;
1687 struct hlist_node *n;
1688 struct irq_info *i;
1689 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1690
1691 mutex_lock(&hash_mutex);
1692
1693 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1694
1695 hlist_for_each(n, h) {
1696 i = hlist_entry(n, struct irq_info, node);
1697 if (i->irq == up->port.irq)
1698 break;
1699 }
1700
1701 if (n == NULL) {
1702 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1703 if (i == NULL) {
1704 mutex_unlock(&hash_mutex);
1705 return -ENOMEM;
1706 }
1707 spin_lock_init(&i->lock);
1708 i->irq = up->port.irq;
1709 hlist_add_head(&i->node, h);
1710 }
1711 mutex_unlock(&hash_mutex);
1712
1713 spin_lock_irq(&i->lock);
1714
1715 if (i->head) {
1716 list_add(&up->list, i->head);
1717 spin_unlock_irq(&i->lock);
1718
1719 ret = 0;
1720 } else {
1721 INIT_LIST_HEAD(&up->list);
1722 i->head = &up->list;
1723 spin_unlock_irq(&i->lock);
1724 irq_flags |= up->port.irqflags;
1725 ret = request_irq(up->port.irq, serial8250_interrupt,
1726 irq_flags, "serial", i);
1727 if (ret < 0)
1728 serial_do_unlink(i, up);
1729 }
1730
1731 return ret;
1732 }
1733
1734 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1735 {
1736 struct irq_info *i;
1737 struct hlist_node *n;
1738 struct hlist_head *h;
1739
1740 mutex_lock(&hash_mutex);
1741
1742 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1743
1744 hlist_for_each(n, h) {
1745 i = hlist_entry(n, struct irq_info, node);
1746 if (i->irq == up->port.irq)
1747 break;
1748 }
1749
1750 BUG_ON(n == NULL);
1751 BUG_ON(i->head == NULL);
1752
1753 if (list_empty(i->head))
1754 free_irq(up->port.irq, i);
1755
1756 serial_do_unlink(i, up);
1757 mutex_unlock(&hash_mutex);
1758 }
1759
1760 /*
1761 * This function is used to handle ports that do not have an
1762 * interrupt. This doesn't work very well for 16450's, but gives
1763 * barely passable results for a 16550A. (Although at the expense
1764 * of much CPU overhead).
1765 */
1766 static void serial8250_timeout(unsigned long data)
1767 {
1768 struct uart_8250_port *up = (struct uart_8250_port *)data;
1769 unsigned int iir;
1770
1771 iir = serial_in(up, UART_IIR);
1772 if (!(iir & UART_IIR_NO_INT))
1773 serial8250_handle_port(up);
1774 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
1775 }
1776
1777 static void serial8250_backup_timeout(unsigned long data)
1778 {
1779 struct uart_8250_port *up = (struct uart_8250_port *)data;
1780 unsigned int iir, ier = 0, lsr;
1781 unsigned long flags;
1782
1783 spin_lock_irqsave(&up->port.lock, flags);
1784
1785 /*
1786 * Must disable interrupts or else we risk racing with the interrupt
1787 * based handler.
1788 */
1789 if (is_real_interrupt(up->port.irq)) {
1790 ier = serial_in(up, UART_IER);
1791 serial_out(up, UART_IER, 0);
1792 }
1793
1794 iir = serial_in(up, UART_IIR);
1795
1796 /*
1797 * This should be a safe test for anyone who doesn't trust the
1798 * IIR bits on their UART, but it's specifically designed for
1799 * the "Diva" UART used on the management processor on many HP
1800 * ia64 and parisc boxes.
1801 */
1802 lsr = serial_in(up, UART_LSR);
1803 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1804 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1805 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1806 (lsr & UART_LSR_THRE)) {
1807 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1808 iir |= UART_IIR_THRI;
1809 }
1810
1811 if (!(iir & UART_IIR_NO_INT))
1812 transmit_chars(up);
1813
1814 if (is_real_interrupt(up->port.irq))
1815 serial_out(up, UART_IER, ier);
1816
1817 spin_unlock_irqrestore(&up->port.lock, flags);
1818
1819 /* Standard timer interval plus 0.2s to keep the port running */
1820 mod_timer(&up->timer,
1821 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1822 }
1823
1824 static unsigned int serial8250_tx_empty(struct uart_port *port)
1825 {
1826 struct uart_8250_port *up =
1827 container_of(port, struct uart_8250_port, port);
1828 unsigned long flags;
1829 unsigned int lsr;
1830
1831 spin_lock_irqsave(&up->port.lock, flags);
1832 lsr = serial_in(up, UART_LSR);
1833 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1834 spin_unlock_irqrestore(&up->port.lock, flags);
1835
1836 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1837 }
1838
1839 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1840 {
1841 struct uart_8250_port *up =
1842 container_of(port, struct uart_8250_port, port);
1843 unsigned int status;
1844 unsigned int ret;
1845
1846 status = check_modem_status(up);
1847
1848 ret = 0;
1849 if (status & UART_MSR_DCD)
1850 ret |= TIOCM_CAR;
1851 if (status & UART_MSR_RI)
1852 ret |= TIOCM_RNG;
1853 if (status & UART_MSR_DSR)
1854 ret |= TIOCM_DSR;
1855 if (status & UART_MSR_CTS)
1856 ret |= TIOCM_CTS;
1857 return ret;
1858 }
1859
1860 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1861 {
1862 struct uart_8250_port *up =
1863 container_of(port, struct uart_8250_port, port);
1864 unsigned char mcr = 0;
1865
1866 if (mctrl & TIOCM_RTS)
1867 mcr |= UART_MCR_RTS;
1868 if (mctrl & TIOCM_DTR)
1869 mcr |= UART_MCR_DTR;
1870 if (mctrl & TIOCM_OUT1)
1871 mcr |= UART_MCR_OUT1;
1872 if (mctrl & TIOCM_OUT2)
1873 mcr |= UART_MCR_OUT2;
1874 if (mctrl & TIOCM_LOOP)
1875 mcr |= UART_MCR_LOOP;
1876
1877 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1878
1879 serial_out(up, UART_MCR, mcr);
1880 }
1881
1882 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1883 {
1884 struct uart_8250_port *up =
1885 container_of(port, struct uart_8250_port, port);
1886 unsigned long flags;
1887
1888 spin_lock_irqsave(&up->port.lock, flags);
1889 if (break_state == -1)
1890 up->lcr |= UART_LCR_SBC;
1891 else
1892 up->lcr &= ~UART_LCR_SBC;
1893 serial_out(up, UART_LCR, up->lcr);
1894 spin_unlock_irqrestore(&up->port.lock, flags);
1895 }
1896
1897 /*
1898 * Wait for transmitter & holding register to empty
1899 */
1900 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1901 {
1902 unsigned int status, tmout = 10000;
1903
1904 /* Wait up to 10ms for the character(s) to be sent. */
1905 for (;;) {
1906 status = serial_in(up, UART_LSR);
1907
1908 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1909
1910 if ((status & bits) == bits)
1911 break;
1912 if (--tmout == 0)
1913 break;
1914 udelay(1);
1915 }
1916
1917 /* Wait up to 1s for flow control if necessary */
1918 if (up->port.flags & UPF_CONS_FLOW) {
1919 unsigned int tmout;
1920 for (tmout = 1000000; tmout; tmout--) {
1921 unsigned int msr = serial_in(up, UART_MSR);
1922 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1923 if (msr & UART_MSR_CTS)
1924 break;
1925 udelay(1);
1926 touch_nmi_watchdog();
1927 }
1928 }
1929 }
1930
1931 #ifdef CONFIG_CONSOLE_POLL
1932 /*
1933 * Console polling routines for writing and reading from the uart while
1934 * in an interrupt or debug context.
1935 */
1936
1937 static int serial8250_get_poll_char(struct uart_port *port)
1938 {
1939 struct uart_8250_port *up =
1940 container_of(port, struct uart_8250_port, port);
1941 unsigned char lsr = serial_inp(up, UART_LSR);
1942
1943 if (!(lsr & UART_LSR_DR))
1944 return NO_POLL_CHAR;
1945
1946 return serial_inp(up, UART_RX);
1947 }
1948
1949
1950 static void serial8250_put_poll_char(struct uart_port *port,
1951 unsigned char c)
1952 {
1953 unsigned int ier;
1954 struct uart_8250_port *up =
1955 container_of(port, struct uart_8250_port, port);
1956
1957 /*
1958 * First save the IER then disable the interrupts
1959 */
1960 ier = serial_in(up, UART_IER);
1961 if (up->capabilities & UART_CAP_UUE)
1962 serial_out(up, UART_IER, UART_IER_UUE);
1963 else
1964 serial_out(up, UART_IER, 0);
1965
1966 wait_for_xmitr(up, BOTH_EMPTY);
1967 /*
1968 * Send the character out.
1969 * If a LF, also do CR...
1970 */
1971 serial_out(up, UART_TX, c);
1972 if (c == 10) {
1973 wait_for_xmitr(up, BOTH_EMPTY);
1974 serial_out(up, UART_TX, 13);
1975 }
1976
1977 /*
1978 * Finally, wait for transmitter to become empty
1979 * and restore the IER
1980 */
1981 wait_for_xmitr(up, BOTH_EMPTY);
1982 serial_out(up, UART_IER, ier);
1983 }
1984
1985 #endif /* CONFIG_CONSOLE_POLL */
1986
1987 static int serial8250_startup(struct uart_port *port)
1988 {
1989 struct uart_8250_port *up =
1990 container_of(port, struct uart_8250_port, port);
1991 unsigned long flags;
1992 unsigned char lsr, iir;
1993 int retval;
1994
1995 up->port.fifosize = uart_config[up->port.type].fifo_size;
1996 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1997 up->capabilities = uart_config[up->port.type].flags;
1998 up->mcr = 0;
1999
2000 if (up->port.iotype != up->cur_iotype)
2001 set_io_from_upio(port);
2002
2003 if (up->port.type == PORT_16C950) {
2004 /* Wake up and initialize UART */
2005 up->acr = 0;
2006 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2007 serial_outp(up, UART_EFR, UART_EFR_ECB);
2008 serial_outp(up, UART_IER, 0);
2009 serial_outp(up, UART_LCR, 0);
2010 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2011 serial_outp(up, UART_LCR, 0xBF);
2012 serial_outp(up, UART_EFR, UART_EFR_ECB);
2013 serial_outp(up, UART_LCR, 0);
2014 }
2015
2016 #ifdef CONFIG_SERIAL_8250_RSA
2017 /*
2018 * If this is an RSA port, see if we can kick it up to the
2019 * higher speed clock.
2020 */
2021 enable_rsa(up);
2022 #endif
2023
2024 /*
2025 * Clear the FIFO buffers and disable them.
2026 * (they will be reenabled in set_termios())
2027 */
2028 serial8250_clear_fifos(up);
2029
2030 /*
2031 * Clear the interrupt registers.
2032 */
2033 (void) serial_inp(up, UART_LSR);
2034 (void) serial_inp(up, UART_RX);
2035 (void) serial_inp(up, UART_IIR);
2036 (void) serial_inp(up, UART_MSR);
2037
2038 /*
2039 * At this point, there's no way the LSR could still be 0xff;
2040 * if it is, then bail out, because there's likely no UART
2041 * here.
2042 */
2043 if (!(up->port.flags & UPF_BUGGY_UART) &&
2044 (serial_inp(up, UART_LSR) == 0xff)) {
2045 printk(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2046 serial_index(&up->port));
2047 return -ENODEV;
2048 }
2049
2050 /*
2051 * For a XR16C850, we need to set the trigger levels
2052 */
2053 if (up->port.type == PORT_16850) {
2054 unsigned char fctr;
2055
2056 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2057
2058 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2059 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2060 serial_outp(up, UART_TRG, UART_TRG_96);
2061 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2062 serial_outp(up, UART_TRG, UART_TRG_96);
2063
2064 serial_outp(up, UART_LCR, 0);
2065 }
2066
2067 if (is_real_interrupt(up->port.irq)) {
2068 unsigned char iir1;
2069 /*
2070 * Test for UARTs that do not reassert THRE when the
2071 * transmitter is idle and the interrupt has already
2072 * been cleared. Real 16550s should always reassert
2073 * this interrupt whenever the transmitter is idle and
2074 * the interrupt is enabled. Delays are necessary to
2075 * allow register changes to become visible.
2076 */
2077 spin_lock_irqsave(&up->port.lock, flags);
2078 if (up->port.irqflags & IRQF_SHARED)
2079 disable_irq_nosync(up->port.irq);
2080
2081 wait_for_xmitr(up, UART_LSR_THRE);
2082 serial_out_sync(up, UART_IER, UART_IER_THRI);
2083 udelay(1); /* allow THRE to set */
2084 iir1 = serial_in(up, UART_IIR);
2085 serial_out(up, UART_IER, 0);
2086 serial_out_sync(up, UART_IER, UART_IER_THRI);
2087 udelay(1); /* allow a working UART time to re-assert THRE */
2088 iir = serial_in(up, UART_IIR);
2089 serial_out(up, UART_IER, 0);
2090
2091 if (up->port.irqflags & IRQF_SHARED)
2092 enable_irq(up->port.irq);
2093 spin_unlock_irqrestore(&up->port.lock, flags);
2094
2095 /*
2096 * If the interrupt is not reasserted, setup a timer to
2097 * kick the UART on a regular basis.
2098 */
2099 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
2100 up->bugs |= UART_BUG_THRE;
2101 pr_debug("ttyS%d - using backup timer\n",
2102 serial_index(port));
2103 }
2104 }
2105
2106 /*
2107 * The above check will only give an accurate result the first time
2108 * the port is opened so this value needs to be preserved.
2109 */
2110 if (up->bugs & UART_BUG_THRE) {
2111 up->timer.function = serial8250_backup_timeout;
2112 up->timer.data = (unsigned long)up;
2113 mod_timer(&up->timer, jiffies +
2114 uart_poll_timeout(port) + HZ / 5);
2115 }
2116
2117 /*
2118 * If the "interrupt" for this port doesn't correspond with any
2119 * hardware interrupt, we use a timer-based system. The original
2120 * driver used to do this with IRQ0.
2121 */
2122 if (!is_real_interrupt(up->port.irq)) {
2123 up->timer.data = (unsigned long)up;
2124 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
2125 } else {
2126 retval = serial_link_irq_chain(up);
2127 if (retval)
2128 return retval;
2129 }
2130
2131 /*
2132 * Now, initialize the UART
2133 */
2134 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2135
2136 spin_lock_irqsave(&up->port.lock, flags);
2137 if (up->port.flags & UPF_FOURPORT) {
2138 if (!is_real_interrupt(up->port.irq))
2139 up->port.mctrl |= TIOCM_OUT1;
2140 } else
2141 /*
2142 * Most PC uarts need OUT2 raised to enable interrupts.
2143 */
2144 if (is_real_interrupt(up->port.irq))
2145 up->port.mctrl |= TIOCM_OUT2;
2146
2147 serial8250_set_mctrl(&up->port, up->port.mctrl);
2148
2149 /* Serial over Lan (SoL) hack:
2150 Intel 8257x Gigabit ethernet chips have a
2151 16550 emulation, to be used for Serial Over Lan.
2152 Those chips take a longer time than a normal
2153 serial device to signalize that a transmission
2154 data was queued. Due to that, the above test generally
2155 fails. One solution would be to delay the reading of
2156 iir. However, this is not reliable, since the timeout
2157 is variable. So, let's just don't test if we receive
2158 TX irq. This way, we'll never enable UART_BUG_TXEN.
2159 */
2160 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2161 goto dont_test_tx_en;
2162
2163 /*
2164 * Do a quick test to see if we receive an
2165 * interrupt when we enable the TX irq.
2166 */
2167 serial_outp(up, UART_IER, UART_IER_THRI);
2168 lsr = serial_in(up, UART_LSR);
2169 iir = serial_in(up, UART_IIR);
2170 serial_outp(up, UART_IER, 0);
2171
2172 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2173 if (!(up->bugs & UART_BUG_TXEN)) {
2174 up->bugs |= UART_BUG_TXEN;
2175 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2176 serial_index(port));
2177 }
2178 } else {
2179 up->bugs &= ~UART_BUG_TXEN;
2180 }
2181
2182 dont_test_tx_en:
2183 spin_unlock_irqrestore(&up->port.lock, flags);
2184
2185 /*
2186 * Clear the interrupt registers again for luck, and clear the
2187 * saved flags to avoid getting false values from polling
2188 * routines or the previous session.
2189 */
2190 serial_inp(up, UART_LSR);
2191 serial_inp(up, UART_RX);
2192 serial_inp(up, UART_IIR);
2193 serial_inp(up, UART_MSR);
2194 up->lsr_saved_flags = 0;
2195 up->msr_saved_flags = 0;
2196
2197 /*
2198 * Finally, enable interrupts. Note: Modem status interrupts
2199 * are set via set_termios(), which will be occurring imminently
2200 * anyway, so we don't enable them here.
2201 */
2202 up->ier = UART_IER_RLSI | UART_IER_RDI;
2203 serial_outp(up, UART_IER, up->ier);
2204
2205 if (up->port.flags & UPF_FOURPORT) {
2206 unsigned int icp;
2207 /*
2208 * Enable interrupts on the AST Fourport board
2209 */
2210 icp = (up->port.iobase & 0xfe0) | 0x01f;
2211 outb_p(0x80, icp);
2212 (void) inb_p(icp);
2213 }
2214
2215 return 0;
2216 }
2217
2218 static void serial8250_shutdown(struct uart_port *port)
2219 {
2220 struct uart_8250_port *up =
2221 container_of(port, struct uart_8250_port, port);
2222 unsigned long flags;
2223
2224 /*
2225 * Disable interrupts from this port
2226 */
2227 up->ier = 0;
2228 serial_outp(up, UART_IER, 0);
2229
2230 spin_lock_irqsave(&up->port.lock, flags);
2231 if (up->port.flags & UPF_FOURPORT) {
2232 /* reset interrupts on the AST Fourport board */
2233 inb((up->port.iobase & 0xfe0) | 0x1f);
2234 up->port.mctrl |= TIOCM_OUT1;
2235 } else
2236 up->port.mctrl &= ~TIOCM_OUT2;
2237
2238 serial8250_set_mctrl(&up->port, up->port.mctrl);
2239 spin_unlock_irqrestore(&up->port.lock, flags);
2240
2241 /*
2242 * Disable break condition and FIFOs
2243 */
2244 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2245 serial8250_clear_fifos(up);
2246
2247 #ifdef CONFIG_SERIAL_8250_RSA
2248 /*
2249 * Reset the RSA board back to 115kbps compat mode.
2250 */
2251 disable_rsa(up);
2252 #endif
2253
2254 /*
2255 * Read data port to reset things, and then unlink from
2256 * the IRQ chain.
2257 */
2258 (void) serial_in(up, UART_RX);
2259
2260 del_timer_sync(&up->timer);
2261 up->timer.function = serial8250_timeout;
2262 if (is_real_interrupt(up->port.irq))
2263 serial_unlink_irq_chain(up);
2264 }
2265
2266 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2267 {
2268 unsigned int quot;
2269
2270 /*
2271 * Handle magic divisors for baud rates above baud_base on
2272 * SMSC SuperIO chips.
2273 */
2274 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2275 baud == (port->uartclk/4))
2276 quot = 0x8001;
2277 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2278 baud == (port->uartclk/8))
2279 quot = 0x8002;
2280 else
2281 quot = uart_get_divisor(port, baud);
2282
2283 return quot;
2284 }
2285
2286 void
2287 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2288 struct ktermios *old)
2289 {
2290 struct uart_8250_port *up =
2291 container_of(port, struct uart_8250_port, port);
2292 unsigned char cval, fcr = 0;
2293 unsigned long flags;
2294 unsigned int baud, quot;
2295
2296 switch (termios->c_cflag & CSIZE) {
2297 case CS5:
2298 cval = UART_LCR_WLEN5;
2299 break;
2300 case CS6:
2301 cval = UART_LCR_WLEN6;
2302 break;
2303 case CS7:
2304 cval = UART_LCR_WLEN7;
2305 break;
2306 default:
2307 case CS8:
2308 cval = UART_LCR_WLEN8;
2309 break;
2310 }
2311
2312 if (termios->c_cflag & CSTOPB)
2313 cval |= UART_LCR_STOP;
2314 if (termios->c_cflag & PARENB)
2315 cval |= UART_LCR_PARITY;
2316 if (!(termios->c_cflag & PARODD))
2317 cval |= UART_LCR_EPAR;
2318 #ifdef CMSPAR
2319 if (termios->c_cflag & CMSPAR)
2320 cval |= UART_LCR_SPAR;
2321 #endif
2322
2323 /*
2324 * Ask the core to calculate the divisor for us.
2325 */
2326 baud = uart_get_baud_rate(port, termios, old,
2327 port->uartclk / 16 / 0xffff,
2328 port->uartclk / 16);
2329 quot = serial8250_get_divisor(port, baud);
2330
2331 /*
2332 * Oxford Semi 952 rev B workaround
2333 */
2334 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2335 quot++;
2336
2337 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2338 if (baud < 2400)
2339 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2340 else
2341 fcr = uart_config[up->port.type].fcr;
2342 }
2343
2344 /*
2345 * MCR-based auto flow control. When AFE is enabled, RTS will be
2346 * deasserted when the receive FIFO contains more characters than
2347 * the trigger, or the MCR RTS bit is cleared. In the case where
2348 * the remote UART is not using CTS auto flow control, we must
2349 * have sufficient FIFO entries for the latency of the remote
2350 * UART to respond. IOW, at least 32 bytes of FIFO.
2351 */
2352 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2353 up->mcr &= ~UART_MCR_AFE;
2354 if (termios->c_cflag & CRTSCTS)
2355 up->mcr |= UART_MCR_AFE;
2356 }
2357
2358 /*
2359 * Ok, we're now changing the port state. Do it with
2360 * interrupts disabled.
2361 */
2362 spin_lock_irqsave(&up->port.lock, flags);
2363
2364 /*
2365 * Update the per-port timeout.
2366 */
2367 uart_update_timeout(port, termios->c_cflag, baud);
2368
2369 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2370 if (termios->c_iflag & INPCK)
2371 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2372 if (termios->c_iflag & (BRKINT | PARMRK))
2373 up->port.read_status_mask |= UART_LSR_BI;
2374
2375 /*
2376 * Characteres to ignore
2377 */
2378 up->port.ignore_status_mask = 0;
2379 if (termios->c_iflag & IGNPAR)
2380 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2381 if (termios->c_iflag & IGNBRK) {
2382 up->port.ignore_status_mask |= UART_LSR_BI;
2383 /*
2384 * If we're ignoring parity and break indicators,
2385 * ignore overruns too (for real raw support).
2386 */
2387 if (termios->c_iflag & IGNPAR)
2388 up->port.ignore_status_mask |= UART_LSR_OE;
2389 }
2390
2391 /*
2392 * ignore all characters if CREAD is not set
2393 */
2394 if ((termios->c_cflag & CREAD) == 0)
2395 up->port.ignore_status_mask |= UART_LSR_DR;
2396
2397 /*
2398 * CTS flow control flag and modem status interrupts
2399 */
2400 up->ier &= ~UART_IER_MSI;
2401 if (!(up->bugs & UART_BUG_NOMSR) &&
2402 UART_ENABLE_MS(&up->port, termios->c_cflag))
2403 up->ier |= UART_IER_MSI;
2404 if (up->capabilities & UART_CAP_UUE)
2405 up->ier |= UART_IER_UUE;
2406 if (up->capabilities & UART_CAP_RTOIE)
2407 up->ier |= UART_IER_RTOIE;
2408
2409 serial_out(up, UART_IER, up->ier);
2410
2411 if (up->capabilities & UART_CAP_EFR) {
2412 unsigned char efr = 0;
2413 /*
2414 * TI16C752/Startech hardware flow control. FIXME:
2415 * - TI16C752 requires control thresholds to be set.
2416 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2417 */
2418 if (termios->c_cflag & CRTSCTS)
2419 efr |= UART_EFR_CTS;
2420
2421 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2422 serial_outp(up, UART_EFR, efr);
2423 }
2424
2425 #ifdef CONFIG_ARCH_OMAP
2426 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2427 if (cpu_is_omap1510() && is_omap_port(up)) {
2428 if (baud == 115200) {
2429 quot = 1;
2430 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2431 } else
2432 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2433 }
2434 #endif
2435
2436 if (up->capabilities & UART_NATSEMI) {
2437 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2438 serial_outp(up, UART_LCR, 0xe0);
2439 } else {
2440 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2441 }
2442
2443 serial_dl_write(up, quot);
2444
2445 /*
2446 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2447 * is written without DLAB set, this mode will be disabled.
2448 */
2449 if (up->port.type == PORT_16750)
2450 serial_outp(up, UART_FCR, fcr);
2451
2452 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2453 up->lcr = cval; /* Save LCR */
2454 if (up->port.type != PORT_16750) {
2455 if (fcr & UART_FCR_ENABLE_FIFO) {
2456 /* emulated UARTs (Lucent Venus 167x) need two steps */
2457 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2458 }
2459 serial_outp(up, UART_FCR, fcr); /* set fcr */
2460 }
2461 serial8250_set_mctrl(&up->port, up->port.mctrl);
2462 spin_unlock_irqrestore(&up->port.lock, flags);
2463 /* Don't rewrite B0 */
2464 if (tty_termios_baud_rate(termios))
2465 tty_termios_encode_baud_rate(termios, baud, baud);
2466 }
2467 EXPORT_SYMBOL(serial8250_do_set_termios);
2468
2469 static void
2470 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2471 struct ktermios *old)
2472 {
2473 if (port->set_termios)
2474 port->set_termios(port, termios, old);
2475 else
2476 serial8250_do_set_termios(port, termios, old);
2477 }
2478
2479 static void
2480 serial8250_set_ldisc(struct uart_port *port, int new)
2481 {
2482 if (new == N_PPS) {
2483 port->flags |= UPF_HARDPPS_CD;
2484 serial8250_enable_ms(port);
2485 } else
2486 port->flags &= ~UPF_HARDPPS_CD;
2487 }
2488
2489
2490 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2491 unsigned int oldstate)
2492 {
2493 struct uart_8250_port *p =
2494 container_of(port, struct uart_8250_port, port);
2495
2496 serial8250_set_sleep(p, state != 0);
2497 }
2498 EXPORT_SYMBOL(serial8250_do_pm);
2499
2500 static void
2501 serial8250_pm(struct uart_port *port, unsigned int state,
2502 unsigned int oldstate)
2503 {
2504 if (port->pm)
2505 port->pm(port, state, oldstate);
2506 else
2507 serial8250_do_pm(port, state, oldstate);
2508 }
2509
2510 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2511 {
2512 if (pt->port.iotype == UPIO_AU)
2513 return 0x1000;
2514 #ifdef CONFIG_ARCH_OMAP
2515 if (is_omap_port(pt))
2516 return 0x16 << pt->port.regshift;
2517 #endif
2518 return 8 << pt->port.regshift;
2519 }
2520
2521 /*
2522 * Resource handling.
2523 */
2524 static int serial8250_request_std_resource(struct uart_8250_port *up)
2525 {
2526 unsigned int size = serial8250_port_size(up);
2527 int ret = 0;
2528
2529 switch (up->port.iotype) {
2530 case UPIO_AU:
2531 case UPIO_TSI:
2532 case UPIO_MEM32:
2533 case UPIO_MEM:
2534 if (!up->port.mapbase)
2535 break;
2536
2537 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2538 ret = -EBUSY;
2539 break;
2540 }
2541
2542 if (up->port.flags & UPF_IOREMAP) {
2543 up->port.membase = ioremap_nocache(up->port.mapbase,
2544 size);
2545 if (!up->port.membase) {
2546 release_mem_region(up->port.mapbase, size);
2547 ret = -ENOMEM;
2548 }
2549 }
2550 break;
2551
2552 case UPIO_HUB6:
2553 case UPIO_PORT:
2554 if (!request_region(up->port.iobase, size, "serial"))
2555 ret = -EBUSY;
2556 break;
2557 }
2558 return ret;
2559 }
2560
2561 static void serial8250_release_std_resource(struct uart_8250_port *up)
2562 {
2563 unsigned int size = serial8250_port_size(up);
2564
2565 switch (up->port.iotype) {
2566 case UPIO_AU:
2567 case UPIO_TSI:
2568 case UPIO_MEM32:
2569 case UPIO_MEM:
2570 if (!up->port.mapbase)
2571 break;
2572
2573 if (up->port.flags & UPF_IOREMAP) {
2574 iounmap(up->port.membase);
2575 up->port.membase = NULL;
2576 }
2577
2578 release_mem_region(up->port.mapbase, size);
2579 break;
2580
2581 case UPIO_HUB6:
2582 case UPIO_PORT:
2583 release_region(up->port.iobase, size);
2584 break;
2585 }
2586 }
2587
2588 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2589 {
2590 unsigned long start = UART_RSA_BASE << up->port.regshift;
2591 unsigned int size = 8 << up->port.regshift;
2592 int ret = -EINVAL;
2593
2594 switch (up->port.iotype) {
2595 case UPIO_HUB6:
2596 case UPIO_PORT:
2597 start += up->port.iobase;
2598 if (request_region(start, size, "serial-rsa"))
2599 ret = 0;
2600 else
2601 ret = -EBUSY;
2602 break;
2603 }
2604
2605 return ret;
2606 }
2607
2608 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2609 {
2610 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2611 unsigned int size = 8 << up->port.regshift;
2612
2613 switch (up->port.iotype) {
2614 case UPIO_HUB6:
2615 case UPIO_PORT:
2616 release_region(up->port.iobase + offset, size);
2617 break;
2618 }
2619 }
2620
2621 static void serial8250_release_port(struct uart_port *port)
2622 {
2623 struct uart_8250_port *up =
2624 container_of(port, struct uart_8250_port, port);
2625
2626 serial8250_release_std_resource(up);
2627 if (up->port.type == PORT_RSA)
2628 serial8250_release_rsa_resource(up);
2629 }
2630
2631 static int serial8250_request_port(struct uart_port *port)
2632 {
2633 struct uart_8250_port *up =
2634 container_of(port, struct uart_8250_port, port);
2635 int ret = 0;
2636
2637 ret = serial8250_request_std_resource(up);
2638 if (ret == 0 && up->port.type == PORT_RSA) {
2639 ret = serial8250_request_rsa_resource(up);
2640 if (ret < 0)
2641 serial8250_release_std_resource(up);
2642 }
2643
2644 return ret;
2645 }
2646
2647 static void serial8250_config_port(struct uart_port *port, int flags)
2648 {
2649 struct uart_8250_port *up =
2650 container_of(port, struct uart_8250_port, port);
2651 int probeflags = PROBE_ANY;
2652 int ret;
2653
2654 /*
2655 * Find the region that we can probe for. This in turn
2656 * tells us whether we can probe for the type of port.
2657 */
2658 ret = serial8250_request_std_resource(up);
2659 if (ret < 0)
2660 return;
2661
2662 ret = serial8250_request_rsa_resource(up);
2663 if (ret < 0)
2664 probeflags &= ~PROBE_RSA;
2665
2666 if (up->port.iotype != up->cur_iotype)
2667 set_io_from_upio(port);
2668
2669 if (flags & UART_CONFIG_TYPE)
2670 autoconfig(up, probeflags);
2671
2672 /* if access method is AU, it is a 16550 with a quirk */
2673 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
2674 up->bugs |= UART_BUG_NOMSR;
2675
2676 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2677 autoconfig_irq(up);
2678
2679 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2680 serial8250_release_rsa_resource(up);
2681 if (up->port.type == PORT_UNKNOWN)
2682 serial8250_release_std_resource(up);
2683 }
2684
2685 static int
2686 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2687 {
2688 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2689 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2690 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2691 ser->type == PORT_STARTECH)
2692 return -EINVAL;
2693 return 0;
2694 }
2695
2696 static const char *
2697 serial8250_type(struct uart_port *port)
2698 {
2699 int type = port->type;
2700
2701 if (type >= ARRAY_SIZE(uart_config))
2702 type = 0;
2703 return uart_config[type].name;
2704 }
2705
2706 static struct uart_ops serial8250_pops = {
2707 .tx_empty = serial8250_tx_empty,
2708 .set_mctrl = serial8250_set_mctrl,
2709 .get_mctrl = serial8250_get_mctrl,
2710 .stop_tx = serial8250_stop_tx,
2711 .start_tx = serial8250_start_tx,
2712 .stop_rx = serial8250_stop_rx,
2713 .enable_ms = serial8250_enable_ms,
2714 .break_ctl = serial8250_break_ctl,
2715 .startup = serial8250_startup,
2716 .shutdown = serial8250_shutdown,
2717 .set_termios = serial8250_set_termios,
2718 .set_ldisc = serial8250_set_ldisc,
2719 .pm = serial8250_pm,
2720 .type = serial8250_type,
2721 .release_port = serial8250_release_port,
2722 .request_port = serial8250_request_port,
2723 .config_port = serial8250_config_port,
2724 .verify_port = serial8250_verify_port,
2725 #ifdef CONFIG_CONSOLE_POLL
2726 .poll_get_char = serial8250_get_poll_char,
2727 .poll_put_char = serial8250_put_poll_char,
2728 #endif
2729 };
2730
2731 static struct uart_8250_port serial8250_ports[UART_NR];
2732
2733 static void (*serial8250_isa_config)(int port, struct uart_port *up,
2734 unsigned short *capabilities);
2735
2736 void serial8250_set_isa_configurator(
2737 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2738 {
2739 serial8250_isa_config = v;
2740 }
2741 EXPORT_SYMBOL(serial8250_set_isa_configurator);
2742
2743 static void __init serial8250_isa_init_ports(void)
2744 {
2745 struct uart_8250_port *up;
2746 static int first = 1;
2747 int i, irqflag = 0;
2748
2749 if (!first)
2750 return;
2751 first = 0;
2752
2753 for (i = 0; i < nr_uarts; i++) {
2754 struct uart_8250_port *up = &serial8250_ports[i];
2755
2756 up->port.line = i;
2757 spin_lock_init(&up->port.lock);
2758
2759 init_timer(&up->timer);
2760 up->timer.function = serial8250_timeout;
2761
2762 /*
2763 * ALPHA_KLUDGE_MCR needs to be killed.
2764 */
2765 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2766 up->mcr_force = ALPHA_KLUDGE_MCR;
2767
2768 up->port.ops = &serial8250_pops;
2769 }
2770
2771 if (share_irqs)
2772 irqflag = IRQF_SHARED;
2773
2774 for (i = 0, up = serial8250_ports;
2775 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2776 i++, up++) {
2777 up->port.iobase = old_serial_port[i].port;
2778 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2779 up->port.irqflags = old_serial_port[i].irqflags;
2780 up->port.uartclk = old_serial_port[i].baud_base * 16;
2781 up->port.flags = old_serial_port[i].flags;
2782 up->port.hub6 = old_serial_port[i].hub6;
2783 up->port.membase = old_serial_port[i].iomem_base;
2784 up->port.iotype = old_serial_port[i].io_type;
2785 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2786 set_io_from_upio(&up->port);
2787 up->port.irqflags |= irqflag;
2788 if (serial8250_isa_config != NULL)
2789 serial8250_isa_config(i, &up->port, &up->capabilities);
2790
2791 }
2792 }
2793
2794 static void
2795 serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2796 {
2797 up->port.type = type;
2798 up->port.fifosize = uart_config[type].fifo_size;
2799 up->capabilities = uart_config[type].flags;
2800 up->tx_loadsz = uart_config[type].tx_loadsz;
2801 }
2802
2803 static void __init
2804 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2805 {
2806 int i;
2807
2808 for (i = 0; i < nr_uarts; i++) {
2809 struct uart_8250_port *up = &serial8250_ports[i];
2810 up->cur_iotype = 0xFF;
2811 }
2812
2813 serial8250_isa_init_ports();
2814
2815 for (i = 0; i < nr_uarts; i++) {
2816 struct uart_8250_port *up = &serial8250_ports[i];
2817
2818 up->port.dev = dev;
2819
2820 if (up->port.flags & UPF_FIXED_TYPE)
2821 serial8250_init_fixed_type_port(up, up->port.type);
2822
2823 uart_add_one_port(drv, &up->port);
2824 }
2825 }
2826
2827 #ifdef CONFIG_SERIAL_8250_CONSOLE
2828
2829 static void serial8250_console_putchar(struct uart_port *port, int ch)
2830 {
2831 struct uart_8250_port *up =
2832 container_of(port, struct uart_8250_port, port);
2833
2834 wait_for_xmitr(up, UART_LSR_THRE);
2835 serial_out(up, UART_TX, ch);
2836 }
2837
2838 /*
2839 * Print a string to the serial port trying not to disturb
2840 * any possible real use of the port...
2841 *
2842 * The console_lock must be held when we get here.
2843 */
2844 static void
2845 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2846 {
2847 struct uart_8250_port *up = &serial8250_ports[co->index];
2848 unsigned long flags;
2849 unsigned int ier;
2850 int locked = 1;
2851
2852 touch_nmi_watchdog();
2853
2854 local_irq_save(flags);
2855 if (up->port.sysrq) {
2856 /* serial8250_handle_port() already took the lock */
2857 locked = 0;
2858 } else if (oops_in_progress) {
2859 locked = spin_trylock(&up->port.lock);
2860 } else
2861 spin_lock(&up->port.lock);
2862
2863 /*
2864 * First save the IER then disable the interrupts
2865 */
2866 ier = serial_in(up, UART_IER);
2867
2868 if (up->capabilities & UART_CAP_UUE)
2869 serial_out(up, UART_IER, UART_IER_UUE);
2870 else
2871 serial_out(up, UART_IER, 0);
2872
2873 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2874
2875 /*
2876 * Finally, wait for transmitter to become empty
2877 * and restore the IER
2878 */
2879 wait_for_xmitr(up, BOTH_EMPTY);
2880 serial_out(up, UART_IER, ier);
2881
2882 /*
2883 * The receive handling will happen properly because the
2884 * receive ready bit will still be set; it is not cleared
2885 * on read. However, modem control will not, we must
2886 * call it if we have saved something in the saved flags
2887 * while processing with interrupts off.
2888 */
2889 if (up->msr_saved_flags)
2890 check_modem_status(up);
2891
2892 if (locked)
2893 spin_unlock(&up->port.lock);
2894 local_irq_restore(flags);
2895 }
2896
2897 static int __init serial8250_console_setup(struct console *co, char *options)
2898 {
2899 struct uart_port *port;
2900 int baud = 9600;
2901 int bits = 8;
2902 int parity = 'n';
2903 int flow = 'n';
2904
2905 /*
2906 * Check whether an invalid uart number has been specified, and
2907 * if so, search for the first available port that does have
2908 * console support.
2909 */
2910 if (co->index >= nr_uarts)
2911 co->index = 0;
2912 port = &serial8250_ports[co->index].port;
2913 if (!port->iobase && !port->membase)
2914 return -ENODEV;
2915
2916 if (options)
2917 uart_parse_options(options, &baud, &parity, &bits, &flow);
2918
2919 return uart_set_options(port, co, baud, parity, bits, flow);
2920 }
2921
2922 static int serial8250_console_early_setup(void)
2923 {
2924 return serial8250_find_port_for_earlycon();
2925 }
2926
2927 static struct console serial8250_console = {
2928 .name = "ttyS",
2929 .write = serial8250_console_write,
2930 .device = uart_console_device,
2931 .setup = serial8250_console_setup,
2932 .early_setup = serial8250_console_early_setup,
2933 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2934 .index = -1,
2935 .data = &serial8250_reg,
2936 };
2937
2938 static int __init serial8250_console_init(void)
2939 {
2940 if (nr_uarts > UART_NR)
2941 nr_uarts = UART_NR;
2942
2943 serial8250_isa_init_ports();
2944 register_console(&serial8250_console);
2945 return 0;
2946 }
2947 console_initcall(serial8250_console_init);
2948
2949 int serial8250_find_port(struct uart_port *p)
2950 {
2951 int line;
2952 struct uart_port *port;
2953
2954 for (line = 0; line < nr_uarts; line++) {
2955 port = &serial8250_ports[line].port;
2956 if (uart_match_port(p, port))
2957 return line;
2958 }
2959 return -ENODEV;
2960 }
2961
2962 #define SERIAL8250_CONSOLE &serial8250_console
2963 #else
2964 #define SERIAL8250_CONSOLE NULL
2965 #endif
2966
2967 static struct uart_driver serial8250_reg = {
2968 .owner = THIS_MODULE,
2969 .driver_name = "serial",
2970 .dev_name = "ttyS",
2971 .major = TTY_MAJOR,
2972 .minor = 64,
2973 .cons = SERIAL8250_CONSOLE,
2974 };
2975
2976 /*
2977 * early_serial_setup - early registration for 8250 ports
2978 *
2979 * Setup an 8250 port structure prior to console initialisation. Use
2980 * after console initialisation will cause undefined behaviour.
2981 */
2982 int __init early_serial_setup(struct uart_port *port)
2983 {
2984 struct uart_port *p;
2985
2986 if (port->line >= ARRAY_SIZE(serial8250_ports))
2987 return -ENODEV;
2988
2989 serial8250_isa_init_ports();
2990 p = &serial8250_ports[port->line].port;
2991 p->iobase = port->iobase;
2992 p->membase = port->membase;
2993 p->irq = port->irq;
2994 p->irqflags = port->irqflags;
2995 p->uartclk = port->uartclk;
2996 p->fifosize = port->fifosize;
2997 p->regshift = port->regshift;
2998 p->iotype = port->iotype;
2999 p->flags = port->flags;
3000 p->mapbase = port->mapbase;
3001 p->private_data = port->private_data;
3002 p->type = port->type;
3003 p->line = port->line;
3004
3005 set_io_from_upio(p);
3006 if (port->serial_in)
3007 p->serial_in = port->serial_in;
3008 if (port->serial_out)
3009 p->serial_out = port->serial_out;
3010 if (port->handle_irq)
3011 p->handle_irq = port->handle_irq;
3012 else
3013 p->handle_irq = serial8250_default_handle_irq;
3014
3015 return 0;
3016 }
3017
3018 /**
3019 * serial8250_suspend_port - suspend one serial port
3020 * @line: serial line number
3021 *
3022 * Suspend one serial port.
3023 */
3024 void serial8250_suspend_port(int line)
3025 {
3026 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
3027 }
3028
3029 /**
3030 * serial8250_resume_port - resume one serial port
3031 * @line: serial line number
3032 *
3033 * Resume one serial port.
3034 */
3035 void serial8250_resume_port(int line)
3036 {
3037 struct uart_8250_port *up = &serial8250_ports[line];
3038
3039 if (up->capabilities & UART_NATSEMI) {
3040 /* Ensure it's still in high speed mode */
3041 serial_outp(up, UART_LCR, 0xE0);
3042
3043 ns16550a_goto_highspeed(up);
3044
3045 serial_outp(up, UART_LCR, 0);
3046 up->port.uartclk = 921600*16;
3047 }
3048 uart_resume_port(&serial8250_reg, &up->port);
3049 }
3050
3051 /*
3052 * Register a set of serial devices attached to a platform device. The
3053 * list is terminated with a zero flags entry, which means we expect
3054 * all entries to have at least UPF_BOOT_AUTOCONF set.
3055 */
3056 static int __devinit serial8250_probe(struct platform_device *dev)
3057 {
3058 struct plat_serial8250_port *p = dev->dev.platform_data;
3059 struct uart_port port;
3060 int ret, i, irqflag = 0;
3061
3062 memset(&port, 0, sizeof(struct uart_port));
3063
3064 if (share_irqs)
3065 irqflag = IRQF_SHARED;
3066
3067 for (i = 0; p && p->flags != 0; p++, i++) {
3068 port.iobase = p->iobase;
3069 port.membase = p->membase;
3070 port.irq = p->irq;
3071 port.irqflags = p->irqflags;
3072 port.uartclk = p->uartclk;
3073 port.regshift = p->regshift;
3074 port.iotype = p->iotype;
3075 port.flags = p->flags;
3076 port.mapbase = p->mapbase;
3077 port.hub6 = p->hub6;
3078 port.private_data = p->private_data;
3079 port.type = p->type;
3080 port.serial_in = p->serial_in;
3081 port.serial_out = p->serial_out;
3082 port.handle_irq = p->handle_irq;
3083 port.set_termios = p->set_termios;
3084 port.pm = p->pm;
3085 port.dev = &dev->dev;
3086 port.irqflags |= irqflag;
3087 ret = serial8250_register_port(&port);
3088 if (ret < 0) {
3089 dev_err(&dev->dev, "unable to register port at index %d "
3090 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3091 p->iobase, (unsigned long long)p->mapbase,
3092 p->irq, ret);
3093 }
3094 }
3095 return 0;
3096 }
3097
3098 /*
3099 * Remove serial ports registered against a platform device.
3100 */
3101 static int __devexit serial8250_remove(struct platform_device *dev)
3102 {
3103 int i;
3104
3105 for (i = 0; i < nr_uarts; i++) {
3106 struct uart_8250_port *up = &serial8250_ports[i];
3107
3108 if (up->port.dev == &dev->dev)
3109 serial8250_unregister_port(i);
3110 }
3111 return 0;
3112 }
3113
3114 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3115 {
3116 int i;
3117
3118 for (i = 0; i < UART_NR; i++) {
3119 struct uart_8250_port *up = &serial8250_ports[i];
3120
3121 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3122 uart_suspend_port(&serial8250_reg, &up->port);
3123 }
3124
3125 return 0;
3126 }
3127
3128 static int serial8250_resume(struct platform_device *dev)
3129 {
3130 int i;
3131
3132 for (i = 0; i < UART_NR; i++) {
3133 struct uart_8250_port *up = &serial8250_ports[i];
3134
3135 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3136 serial8250_resume_port(i);
3137 }
3138
3139 return 0;
3140 }
3141
3142 static struct platform_driver serial8250_isa_driver = {
3143 .probe = serial8250_probe,
3144 .remove = __devexit_p(serial8250_remove),
3145 .suspend = serial8250_suspend,
3146 .resume = serial8250_resume,
3147 .driver = {
3148 .name = "serial8250",
3149 .owner = THIS_MODULE,
3150 },
3151 };
3152
3153 /*
3154 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3155 * in the table in include/asm/serial.h
3156 */
3157 static struct platform_device *serial8250_isa_devs;
3158
3159 /*
3160 * serial8250_register_port and serial8250_unregister_port allows for
3161 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3162 * modems and PCI multiport cards.
3163 */
3164 static DEFINE_MUTEX(serial_mutex);
3165
3166 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3167 {
3168 int i;
3169
3170 /*
3171 * First, find a port entry which matches.
3172 */
3173 for (i = 0; i < nr_uarts; i++)
3174 if (uart_match_port(&serial8250_ports[i].port, port))
3175 return &serial8250_ports[i];
3176
3177 /*
3178 * We didn't find a matching entry, so look for the first
3179 * free entry. We look for one which hasn't been previously
3180 * used (indicated by zero iobase).
3181 */
3182 for (i = 0; i < nr_uarts; i++)
3183 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3184 serial8250_ports[i].port.iobase == 0)
3185 return &serial8250_ports[i];
3186
3187 /*
3188 * That also failed. Last resort is to find any entry which
3189 * doesn't have a real port associated with it.
3190 */
3191 for (i = 0; i < nr_uarts; i++)
3192 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3193 return &serial8250_ports[i];
3194
3195 return NULL;
3196 }
3197
3198 /**
3199 * serial8250_register_port - register a serial port
3200 * @port: serial port template
3201 *
3202 * Configure the serial port specified by the request. If the
3203 * port exists and is in use, it is hung up and unregistered
3204 * first.
3205 *
3206 * The port is then probed and if necessary the IRQ is autodetected
3207 * If this fails an error is returned.
3208 *
3209 * On success the port is ready to use and the line number is returned.
3210 */
3211 int serial8250_register_port(struct uart_port *port)
3212 {
3213 struct uart_8250_port *uart;
3214 int ret = -ENOSPC;
3215
3216 if (port->uartclk == 0)
3217 return -EINVAL;
3218
3219 mutex_lock(&serial_mutex);
3220
3221 uart = serial8250_find_match_or_unused(port);
3222 if (uart) {
3223 uart_remove_one_port(&serial8250_reg, &uart->port);
3224
3225 uart->port.iobase = port->iobase;
3226 uart->port.membase = port->membase;
3227 uart->port.irq = port->irq;
3228 uart->port.irqflags = port->irqflags;
3229 uart->port.uartclk = port->uartclk;
3230 uart->port.fifosize = port->fifosize;
3231 uart->port.regshift = port->regshift;
3232 uart->port.iotype = port->iotype;
3233 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3234 uart->port.mapbase = port->mapbase;
3235 uart->port.private_data = port->private_data;
3236 if (port->dev)
3237 uart->port.dev = port->dev;
3238
3239 if (port->flags & UPF_FIXED_TYPE)
3240 serial8250_init_fixed_type_port(uart, port->type);
3241
3242 set_io_from_upio(&uart->port);
3243 /* Possibly override default I/O functions. */
3244 if (port->serial_in)
3245 uart->port.serial_in = port->serial_in;
3246 if (port->serial_out)
3247 uart->port.serial_out = port->serial_out;
3248 if (port->handle_irq)
3249 uart->port.handle_irq = port->handle_irq;
3250 /* Possibly override set_termios call */
3251 if (port->set_termios)
3252 uart->port.set_termios = port->set_termios;
3253 if (port->pm)
3254 uart->port.pm = port->pm;
3255
3256 if (serial8250_isa_config != NULL)
3257 serial8250_isa_config(0, &uart->port,
3258 &uart->capabilities);
3259
3260 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3261 if (ret == 0)
3262 ret = uart->port.line;
3263 }
3264 mutex_unlock(&serial_mutex);
3265
3266 return ret;
3267 }
3268 EXPORT_SYMBOL(serial8250_register_port);
3269
3270 /**
3271 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3272 * @line: serial line number
3273 *
3274 * Remove one serial port. This may not be called from interrupt
3275 * context. We hand the port back to the our control.
3276 */
3277 void serial8250_unregister_port(int line)
3278 {
3279 struct uart_8250_port *uart = &serial8250_ports[line];
3280
3281 mutex_lock(&serial_mutex);
3282 uart_remove_one_port(&serial8250_reg, &uart->port);
3283 if (serial8250_isa_devs) {
3284 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3285 uart->port.type = PORT_UNKNOWN;
3286 uart->port.dev = &serial8250_isa_devs->dev;
3287 uart->capabilities = uart_config[uart->port.type].flags;
3288 uart_add_one_port(&serial8250_reg, &uart->port);
3289 } else {
3290 uart->port.dev = NULL;
3291 }
3292 mutex_unlock(&serial_mutex);
3293 }
3294 EXPORT_SYMBOL(serial8250_unregister_port);
3295
3296 static int __init serial8250_init(void)
3297 {
3298 int ret;
3299
3300 if (nr_uarts > UART_NR)
3301 nr_uarts = UART_NR;
3302
3303 printk(KERN_INFO "Serial: 8250/16550 driver, "
3304 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3305 share_irqs ? "en" : "dis");
3306
3307 #ifdef CONFIG_SPARC
3308 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3309 #else
3310 serial8250_reg.nr = UART_NR;
3311 ret = uart_register_driver(&serial8250_reg);
3312 #endif
3313 if (ret)
3314 goto out;
3315
3316 serial8250_isa_devs = platform_device_alloc("serial8250",
3317 PLAT8250_DEV_LEGACY);
3318 if (!serial8250_isa_devs) {
3319 ret = -ENOMEM;
3320 goto unreg_uart_drv;
3321 }
3322
3323 ret = platform_device_add(serial8250_isa_devs);
3324 if (ret)
3325 goto put_dev;
3326
3327 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3328
3329 ret = platform_driver_register(&serial8250_isa_driver);
3330 if (ret == 0)
3331 goto out;
3332
3333 platform_device_del(serial8250_isa_devs);
3334 put_dev:
3335 platform_device_put(serial8250_isa_devs);
3336 unreg_uart_drv:
3337 #ifdef CONFIG_SPARC
3338 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3339 #else
3340 uart_unregister_driver(&serial8250_reg);
3341 #endif
3342 out:
3343 return ret;
3344 }
3345
3346 static void __exit serial8250_exit(void)
3347 {
3348 struct platform_device *isa_dev = serial8250_isa_devs;
3349
3350 /*
3351 * This tells serial8250_unregister_port() not to re-register
3352 * the ports (thereby making serial8250_isa_driver permanently
3353 * in use.)
3354 */
3355 serial8250_isa_devs = NULL;
3356
3357 platform_driver_unregister(&serial8250_isa_driver);
3358 platform_device_unregister(isa_dev);
3359
3360 #ifdef CONFIG_SPARC
3361 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3362 #else
3363 uart_unregister_driver(&serial8250_reg);
3364 #endif
3365 }
3366
3367 module_init(serial8250_init);
3368 module_exit(serial8250_exit);
3369
3370 EXPORT_SYMBOL(serial8250_suspend_port);
3371 EXPORT_SYMBOL(serial8250_resume_port);
3372
3373 MODULE_LICENSE("GPL");
3374 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3375
3376 module_param(share_irqs, uint, 0644);
3377 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3378 " (unsafe)");
3379
3380 module_param(nr_uarts, uint, 0644);
3381 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3382
3383 module_param(skip_txen_test, uint, 0644);
3384 MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3385
3386 #ifdef CONFIG_SERIAL_8250_RSA
3387 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3388 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3389 #endif
3390 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
linux-next