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Add linux-next specific files for 20110831
[linux-2.6/next.git] / drivers / tty / serial / max3107.c
bloba50f40691f46617cb071ba138f193fb3afdb8fb8
1 /*
2 * max3107.c - spi uart protocol driver for Maxim 3107
3 * Based on max3100.c
4 * by Christian Pellegrin <chripell@evolware.org>
5 * and max3110.c
6 * by Feng Tang <feng.tang@intel.com>
7 *
8 * Copyright (C) Aavamobile 2009
9 *
10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
27 *
28 */
29
30 #include <linux/delay.h>
31 #include <linux/device.h>
32 #include <linux/serial_core.h>
33 #include <linux/serial.h>
34 #include <linux/gpio.h>
35 #include <linux/spi/spi.h>
36 #include <linux/freezer.h>
37 #include <linux/module.h>
38 #include "max3107.h"
39
40 static const struct baud_table brg26_ext[] = {
41 { 300, MAX3107_BRG26_B300 },
42 { 600, MAX3107_BRG26_B600 },
43 { 1200, MAX3107_BRG26_B1200 },
44 { 2400, MAX3107_BRG26_B2400 },
45 { 4800, MAX3107_BRG26_B4800 },
46 { 9600, MAX3107_BRG26_B9600 },
47 { 19200, MAX3107_BRG26_B19200 },
48 { 57600, MAX3107_BRG26_B57600 },
49 { 115200, MAX3107_BRG26_B115200 },
50 { 230400, MAX3107_BRG26_B230400 },
51 { 460800, MAX3107_BRG26_B460800 },
52 { 921600, MAX3107_BRG26_B921600 },
53 { 0, 0 }
54 };
55
56 static const struct baud_table brg13_int[] = {
57 { 300, MAX3107_BRG13_IB300 },
58 { 600, MAX3107_BRG13_IB600 },
59 { 1200, MAX3107_BRG13_IB1200 },
60 { 2400, MAX3107_BRG13_IB2400 },
61 { 4800, MAX3107_BRG13_IB4800 },
62 { 9600, MAX3107_BRG13_IB9600 },
63 { 19200, MAX3107_BRG13_IB19200 },
64 { 57600, MAX3107_BRG13_IB57600 },
65 { 115200, MAX3107_BRG13_IB115200 },
66 { 230400, MAX3107_BRG13_IB230400 },
67 { 460800, MAX3107_BRG13_IB460800 },
68 { 921600, MAX3107_BRG13_IB921600 },
69 { 0, 0 }
70 };
71
72 static u32 get_new_brg(int baud, struct max3107_port *s)
73 {
74 int i;
75 const struct baud_table *baud_tbl = s->baud_tbl;
76
77 for (i = 0; i < 13; i++) {
78 if (baud == baud_tbl[i].baud)
79 return baud_tbl[i].new_brg;
80 }
81
82 return 0;
83 }
84
85 /* Perform SPI transfer for write/read of device register(s) */
86 int max3107_rw(struct max3107_port *s, u8 *tx, u8 *rx, int len)
87 {
88 struct spi_message spi_msg;
89 struct spi_transfer spi_xfer;
90
91 /* Initialize SPI ,message */
92 spi_message_init(&spi_msg);
93
94 /* Initialize SPI transfer */
95 memset(&spi_xfer, 0, sizeof spi_xfer);
96 spi_xfer.len = len;
97 spi_xfer.tx_buf = tx;
98 spi_xfer.rx_buf = rx;
99 spi_xfer.speed_hz = MAX3107_SPI_SPEED;
100
101 /* Add SPI transfer to SPI message */
102 spi_message_add_tail(&spi_xfer, &spi_msg);
103
104 #ifdef DBG_TRACE_SPI_DATA
105 {
106 int i;
107 pr_info("tx len %d:\n", spi_xfer.len);
108 for (i = 0 ; i < spi_xfer.len && i < 32 ; i++)
109 pr_info(" %x", ((u8 *)spi_xfer.tx_buf)[i]);
110 pr_info("\n");
111 }
112 #endif
113
114 /* Perform synchronous SPI transfer */
115 if (spi_sync(s->spi, &spi_msg)) {
116 dev_err(&s->spi->dev, "spi_sync failure\n");
117 return -EIO;
118 }
119
120 #ifdef DBG_TRACE_SPI_DATA
121 if (spi_xfer.rx_buf) {
122 int i;
123 pr_info("rx len %d:\n", spi_xfer.len);
124 for (i = 0 ; i < spi_xfer.len && i < 32 ; i++)
125 pr_info(" %x", ((u8 *)spi_xfer.rx_buf)[i]);
126 pr_info("\n");
127 }
128 #endif
129 return 0;
130 }
131 EXPORT_SYMBOL_GPL(max3107_rw);
132
133 /* Puts received data to circular buffer */
134 static void put_data_to_circ_buf(struct max3107_port *s, unsigned char *data,
135 int len)
136 {
137 struct uart_port *port = &s->port;
138 struct tty_struct *tty;
139
140 if (!port->state)
141 return;
142
143 tty = port->state->port.tty;
144 if (!tty)
145 return;
146
147 /* Insert received data */
148 tty_insert_flip_string(tty, data, len);
149 /* Update RX counter */
150 port->icount.rx += len;
151 }
152
153 /* Handle data receiving */
154 static void max3107_handlerx(struct max3107_port *s, u16 rxlvl)
155 {
156 int i;
157 int j;
158 int len; /* SPI transfer buffer length */
159 u16 *buf;
160 u8 *valid_str;
161
162 if (!s->rx_enabled)
163 /* RX is disabled */
164 return;
165
166 if (rxlvl == 0) {
167 /* RX fifo is empty */
168 return;
169 } else if (rxlvl >= MAX3107_RX_FIFO_SIZE) {
170 dev_warn(&s->spi->dev, "Possible RX FIFO overrun %d\n", rxlvl);
171 /* Ensure sanity of RX level */
172 rxlvl = MAX3107_RX_FIFO_SIZE;
173 }
174 if ((s->rxbuf == 0) || (s->rxstr == 0)) {
175 dev_warn(&s->spi->dev, "Rx buffer/str isn't ready\n");
176 return;
177 }
178 buf = s->rxbuf;
179 valid_str = s->rxstr;
180 while (rxlvl) {
181 pr_debug("rxlvl %d\n", rxlvl);
182 /* Clear buffer */
183 memset(buf, 0, sizeof(u16) * (MAX3107_RX_FIFO_SIZE + 2));
184 len = 0;
185 if (s->irqen_reg & MAX3107_IRQ_RXFIFO_BIT) {
186 /* First disable RX FIFO interrupt */
187 pr_debug("Disabling RX INT\n");
188 buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
189 s->irqen_reg &= ~MAX3107_IRQ_RXFIFO_BIT;
190 buf[0] |= s->irqen_reg;
191 len++;
192 }
193 /* Just increase the length by amount of words in FIFO since
194 * buffer was zeroed and SPI transfer of 0x0000 means reading
195 * from RX FIFO
196 */
197 len += rxlvl;
198 /* Append RX level query */
199 buf[len] = MAX3107_RXFIFOLVL_REG;
200 len++;
201
202 /* Perform the SPI transfer */
203 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, len * 2)) {
204 dev_err(&s->spi->dev, "SPI transfer for RX h failed\n");
205 return;
206 }
207
208 /* Skip RX FIFO interrupt disabling word if it was added */
209 j = ((len - 1) - rxlvl);
210 /* Read received words */
211 for (i = 0; i < rxlvl; i++, j++)
212 valid_str[i] = (u8)buf[j];
213 put_data_to_circ_buf(s, valid_str, rxlvl);
214 /* Get new RX level */
215 rxlvl = (buf[len - 1] & MAX3107_SPI_RX_DATA_MASK);
216 }
217
218 if (s->rx_enabled) {
219 /* RX still enabled, re-enable RX FIFO interrupt */
220 pr_debug("Enabling RX INT\n");
221 buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
222 s->irqen_reg |= MAX3107_IRQ_RXFIFO_BIT;
223 buf[0] |= s->irqen_reg;
224 if (max3107_rw(s, (u8 *)buf, NULL, 2))
225 dev_err(&s->spi->dev, "RX FIFO INT enabling failed\n");
226 }
227
228 /* Push the received data to receivers */
229 if (s->port.state->port.tty)
230 tty_flip_buffer_push(s->port.state->port.tty);
231 }
232
233
234 /* Handle data sending */
235 static void max3107_handletx(struct max3107_port *s)
236 {
237 struct circ_buf *xmit = &s->port.state->xmit;
238 int i;
239 unsigned long flags;
240 int len; /* SPI transfer buffer length */
241 u16 *buf;
242
243 if (!s->tx_fifo_empty)
244 /* Don't send more data before previous data is sent */
245 return;
246
247 if (uart_circ_empty(xmit) || uart_tx_stopped(&s->port))
248 /* No data to send or TX is stopped */
249 return;
250
251 if (!s->txbuf) {
252 dev_warn(&s->spi->dev, "Txbuf isn't ready\n");
253 return;
254 }
255 buf = s->txbuf;
256 /* Get length of data pending in circular buffer */
257 len = uart_circ_chars_pending(xmit);
258 if (len) {
259 /* Limit to size of TX FIFO */
260 if (len > MAX3107_TX_FIFO_SIZE)
261 len = MAX3107_TX_FIFO_SIZE;
262
263 pr_debug("txlen %d\n", len);
264
265 /* Update TX counter */
266 s->port.icount.tx += len;
267
268 /* TX FIFO will no longer be empty */
269 s->tx_fifo_empty = 0;
270
271 i = 0;
272 if (s->irqen_reg & MAX3107_IRQ_TXEMPTY_BIT) {
273 /* First disable TX empty interrupt */
274 pr_debug("Disabling TE INT\n");
275 buf[i] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
276 s->irqen_reg &= ~MAX3107_IRQ_TXEMPTY_BIT;
277 buf[i] |= s->irqen_reg;
278 i++;
279 len++;
280 }
281 /* Add data to send */
282 spin_lock_irqsave(&s->port.lock, flags);
283 for ( ; i < len ; i++) {
284 buf[i] = (MAX3107_WRITE_BIT | MAX3107_THR_REG);
285 buf[i] |= ((u16)xmit->buf[xmit->tail] &
286 MAX3107_SPI_TX_DATA_MASK);
287 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
288 }
289 spin_unlock_irqrestore(&s->port.lock, flags);
290 if (!(s->irqen_reg & MAX3107_IRQ_TXEMPTY_BIT)) {
291 /* Enable TX empty interrupt */
292 pr_debug("Enabling TE INT\n");
293 buf[i] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
294 s->irqen_reg |= MAX3107_IRQ_TXEMPTY_BIT;
295 buf[i] |= s->irqen_reg;
296 i++;
297 len++;
298 }
299 if (!s->tx_enabled) {
300 /* Enable TX */
301 pr_debug("Enable TX\n");
302 buf[i] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
303 spin_lock_irqsave(&s->data_lock, flags);
304 s->mode1_reg &= ~MAX3107_MODE1_TXDIS_BIT;
305 buf[i] |= s->mode1_reg;
306 spin_unlock_irqrestore(&s->data_lock, flags);
307 s->tx_enabled = 1;
308 i++;
309 len++;
310 }
311
312 /* Perform the SPI transfer */
313 if (max3107_rw(s, (u8 *)buf, NULL, len*2)) {
314 dev_err(&s->spi->dev,
315 "SPI transfer TX handling failed\n");
316 return;
317 }
318 }
319
320 /* Indicate wake up if circular buffer is getting low on data */
321 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
322 uart_write_wakeup(&s->port);
323
324 }
325
326 /* Handle interrupts
327 * Also reads and returns current RX FIFO level
328 */
329 static u16 handle_interrupt(struct max3107_port *s)
330 {
331 u16 buf[4]; /* Buffer for SPI transfers */
332 u8 irq_status;
333 u16 rx_level;
334 unsigned long flags;
335
336 /* Read IRQ status register */
337 buf[0] = MAX3107_IRQSTS_REG;
338 /* Read status IRQ status register */
339 buf[1] = MAX3107_STS_IRQSTS_REG;
340 /* Read LSR IRQ status register */
341 buf[2] = MAX3107_LSR_IRQSTS_REG;
342 /* Query RX level */
343 buf[3] = MAX3107_RXFIFOLVL_REG;
344
345 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 8)) {
346 dev_err(&s->spi->dev,
347 "SPI transfer for INTR handling failed\n");
348 return 0;
349 }
350
351 irq_status = (u8)buf[0];
352 pr_debug("IRQSTS %x\n", irq_status);
353 rx_level = (buf[3] & MAX3107_SPI_RX_DATA_MASK);
354
355 if (irq_status & MAX3107_IRQ_LSR_BIT) {
356 /* LSR interrupt */
357 if (buf[2] & MAX3107_LSR_RXTO_BIT)
358 /* RX timeout interrupt,
359 * handled by normal RX handling
360 */
361 pr_debug("RX TO INT\n");
362 }
363
364 if (irq_status & MAX3107_IRQ_TXEMPTY_BIT) {
365 /* Tx empty interrupt,
366 * disable TX and set tx_fifo_empty flag
367 */
368 pr_debug("TE INT, disabling TX\n");
369 buf[0] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
370 spin_lock_irqsave(&s->data_lock, flags);
371 s->mode1_reg |= MAX3107_MODE1_TXDIS_BIT;
372 buf[0] |= s->mode1_reg;
373 spin_unlock_irqrestore(&s->data_lock, flags);
374 if (max3107_rw(s, (u8 *)buf, NULL, 2))
375 dev_err(&s->spi->dev, "SPI transfer TX dis failed\n");
376 s->tx_enabled = 0;
377 s->tx_fifo_empty = 1;
378 }
379
380 if (irq_status & MAX3107_IRQ_RXFIFO_BIT)
381 /* RX FIFO interrupt,
382 * handled by normal RX handling
383 */
384 pr_debug("RFIFO INT\n");
385
386 /* Return RX level */
387 return rx_level;
388 }
389
390 /* Trigger work thread*/
391 static void max3107_dowork(struct max3107_port *s)
392 {
393 if (!work_pending(&s->work) && !freezing(current) && !s->suspended)
394 queue_work(s->workqueue, &s->work);
395 else
396 dev_warn(&s->spi->dev, "interrup isn't serviced normally!\n");
397 }
398
399 /* Work thread */
400 static void max3107_work(struct work_struct *w)
401 {
402 struct max3107_port *s = container_of(w, struct max3107_port, work);
403 u16 rxlvl = 0;
404 int len; /* SPI transfer buffer length */
405 u16 buf[5]; /* Buffer for SPI transfers */
406 unsigned long flags;
407
408 /* Start by reading current RX FIFO level */
409 buf[0] = MAX3107_RXFIFOLVL_REG;
410 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
411 dev_err(&s->spi->dev, "SPI transfer RX lev failed\n");
412 rxlvl = 0;
413 } else {
414 rxlvl = (buf[0] & MAX3107_SPI_RX_DATA_MASK);
415 }
416
417 do {
418 pr_debug("rxlvl %d\n", rxlvl);
419
420 /* Handle RX */
421 max3107_handlerx(s, rxlvl);
422 rxlvl = 0;
423
424 if (s->handle_irq) {
425 /* Handle pending interrupts
426 * We also get new RX FIFO level since new data may
427 * have been received while pushing received data to
428 * receivers
429 */
430 s->handle_irq = 0;
431 rxlvl = handle_interrupt(s);
432 }
433
434 /* Handle TX */
435 max3107_handletx(s);
436
437 /* Handle configuration changes */
438 len = 0;
439 spin_lock_irqsave(&s->data_lock, flags);
440 if (s->mode1_commit) {
441 pr_debug("mode1_commit\n");
442 buf[len] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
443 buf[len++] |= s->mode1_reg;
444 s->mode1_commit = 0;
445 }
446 if (s->lcr_commit) {
447 pr_debug("lcr_commit\n");
448 buf[len] = (MAX3107_WRITE_BIT | MAX3107_LCR_REG);
449 buf[len++] |= s->lcr_reg;
450 s->lcr_commit = 0;
451 }
452 if (s->brg_commit) {
453 pr_debug("brg_commit\n");
454 buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVMSB_REG);
455 buf[len++] |= ((s->brg_cfg >> 16) &
456 MAX3107_SPI_TX_DATA_MASK);
457 buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVLSB_REG);
458 buf[len++] |= ((s->brg_cfg >> 8) &
459 MAX3107_SPI_TX_DATA_MASK);
460 buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGCFG_REG);
461 buf[len++] |= ((s->brg_cfg) & 0xff);
462 s->brg_commit = 0;
463 }
464 spin_unlock_irqrestore(&s->data_lock, flags);
465
466 if (len > 0) {
467 if (max3107_rw(s, (u8 *)buf, NULL, len * 2))
468 dev_err(&s->spi->dev,
469 "SPI transfer config failed\n");
470 }
471
472 /* Reloop if interrupt handling indicated data in RX FIFO */
473 } while (rxlvl);
474
475 }
476
477 /* Set sleep mode */
478 static void max3107_set_sleep(struct max3107_port *s, int mode)
479 {
480 u16 buf[1]; /* Buffer for SPI transfer */
481 unsigned long flags;
482 pr_debug("enter, mode %d\n", mode);
483
484 buf[0] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
485 spin_lock_irqsave(&s->data_lock, flags);
486 switch (mode) {
487 case MAX3107_DISABLE_FORCED_SLEEP:
488 s->mode1_reg &= ~MAX3107_MODE1_FORCESLEEP_BIT;
489 break;
490 case MAX3107_ENABLE_FORCED_SLEEP:
491 s->mode1_reg |= MAX3107_MODE1_FORCESLEEP_BIT;
492 break;
493 case MAX3107_DISABLE_AUTOSLEEP:
494 s->mode1_reg &= ~MAX3107_MODE1_AUTOSLEEP_BIT;
495 break;
496 case MAX3107_ENABLE_AUTOSLEEP:
497 s->mode1_reg |= MAX3107_MODE1_AUTOSLEEP_BIT;
498 break;
499 default:
500 spin_unlock_irqrestore(&s->data_lock, flags);
501 dev_warn(&s->spi->dev, "invalid sleep mode\n");
502 return;
503 }
504 buf[0] |= s->mode1_reg;
505 spin_unlock_irqrestore(&s->data_lock, flags);
506
507 if (max3107_rw(s, (u8 *)buf, NULL, 2))
508 dev_err(&s->spi->dev, "SPI transfer sleep mode failed\n");
509
510 if (mode == MAX3107_DISABLE_AUTOSLEEP ||
511 mode == MAX3107_DISABLE_FORCED_SLEEP)
512 msleep(MAX3107_WAKEUP_DELAY);
513 }
514
515 /* Perform full register initialization */
516 static void max3107_register_init(struct max3107_port *s)
517 {
518 u16 buf[11]; /* Buffer for SPI transfers */
519
520 /* 1. Configure baud rate, 9600 as default */
521 s->baud = 9600;
522 /* the below is default*/
523 if (s->ext_clk) {
524 s->brg_cfg = MAX3107_BRG26_B9600;
525 s->baud_tbl = (struct baud_table *)brg26_ext;
526 } else {
527 s->brg_cfg = MAX3107_BRG13_IB9600;
528 s->baud_tbl = (struct baud_table *)brg13_int;
529 }
530
531 if (s->pdata->init)
532 s->pdata->init(s);
533
534 buf[0] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVMSB_REG)
535 | ((s->brg_cfg >> 16) & MAX3107_SPI_TX_DATA_MASK);
536 buf[1] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVLSB_REG)
537 | ((s->brg_cfg >> 8) & MAX3107_SPI_TX_DATA_MASK);
538 buf[2] = (MAX3107_WRITE_BIT | MAX3107_BRGCFG_REG)
539 | ((s->brg_cfg) & 0xff);
540
541 /* 2. Configure LCR register, 8N1 mode by default */
542 s->lcr_reg = MAX3107_LCR_WORD_LEN_8;
543 buf[3] = (MAX3107_WRITE_BIT | MAX3107_LCR_REG)
544 | s->lcr_reg;
545
546 /* 3. Configure MODE 1 register */
547 s->mode1_reg = 0;
548 /* Enable IRQ pin */
549 s->mode1_reg |= MAX3107_MODE1_IRQSEL_BIT;
550 /* Disable TX */
551 s->mode1_reg |= MAX3107_MODE1_TXDIS_BIT;
552 s->tx_enabled = 0;
553 /* RX is enabled */
554 s->rx_enabled = 1;
555 buf[4] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG)
556 | s->mode1_reg;
557
558 /* 4. Configure MODE 2 register */
559 buf[5] = (MAX3107_WRITE_BIT | MAX3107_MODE2_REG);
560 if (s->loopback) {
561 /* Enable loopback */
562 buf[5] |= MAX3107_MODE2_LOOPBACK_BIT;
563 }
564 /* Reset FIFOs */
565 buf[5] |= MAX3107_MODE2_FIFORST_BIT;
566 s->tx_fifo_empty = 1;
567
568 /* 5. Configure FIFO trigger level register */
569 buf[6] = (MAX3107_WRITE_BIT | MAX3107_FIFOTRIGLVL_REG);
570 /* RX FIFO trigger for 16 words, TX FIFO trigger not used */
571 buf[6] |= (MAX3107_FIFOTRIGLVL_RX(16) | MAX3107_FIFOTRIGLVL_TX(0));
572
573 /* 6. Configure flow control levels */
574 buf[7] = (MAX3107_WRITE_BIT | MAX3107_FLOWLVL_REG);
575 /* Flow control halt level 96, resume level 48 */
576 buf[7] |= (MAX3107_FLOWLVL_RES(48) | MAX3107_FLOWLVL_HALT(96));
577
578 /* 7. Configure flow control */
579 buf[8] = (MAX3107_WRITE_BIT | MAX3107_FLOWCTRL_REG);
580 /* Enable auto CTS and auto RTS flow control */
581 buf[8] |= (MAX3107_FLOWCTRL_AUTOCTS_BIT | MAX3107_FLOWCTRL_AUTORTS_BIT);
582
583 /* 8. Configure RX timeout register */
584 buf[9] = (MAX3107_WRITE_BIT | MAX3107_RXTO_REG);
585 /* Timeout after 48 character intervals */
586 buf[9] |= 0x0030;
587
588 /* 9. Configure LSR interrupt enable register */
589 buf[10] = (MAX3107_WRITE_BIT | MAX3107_LSR_IRQEN_REG);
590 /* Enable RX timeout interrupt */
591 buf[10] |= MAX3107_LSR_RXTO_BIT;
592
593 /* Perform SPI transfer */
594 if (max3107_rw(s, (u8 *)buf, NULL, 22))
595 dev_err(&s->spi->dev, "SPI transfer for init failed\n");
596
597 /* 10. Clear IRQ status register by reading it */
598 buf[0] = MAX3107_IRQSTS_REG;
599
600 /* 11. Configure interrupt enable register */
601 /* Enable LSR interrupt */
602 s->irqen_reg = MAX3107_IRQ_LSR_BIT;
603 /* Enable RX FIFO interrupt */
604 s->irqen_reg |= MAX3107_IRQ_RXFIFO_BIT;
605 buf[1] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG)
606 | s->irqen_reg;
607
608 /* 12. Clear FIFO reset that was set in step 6 */
609 buf[2] = (MAX3107_WRITE_BIT | MAX3107_MODE2_REG);
610 if (s->loopback) {
611 /* Keep loopback enabled */
612 buf[2] |= MAX3107_MODE2_LOOPBACK_BIT;
613 }
614
615 /* Perform SPI transfer */
616 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 6))
617 dev_err(&s->spi->dev, "SPI transfer for init failed\n");
618
619 }
620
621 /* IRQ handler */
622 static irqreturn_t max3107_irq(int irqno, void *dev_id)
623 {
624 struct max3107_port *s = dev_id;
625
626 if (irqno != s->spi->irq) {
627 /* Unexpected IRQ */
628 return IRQ_NONE;
629 }
630
631 /* Indicate irq */
632 s->handle_irq = 1;
633
634 /* Trigger work thread */
635 max3107_dowork(s);
636
637 return IRQ_HANDLED;
638 }
639
640 /* HW suspension function
641 *
642 * Currently autosleep is used to decrease current consumption, alternative
643 * approach would be to set the chip to reset mode if UART is not being
644 * used but that would mess the GPIOs
645 *
646 */
647 void max3107_hw_susp(struct max3107_port *s, int suspend)
648 {
649 pr_debug("enter, suspend %d\n", suspend);
650
651 if (suspend) {
652 /* Suspend requested,
653 * enable autosleep to decrease current consumption
654 */
655 s->suspended = 1;
656 max3107_set_sleep(s, MAX3107_ENABLE_AUTOSLEEP);
657 } else {
658 /* Resume requested,
659 * disable autosleep
660 */
661 s->suspended = 0;
662 max3107_set_sleep(s, MAX3107_DISABLE_AUTOSLEEP);
663 }
664 }
665 EXPORT_SYMBOL_GPL(max3107_hw_susp);
666
667 /* Modem status IRQ enabling */
668 static void max3107_enable_ms(struct uart_port *port)
669 {
670 /* Modem status not supported */
671 }
672
673 /* Data send function */
674 static void max3107_start_tx(struct uart_port *port)
675 {
676 struct max3107_port *s = container_of(port, struct max3107_port, port);
677
678 /* Trigger work thread for sending data */
679 max3107_dowork(s);
680 }
681
682 /* Function for checking that there is no pending transfers */
683 static unsigned int max3107_tx_empty(struct uart_port *port)
684 {
685 struct max3107_port *s = container_of(port, struct max3107_port, port);
686
687 pr_debug("returning %d\n",
688 (s->tx_fifo_empty && uart_circ_empty(&s->port.state->xmit)));
689 return s->tx_fifo_empty && uart_circ_empty(&s->port.state->xmit);
690 }
691
692 /* Function for stopping RX */
693 static void max3107_stop_rx(struct uart_port *port)
694 {
695 struct max3107_port *s = container_of(port, struct max3107_port, port);
696 unsigned long flags;
697
698 /* Set RX disabled in MODE 1 register */
699 spin_lock_irqsave(&s->data_lock, flags);
700 s->mode1_reg |= MAX3107_MODE1_RXDIS_BIT;
701 s->mode1_commit = 1;
702 spin_unlock_irqrestore(&s->data_lock, flags);
703 /* Set RX disabled */
704 s->rx_enabled = 0;
705 /* Trigger work thread for doing the actual configuration change */
706 max3107_dowork(s);
707 }
708
709 /* Function for returning control pin states */
710 static unsigned int max3107_get_mctrl(struct uart_port *port)
711 {
712 /* DCD and DSR are not wired and CTS/RTS is handled automatically
713 * so just indicate DSR and CAR asserted
714 */
715 return TIOCM_DSR | TIOCM_CAR;
716 }
717
718 /* Function for setting control pin states */
719 static void max3107_set_mctrl(struct uart_port *port, unsigned int mctrl)
720 {
721 /* DCD and DSR are not wired and CTS/RTS is hadnled automatically
722 * so do nothing
723 */
724 }
725
726 /* Function for configuring UART parameters */
727 static void max3107_set_termios(struct uart_port *port,
728 struct ktermios *termios,
729 struct ktermios *old)
730 {
731 struct max3107_port *s = container_of(port, struct max3107_port, port);
732 struct tty_struct *tty;
733 int baud;
734 u16 new_lcr = 0;
735 u32 new_brg = 0;
736 unsigned long flags;
737
738 if (!port->state)
739 return;
740
741 tty = port->state->port.tty;
742 if (!tty)
743 return;
744
745 /* Get new LCR register values */
746 /* Word size */
747 if ((termios->c_cflag & CSIZE) == CS7)
748 new_lcr |= MAX3107_LCR_WORD_LEN_7;
749 else
750 new_lcr |= MAX3107_LCR_WORD_LEN_8;
751
752 /* Parity */
753 if (termios->c_cflag & PARENB) {
754 new_lcr |= MAX3107_LCR_PARITY_BIT;
755 if (!(termios->c_cflag & PARODD))
756 new_lcr |= MAX3107_LCR_EVENPARITY_BIT;
757 }
758
759 /* Stop bits */
760 if (termios->c_cflag & CSTOPB) {
761 /* 2 stop bits */
762 new_lcr |= MAX3107_LCR_STOPLEN_BIT;
763 }
764
765 /* Mask termios capabilities we don't support */
766 termios->c_cflag &= ~CMSPAR;
767
768 /* Set status ignore mask */
769 s->port.ignore_status_mask = 0;
770 if (termios->c_iflag & IGNPAR)
771 s->port.ignore_status_mask |= MAX3107_ALL_ERRORS;
772
773 /* Set low latency to immediately handle pushed data */
774 s->port.state->port.tty->low_latency = 1;
775
776 /* Get new baud rate generator configuration */
777 baud = tty_get_baud_rate(tty);
778
779 spin_lock_irqsave(&s->data_lock, flags);
780 new_brg = get_new_brg(baud, s);
781 /* if can't find the corrent config, use previous */
782 if (!new_brg) {
783 baud = s->baud;
784 new_brg = s->brg_cfg;
785 }
786 spin_unlock_irqrestore(&s->data_lock, flags);
787 tty_termios_encode_baud_rate(termios, baud, baud);
788 s->baud = baud;
789
790 /* Update timeout according to new baud rate */
791 uart_update_timeout(port, termios->c_cflag, baud);
792
793 spin_lock_irqsave(&s->data_lock, flags);
794 if (s->lcr_reg != new_lcr) {
795 s->lcr_reg = new_lcr;
796 s->lcr_commit = 1;
797 }
798 if (s->brg_cfg != new_brg) {
799 s->brg_cfg = new_brg;
800 s->brg_commit = 1;
801 }
802 spin_unlock_irqrestore(&s->data_lock, flags);
803
804 /* Trigger work thread for doing the actual configuration change */
805 max3107_dowork(s);
806 }
807
808 /* Port shutdown function */
809 static void max3107_shutdown(struct uart_port *port)
810 {
811 struct max3107_port *s = container_of(port, struct max3107_port, port);
812
813 if (s->suspended && s->pdata->hw_suspend)
814 s->pdata->hw_suspend(s, 0);
815
816 /* Free the interrupt */
817 free_irq(s->spi->irq, s);
818
819 if (s->workqueue) {
820 /* Flush and destroy work queue */
821 flush_workqueue(s->workqueue);
822 destroy_workqueue(s->workqueue);
823 s->workqueue = NULL;
824 }
825
826 /* Suspend HW */
827 if (s->pdata->hw_suspend)
828 s->pdata->hw_suspend(s, 1);
829 }
830
831 /* Port startup function */
832 static int max3107_startup(struct uart_port *port)
833 {
834 struct max3107_port *s = container_of(port, struct max3107_port, port);
835
836 /* Initialize work queue */
837 s->workqueue = create_freezable_workqueue("max3107");
838 if (!s->workqueue) {
839 dev_err(&s->spi->dev, "Workqueue creation failed\n");
840 return -EBUSY;
841 }
842 INIT_WORK(&s->work, max3107_work);
843
844 /* Setup IRQ */
845 if (request_irq(s->spi->irq, max3107_irq, IRQF_TRIGGER_FALLING,
846 "max3107", s)) {
847 dev_err(&s->spi->dev, "IRQ reguest failed\n");
848 destroy_workqueue(s->workqueue);
849 s->workqueue = NULL;
850 return -EBUSY;
851 }
852
853 /* Resume HW */
854 if (s->pdata->hw_suspend)
855 s->pdata->hw_suspend(s, 0);
856
857 /* Init registers */
858 max3107_register_init(s);
859
860 return 0;
861 }
862
863 /* Port type function */
864 static const char *max3107_type(struct uart_port *port)
865 {
866 struct max3107_port *s = container_of(port, struct max3107_port, port);
867 return s->spi->modalias;
868 }
869
870 /* Port release function */
871 static void max3107_release_port(struct uart_port *port)
872 {
873 /* Do nothing */
874 }
875
876 /* Port request function */
877 static int max3107_request_port(struct uart_port *port)
878 {
879 /* Do nothing */
880 return 0;
881 }
882
883 /* Port config function */
884 static void max3107_config_port(struct uart_port *port, int flags)
885 {
886 struct max3107_port *s = container_of(port, struct max3107_port, port);
887 s->port.type = PORT_MAX3107;
888 }
889
890 /* Port verify function */
891 static int max3107_verify_port(struct uart_port *port,
892 struct serial_struct *ser)
893 {
894 if (ser->type == PORT_UNKNOWN || ser->type == PORT_MAX3107)
895 return 0;
896
897 return -EINVAL;
898 }
899
900 /* Port stop TX function */
901 static void max3107_stop_tx(struct uart_port *port)
902 {
903 /* Do nothing */
904 }
905
906 /* Port break control function */
907 static void max3107_break_ctl(struct uart_port *port, int break_state)
908 {
909 /* We don't support break control, do nothing */
910 }
911
912
913 /* Port functions */
914 static struct uart_ops max3107_ops = {
915 .tx_empty = max3107_tx_empty,
916 .set_mctrl = max3107_set_mctrl,
917 .get_mctrl = max3107_get_mctrl,
918 .stop_tx = max3107_stop_tx,
919 .start_tx = max3107_start_tx,
920 .stop_rx = max3107_stop_rx,
921 .enable_ms = max3107_enable_ms,
922 .break_ctl = max3107_break_ctl,
923 .startup = max3107_startup,
924 .shutdown = max3107_shutdown,
925 .set_termios = max3107_set_termios,
926 .type = max3107_type,
927 .release_port = max3107_release_port,
928 .request_port = max3107_request_port,
929 .config_port = max3107_config_port,
930 .verify_port = max3107_verify_port,
931 };
932
933 /* UART driver data */
934 static struct uart_driver max3107_uart_driver = {
935 .owner = THIS_MODULE,
936 .driver_name = "ttyMAX",
937 .dev_name = "ttyMAX",
938 .nr = 1,
939 };
940
941 static int driver_registered = 0;
942
943
944
945 /* 'Generic' platform data */
946 static struct max3107_plat generic_plat_data = {
947 .loopback = 0,
948 .ext_clk = 1,
949 .hw_suspend = max3107_hw_susp,
950 .polled_mode = 0,
951 .poll_time = 0,
952 };
953
954
955 /*******************************************************************/
956
957 /**
958 * max3107_probe - SPI bus probe entry point
959 * @spi: the spi device
960 *
961 * SPI wants us to probe this device and if appropriate claim it.
962 * Perform any platform specific requirements and then initialise
963 * the device.
964 */
965
966 int max3107_probe(struct spi_device *spi, struct max3107_plat *pdata)
967 {
968 struct max3107_port *s;
969 u16 buf[2]; /* Buffer for SPI transfers */
970 int retval;
971
972 pr_info("enter max3107 probe\n");
973
974 /* Allocate port structure */
975 s = kzalloc(sizeof(*s), GFP_KERNEL);
976 if (!s) {
977 pr_err("Allocating port structure failed\n");
978 return -ENOMEM;
979 }
980
981 s->pdata = pdata;
982
983 /* SPI Rx buffer
984 * +2 for RX FIFO interrupt
985 * disabling and RX level query
986 */
987 s->rxbuf = kzalloc(sizeof(u16) * (MAX3107_RX_FIFO_SIZE+2), GFP_KERNEL);
988 if (!s->rxbuf) {
989 pr_err("Allocating RX buffer failed\n");
990 retval = -ENOMEM;
991 goto err_free4;
992 }
993 s->rxstr = kzalloc(sizeof(u8) * MAX3107_RX_FIFO_SIZE, GFP_KERNEL);
994 if (!s->rxstr) {
995 pr_err("Allocating RX buffer failed\n");
996 retval = -ENOMEM;
997 goto err_free3;
998 }
999 /* SPI Tx buffer
1000 * SPI transfer buffer
1001 * +3 for TX FIFO empty
1002 * interrupt disabling and
1003 * enabling and TX enabling
1004 */
1005 s->txbuf = kzalloc(sizeof(u16) * MAX3107_TX_FIFO_SIZE + 3, GFP_KERNEL);
1006 if (!s->txbuf) {
1007 pr_err("Allocating TX buffer failed\n");
1008 retval = -ENOMEM;
1009 goto err_free2;
1010 }
1011 /* Initialize shared data lock */
1012 spin_lock_init(&s->data_lock);
1013
1014 /* SPI intializations */
1015 dev_set_drvdata(&spi->dev, s);
1016 spi->mode = SPI_MODE_0;
1017 spi->dev.platform_data = pdata;
1018 spi->bits_per_word = 16;
1019 s->ext_clk = pdata->ext_clk;
1020 s->loopback = pdata->loopback;
1021 spi_setup(spi);
1022 s->spi = spi;
1023
1024 /* Check REV ID to ensure we are talking to what we expect */
1025 buf[0] = MAX3107_REVID_REG;
1026 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
1027 dev_err(&s->spi->dev, "SPI transfer for REVID read failed\n");
1028 retval = -EIO;
1029 goto err_free1;
1030 }
1031 if ((buf[0] & MAX3107_SPI_RX_DATA_MASK) != MAX3107_REVID1 &&
1032 (buf[0] & MAX3107_SPI_RX_DATA_MASK) != MAX3107_REVID2) {
1033 dev_err(&s->spi->dev, "REVID %x does not match\n",
1034 (buf[0] & MAX3107_SPI_RX_DATA_MASK));
1035 retval = -ENODEV;
1036 goto err_free1;
1037 }
1038
1039 /* Disable all interrupts */
1040 buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG | 0x0000);
1041 buf[0] |= 0x0000;
1042
1043 /* Configure clock source */
1044 buf[1] = (MAX3107_WRITE_BIT | MAX3107_CLKSRC_REG);
1045 if (s->ext_clk) {
1046 /* External clock */
1047 buf[1] |= MAX3107_CLKSRC_EXTCLK_BIT;
1048 }
1049
1050 /* PLL bypass ON */
1051 buf[1] |= MAX3107_CLKSRC_PLLBYP_BIT;
1052
1053 /* Perform SPI transfer */
1054 if (max3107_rw(s, (u8 *)buf, NULL, 4)) {
1055 dev_err(&s->spi->dev, "SPI transfer for init failed\n");
1056 retval = -EIO;
1057 goto err_free1;
1058 }
1059
1060 /* Register UART driver */
1061 if (!driver_registered) {
1062 retval = uart_register_driver(&max3107_uart_driver);
1063 if (retval) {
1064 dev_err(&s->spi->dev, "Registering UART driver failed\n");
1065 goto err_free1;
1066 }
1067 driver_registered = 1;
1068 }
1069
1070 /* Initialize UART port data */
1071 s->port.fifosize = 128;
1072 s->port.ops = &max3107_ops;
1073 s->port.line = 0;
1074 s->port.dev = &spi->dev;
1075 s->port.uartclk = 9600;
1076 s->port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF;
1077 s->port.irq = s->spi->irq;
1078 s->port.type = PORT_MAX3107;
1079
1080 /* Add UART port */
1081 retval = uart_add_one_port(&max3107_uart_driver, &s->port);
1082 if (retval < 0) {
1083 dev_err(&s->spi->dev, "Adding UART port failed\n");
1084 goto err_free1;
1085 }
1086
1087 if (pdata->configure) {
1088 retval = pdata->configure(s);
1089 if (retval < 0)
1090 goto err_free1;
1091 }
1092
1093 /* Go to suspend mode */
1094 if (pdata->hw_suspend)
1095 pdata->hw_suspend(s, 1);
1096
1097 return 0;
1098
1099 err_free1:
1100 kfree(s->txbuf);
1101 err_free2:
1102 kfree(s->rxstr);
1103 err_free3:
1104 kfree(s->rxbuf);
1105 err_free4:
1106 kfree(s);
1107 return retval;
1108 }
1109 EXPORT_SYMBOL_GPL(max3107_probe);
1110
1111 /* Driver remove function */
1112 int max3107_remove(struct spi_device *spi)
1113 {
1114 struct max3107_port *s = dev_get_drvdata(&spi->dev);
1115
1116 pr_info("enter max3107 remove\n");
1117
1118 /* Remove port */
1119 if (uart_remove_one_port(&max3107_uart_driver, &s->port))
1120 dev_warn(&s->spi->dev, "Removing UART port failed\n");
1121
1122
1123 /* Free TxRx buffer */
1124 kfree(s->rxbuf);
1125 kfree(s->rxstr);
1126 kfree(s->txbuf);
1127
1128 /* Free port structure */
1129 kfree(s);
1130
1131 return 0;
1132 }
1133 EXPORT_SYMBOL_GPL(max3107_remove);
1134
1135 /* Driver suspend function */
1136 int max3107_suspend(struct spi_device *spi, pm_message_t state)
1137 {
1138 #ifdef CONFIG_PM
1139 struct max3107_port *s = dev_get_drvdata(&spi->dev);
1140
1141 pr_debug("enter suspend\n");
1142
1143 /* Suspend UART port */
1144 uart_suspend_port(&max3107_uart_driver, &s->port);
1145
1146 /* Go to suspend mode */
1147 if (s->pdata->hw_suspend)
1148 s->pdata->hw_suspend(s, 1);
1149 #endif /* CONFIG_PM */
1150 return 0;
1151 }
1152 EXPORT_SYMBOL_GPL(max3107_suspend);
1153
1154 /* Driver resume function */
1155 int max3107_resume(struct spi_device *spi)
1156 {
1157 #ifdef CONFIG_PM
1158 struct max3107_port *s = dev_get_drvdata(&spi->dev);
1159
1160 pr_debug("enter resume\n");
1161
1162 /* Resume from suspend */
1163 if (s->pdata->hw_suspend)
1164 s->pdata->hw_suspend(s, 0);
1165
1166 /* Resume UART port */
1167 uart_resume_port(&max3107_uart_driver, &s->port);
1168 #endif /* CONFIG_PM */
1169 return 0;
1170 }
1171 EXPORT_SYMBOL_GPL(max3107_resume);
1172
1173 static int max3107_probe_generic(struct spi_device *spi)
1174 {
1175 return max3107_probe(spi, &generic_plat_data);
1176 }
1177
1178 /* Spi driver data */
1179 static struct spi_driver max3107_driver = {
1180 .driver = {
1181 .name = "max3107",
1182 .bus = &spi_bus_type,
1183 .owner = THIS_MODULE,
1184 },
1185 .probe = max3107_probe_generic,
1186 .remove = __devexit_p(max3107_remove),
1187 .suspend = max3107_suspend,
1188 .resume = max3107_resume,
1189 };
1190
1191 /* Driver init function */
1192 static int __init max3107_init(void)
1193 {
1194 pr_info("enter max3107 init\n");
1195 return spi_register_driver(&max3107_driver);
1196 }
1197
1198 /* Driver exit function */
1199 static void __exit max3107_exit(void)
1200 {
1201 pr_info("enter max3107 exit\n");
1202 /* Unregister UART driver */
1203 if (driver_registered)
1204 uart_unregister_driver(&max3107_uart_driver);
1205 spi_unregister_driver(&max3107_driver);
1206 }
1207
1208 module_init(max3107_init);
1209 module_exit(max3107_exit);
1210
1211 MODULE_DESCRIPTION("MAX3107 driver");
1212 MODULE_AUTHOR("Aavamobile");
1213 MODULE_ALIAS("spi:max3107");
1214 MODULE_LICENSE("GPL v2");
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