?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Add linux-next specific files for 20110831
[linux-2.6/next.git] / drivers / tty / serial / pch_uart.c
blobb46218d679e21e4561657b8cf5508e7138d5e03e
1 /*
2 *Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
3 *
4 *This program is free software; you can redistribute it and/or modify
5 *it under the terms of the GNU General Public License as published by
6 *the Free Software Foundation; version 2 of the License.
7 *
8 *This program is distributed in the hope that it will be useful,
9 *but WITHOUT ANY WARRANTY; without even the implied warranty of
10 *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 *GNU General Public License for more details.
12 *
13 *You should have received a copy of the GNU General Public License
14 *along with this program; if not, write to the Free Software
15 *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 */
17 #include <linux/kernel.h>
18 #include <linux/serial_reg.h>
19 #include <linux/slab.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/serial_core.h>
23 #include <linux/interrupt.h>
24 #include <linux/io.h>
25 #include <linux/dmi.h>
26
27 #include <linux/dmaengine.h>
28 #include <linux/pch_dma.h>
29
30 enum {
31 PCH_UART_HANDLED_RX_INT_SHIFT,
32 PCH_UART_HANDLED_TX_INT_SHIFT,
33 PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
34 PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
35 PCH_UART_HANDLED_MS_INT_SHIFT,
36 };
37
38 enum {
39 PCH_UART_8LINE,
40 PCH_UART_2LINE,
41 };
42
43 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
44
45 /* Set the max number of UART port
46 * Intel EG20T PCH: 4 port
47 * OKI SEMICONDUCTOR ML7213 IOH: 3 port
48 * OKI SEMICONDUCTOR ML7223 IOH: 2 port
49 */
50 #define PCH_UART_NR 4
51
52 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
53 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
54 #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\
55 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
56 #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\
57 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
58 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
59
60 #define PCH_UART_RBR 0x00
61 #define PCH_UART_THR 0x00
62
63 #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
64 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
65 #define PCH_UART_IER_ERBFI 0x00000001
66 #define PCH_UART_IER_ETBEI 0x00000002
67 #define PCH_UART_IER_ELSI 0x00000004
68 #define PCH_UART_IER_EDSSI 0x00000008
69
70 #define PCH_UART_IIR_IP 0x00000001
71 #define PCH_UART_IIR_IID 0x00000006
72 #define PCH_UART_IIR_MSI 0x00000000
73 #define PCH_UART_IIR_TRI 0x00000002
74 #define PCH_UART_IIR_RRI 0x00000004
75 #define PCH_UART_IIR_REI 0x00000006
76 #define PCH_UART_IIR_TOI 0x00000008
77 #define PCH_UART_IIR_FIFO256 0x00000020
78 #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256
79 #define PCH_UART_IIR_FE 0x000000C0
80
81 #define PCH_UART_FCR_FIFOE 0x00000001
82 #define PCH_UART_FCR_RFR 0x00000002
83 #define PCH_UART_FCR_TFR 0x00000004
84 #define PCH_UART_FCR_DMS 0x00000008
85 #define PCH_UART_FCR_FIFO256 0x00000020
86 #define PCH_UART_FCR_RFTL 0x000000C0
87
88 #define PCH_UART_FCR_RFTL1 0x00000000
89 #define PCH_UART_FCR_RFTL64 0x00000040
90 #define PCH_UART_FCR_RFTL128 0x00000080
91 #define PCH_UART_FCR_RFTL224 0x000000C0
92 #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64
93 #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128
94 #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224
95 #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64
96 #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128
97 #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224
98 #define PCH_UART_FCR_RFTL_SHIFT 6
99
100 #define PCH_UART_LCR_WLS 0x00000003
101 #define PCH_UART_LCR_STB 0x00000004
102 #define PCH_UART_LCR_PEN 0x00000008
103 #define PCH_UART_LCR_EPS 0x00000010
104 #define PCH_UART_LCR_SP 0x00000020
105 #define PCH_UART_LCR_SB 0x00000040
106 #define PCH_UART_LCR_DLAB 0x00000080
107 #define PCH_UART_LCR_NP 0x00000000
108 #define PCH_UART_LCR_OP PCH_UART_LCR_PEN
109 #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
110 #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
111 #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
112 PCH_UART_LCR_SP)
113
114 #define PCH_UART_LCR_5BIT 0x00000000
115 #define PCH_UART_LCR_6BIT 0x00000001
116 #define PCH_UART_LCR_7BIT 0x00000002
117 #define PCH_UART_LCR_8BIT 0x00000003
118
119 #define PCH_UART_MCR_DTR 0x00000001
120 #define PCH_UART_MCR_RTS 0x00000002
121 #define PCH_UART_MCR_OUT 0x0000000C
122 #define PCH_UART_MCR_LOOP 0x00000010
123 #define PCH_UART_MCR_AFE 0x00000020
124
125 #define PCH_UART_LSR_DR 0x00000001
126 #define PCH_UART_LSR_ERR (1<<7)
127
128 #define PCH_UART_MSR_DCTS 0x00000001
129 #define PCH_UART_MSR_DDSR 0x00000002
130 #define PCH_UART_MSR_TERI 0x00000004
131 #define PCH_UART_MSR_DDCD 0x00000008
132 #define PCH_UART_MSR_CTS 0x00000010
133 #define PCH_UART_MSR_DSR 0x00000020
134 #define PCH_UART_MSR_RI 0x00000040
135 #define PCH_UART_MSR_DCD 0x00000080
136 #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
137 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
138
139 #define PCH_UART_DLL 0x00
140 #define PCH_UART_DLM 0x01
141
142 #define PCH_UART_IID_RLS (PCH_UART_IIR_REI)
143 #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI)
144 #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
145 #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI)
146 #define PCH_UART_IID_MS (PCH_UART_IIR_MSI)
147
148 #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP)
149 #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP)
150 #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP)
151 #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P)
152 #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P)
153 #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT)
154 #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT)
155 #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT)
156 #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT)
157 #define PCH_UART_HAL_STB1 0
158 #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB)
159
160 #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR)
161 #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR)
162 #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \
163 PCH_UART_HAL_CLR_RX_FIFO)
164
165 #define PCH_UART_HAL_DMA_MODE0 0
166 #define PCH_UART_HAL_FIFO_DIS 0
167 #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE)
168 #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \
169 PCH_UART_FCR_FIFO256)
170 #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256)
171 #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1)
172 #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64)
173 #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128)
174 #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224)
175 #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16)
176 #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32)
177 #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56)
178 #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4)
179 #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8)
180 #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14)
181 #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64)
182 #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128)
183 #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224)
184
185 #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI)
186 #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI)
187 #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI)
188 #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI)
189 #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK)
190
191 #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR)
192 #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS)
193 #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT)
194 #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP)
195 #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE)
196
197 #define PCI_VENDOR_ID_ROHM 0x10DB
198
199 struct pch_uart_buffer {
200 unsigned char *buf;
201 int size;
202 };
203
204 struct eg20t_port {
205 struct uart_port port;
206 int port_type;
207 void __iomem *membase;
208 resource_size_t mapbase;
209 unsigned int iobase;
210 struct pci_dev *pdev;
211 int fifo_size;
212 int base_baud;
213 int start_tx;
214 int start_rx;
215 int tx_empty;
216 int int_dis_flag;
217 int trigger;
218 int trigger_level;
219 struct pch_uart_buffer rxbuf;
220 unsigned int dmsr;
221 unsigned int fcr;
222 unsigned int mcr;
223 unsigned int use_dma;
224 unsigned int use_dma_flag;
225 struct dma_async_tx_descriptor *desc_tx;
226 struct dma_async_tx_descriptor *desc_rx;
227 struct pch_dma_slave param_tx;
228 struct pch_dma_slave param_rx;
229 struct dma_chan *chan_tx;
230 struct dma_chan *chan_rx;
231 struct scatterlist *sg_tx_p;
232 int nent;
233 struct scatterlist sg_rx;
234 int tx_dma_use;
235 void *rx_buf_virt;
236 dma_addr_t rx_buf_dma;
237 };
238
239 /**
240 * struct pch_uart_driver_data - private data structure for UART-DMA
241 * @port_type: The number of DMA channel
242 * @line_no: UART port line number (0, 1, 2...)
243 */
244 struct pch_uart_driver_data {
245 int port_type;
246 int line_no;
247 };
248
249 enum pch_uart_num_t {
250 pch_et20t_uart0 = 0,
251 pch_et20t_uart1,
252 pch_et20t_uart2,
253 pch_et20t_uart3,
254 pch_ml7213_uart0,
255 pch_ml7213_uart1,
256 pch_ml7213_uart2,
257 pch_ml7223_uart0,
258 pch_ml7223_uart1,
259 };
260
261 static struct pch_uart_driver_data drv_dat[] = {
262 [pch_et20t_uart0] = {PCH_UART_8LINE, 0},
263 [pch_et20t_uart1] = {PCH_UART_2LINE, 1},
264 [pch_et20t_uart2] = {PCH_UART_2LINE, 2},
265 [pch_et20t_uart3] = {PCH_UART_2LINE, 3},
266 [pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
267 [pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
268 [pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
269 [pch_ml7223_uart0] = {PCH_UART_8LINE, 0},
270 [pch_ml7223_uart1] = {PCH_UART_2LINE, 1},
271 };
272
273 static unsigned int default_baud = 9600;
274 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
275 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
276 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
277 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
278
279 static void pch_uart_hal_request(struct pci_dev *pdev, int fifosize,
280 int base_baud)
281 {
282 struct eg20t_port *priv = pci_get_drvdata(pdev);
283
284 priv->trigger_level = 1;
285 priv->fcr = 0;
286 }
287
288 static unsigned int get_msr(struct eg20t_port *priv, void __iomem *base)
289 {
290 unsigned int msr = ioread8(base + UART_MSR);
291 priv->dmsr |= msr & PCH_UART_MSR_DELTA;
292
293 return msr;
294 }
295
296 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
297 unsigned int flag)
298 {
299 u8 ier = ioread8(priv->membase + UART_IER);
300 ier |= flag & PCH_UART_IER_MASK;
301 iowrite8(ier, priv->membase + UART_IER);
302 }
303
304 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
305 unsigned int flag)
306 {
307 u8 ier = ioread8(priv->membase + UART_IER);
308 ier &= ~(flag & PCH_UART_IER_MASK);
309 iowrite8(ier, priv->membase + UART_IER);
310 }
311
312 static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud,
313 unsigned int parity, unsigned int bits,
314 unsigned int stb)
315 {
316 unsigned int dll, dlm, lcr;
317 int div;
318
319 div = DIV_ROUND_CLOSEST(priv->base_baud / 16, baud);
320 if (div < 0 || USHRT_MAX <= div) {
321 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
322 return -EINVAL;
323 }
324
325 dll = (unsigned int)div & 0x00FFU;
326 dlm = ((unsigned int)div >> 8) & 0x00FFU;
327
328 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
329 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
330 return -EINVAL;
331 }
332
333 if (bits & ~PCH_UART_LCR_WLS) {
334 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
335 return -EINVAL;
336 }
337
338 if (stb & ~PCH_UART_LCR_STB) {
339 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
340 return -EINVAL;
341 }
342
343 lcr = parity;
344 lcr |= bits;
345 lcr |= stb;
346
347 dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n",
348 __func__, baud, div, lcr, jiffies);
349 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
350 iowrite8(dll, priv->membase + PCH_UART_DLL);
351 iowrite8(dlm, priv->membase + PCH_UART_DLM);
352 iowrite8(lcr, priv->membase + UART_LCR);
353
354 return 0;
355 }
356
357 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
358 unsigned int flag)
359 {
360 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
361 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
362 __func__, flag);
363 return -EINVAL;
364 }
365
366 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
367 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
368 priv->membase + UART_FCR);
369 iowrite8(priv->fcr, priv->membase + UART_FCR);
370
371 return 0;
372 }
373
374 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
375 unsigned int dmamode,
376 unsigned int fifo_size, unsigned int trigger)
377 {
378 u8 fcr;
379
380 if (dmamode & ~PCH_UART_FCR_DMS) {
381 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
382 __func__, dmamode);
383 return -EINVAL;
384 }
385
386 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
387 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
388 __func__, fifo_size);
389 return -EINVAL;
390 }
391
392 if (trigger & ~PCH_UART_FCR_RFTL) {
393 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
394 __func__, trigger);
395 return -EINVAL;
396 }
397
398 switch (priv->fifo_size) {
399 case 256:
400 priv->trigger_level =
401 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
402 break;
403 case 64:
404 priv->trigger_level =
405 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
406 break;
407 case 16:
408 priv->trigger_level =
409 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
410 break;
411 default:
412 priv->trigger_level =
413 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
414 break;
415 }
416 fcr =
417 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
418 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
419 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
420 priv->membase + UART_FCR);
421 iowrite8(fcr, priv->membase + UART_FCR);
422 priv->fcr = fcr;
423
424 return 0;
425 }
426
427 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
428 {
429 priv->dmsr = 0;
430 return get_msr(priv, priv->membase);
431 }
432
433 static void pch_uart_hal_write(struct eg20t_port *priv,
434 const unsigned char *buf, int tx_size)
435 {
436 int i;
437 unsigned int thr;
438
439 for (i = 0; i < tx_size;) {
440 thr = buf[i++];
441 iowrite8(thr, priv->membase + PCH_UART_THR);
442 }
443 }
444
445 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
446 int rx_size)
447 {
448 int i;
449 u8 rbr, lsr;
450
451 lsr = ioread8(priv->membase + UART_LSR);
452 for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
453 i < rx_size && lsr & UART_LSR_DR;
454 lsr = ioread8(priv->membase + UART_LSR)) {
455 rbr = ioread8(priv->membase + PCH_UART_RBR);
456 buf[i++] = rbr;
457 }
458 return i;
459 }
460
461 static unsigned int pch_uart_hal_get_iid(struct eg20t_port *priv)
462 {
463 unsigned int iir;
464 int ret;
465
466 iir = ioread8(priv->membase + UART_IIR);
467 ret = (iir & (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP));
468 return ret;
469 }
470
471 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
472 {
473 return ioread8(priv->membase + UART_LSR);
474 }
475
476 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
477 {
478 unsigned int lcr;
479
480 lcr = ioread8(priv->membase + UART_LCR);
481 if (on)
482 lcr |= PCH_UART_LCR_SB;
483 else
484 lcr &= ~PCH_UART_LCR_SB;
485
486 iowrite8(lcr, priv->membase + UART_LCR);
487 }
488
489 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
490 int size)
491 {
492 struct uart_port *port;
493 struct tty_struct *tty;
494
495 port = &priv->port;
496 tty = tty_port_tty_get(&port->state->port);
497 if (!tty) {
498 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
499 return -EBUSY;
500 }
501
502 tty_insert_flip_string(tty, buf, size);
503 tty_flip_buffer_push(tty);
504 tty_kref_put(tty);
505
506 return 0;
507 }
508
509 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
510 {
511 int ret;
512 struct uart_port *port = &priv->port;
513
514 if (port->x_char) {
515 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
516 __func__, port->x_char, jiffies);
517 buf[0] = port->x_char;
518 port->x_char = 0;
519 ret = 1;
520 } else {
521 ret = 0;
522 }
523
524 return ret;
525 }
526
527 static int dma_push_rx(struct eg20t_port *priv, int size)
528 {
529 struct tty_struct *tty;
530 int room;
531 struct uart_port *port = &priv->port;
532
533 port = &priv->port;
534 tty = tty_port_tty_get(&port->state->port);
535 if (!tty) {
536 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
537 return 0;
538 }
539
540 room = tty_buffer_request_room(tty, size);
541
542 if (room < size)
543 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
544 size - room);
545 if (!room)
546 return room;
547
548 tty_insert_flip_string(tty, sg_virt(&priv->sg_rx), size);
549
550 port->icount.rx += room;
551 tty_kref_put(tty);
552
553 return room;
554 }
555
556 static void pch_free_dma(struct uart_port *port)
557 {
558 struct eg20t_port *priv;
559 priv = container_of(port, struct eg20t_port, port);
560
561 if (priv->chan_tx) {
562 dma_release_channel(priv->chan_tx);
563 priv->chan_tx = NULL;
564 }
565 if (priv->chan_rx) {
566 dma_release_channel(priv->chan_rx);
567 priv->chan_rx = NULL;
568 }
569 if (sg_dma_address(&priv->sg_rx))
570 dma_free_coherent(port->dev, port->fifosize,
571 sg_virt(&priv->sg_rx),
572 sg_dma_address(&priv->sg_rx));
573
574 return;
575 }
576
577 static bool filter(struct dma_chan *chan, void *slave)
578 {
579 struct pch_dma_slave *param = slave;
580
581 if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
582 chan->device->dev)) {
583 chan->private = param;
584 return true;
585 } else {
586 return false;
587 }
588 }
589
590 static void pch_request_dma(struct uart_port *port)
591 {
592 dma_cap_mask_t mask;
593 struct dma_chan *chan;
594 struct pci_dev *dma_dev;
595 struct pch_dma_slave *param;
596 struct eg20t_port *priv =
597 container_of(port, struct eg20t_port, port);
598 dma_cap_zero(mask);
599 dma_cap_set(DMA_SLAVE, mask);
600
601 dma_dev = pci_get_bus_and_slot(priv->pdev->bus->number,
602 PCI_DEVFN(0xa, 0)); /* Get DMA's dev
603 information */
604 /* Set Tx DMA */
605 param = &priv->param_tx;
606 param->dma_dev = &dma_dev->dev;
607 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
608
609 param->tx_reg = port->mapbase + UART_TX;
610 chan = dma_request_channel(mask, filter, param);
611 if (!chan) {
612 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
613 __func__);
614 return;
615 }
616 priv->chan_tx = chan;
617
618 /* Set Rx DMA */
619 param = &priv->param_rx;
620 param->dma_dev = &dma_dev->dev;
621 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
622
623 param->rx_reg = port->mapbase + UART_RX;
624 chan = dma_request_channel(mask, filter, param);
625 if (!chan) {
626 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
627 __func__);
628 dma_release_channel(priv->chan_tx);
629 return;
630 }
631
632 /* Get Consistent memory for DMA */
633 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
634 &priv->rx_buf_dma, GFP_KERNEL);
635 priv->chan_rx = chan;
636 }
637
638 static void pch_dma_rx_complete(void *arg)
639 {
640 struct eg20t_port *priv = arg;
641 struct uart_port *port = &priv->port;
642 struct tty_struct *tty = tty_port_tty_get(&port->state->port);
643 int count;
644
645 if (!tty) {
646 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
647 return;
648 }
649
650 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
651 count = dma_push_rx(priv, priv->trigger_level);
652 if (count)
653 tty_flip_buffer_push(tty);
654 tty_kref_put(tty);
655 async_tx_ack(priv->desc_rx);
656 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
657 }
658
659 static void pch_dma_tx_complete(void *arg)
660 {
661 struct eg20t_port *priv = arg;
662 struct uart_port *port = &priv->port;
663 struct circ_buf *xmit = &port->state->xmit;
664 struct scatterlist *sg = priv->sg_tx_p;
665 int i;
666
667 for (i = 0; i < priv->nent; i++, sg++) {
668 xmit->tail += sg_dma_len(sg);
669 port->icount.tx += sg_dma_len(sg);
670 }
671 xmit->tail &= UART_XMIT_SIZE - 1;
672 async_tx_ack(priv->desc_tx);
673 dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE);
674 priv->tx_dma_use = 0;
675 priv->nent = 0;
676 kfree(priv->sg_tx_p);
677 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
678 }
679
680 static int pop_tx(struct eg20t_port *priv, int size)
681 {
682 int count = 0;
683 struct uart_port *port = &priv->port;
684 struct circ_buf *xmit = &port->state->xmit;
685
686 if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
687 goto pop_tx_end;
688
689 do {
690 int cnt_to_end =
691 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
692 int sz = min(size - count, cnt_to_end);
693 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
694 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
695 count += sz;
696 } while (!uart_circ_empty(xmit) && count < size);
697
698 pop_tx_end:
699 dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
700 count, size - count, jiffies);
701
702 return count;
703 }
704
705 static int handle_rx_to(struct eg20t_port *priv)
706 {
707 struct pch_uart_buffer *buf;
708 int rx_size;
709 int ret;
710 if (!priv->start_rx) {
711 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
712 return 0;
713 }
714 buf = &priv->rxbuf;
715 do {
716 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
717 ret = push_rx(priv, buf->buf, rx_size);
718 if (ret)
719 return 0;
720 } while (rx_size == buf->size);
721
722 return PCH_UART_HANDLED_RX_INT;
723 }
724
725 static int handle_rx(struct eg20t_port *priv)
726 {
727 return handle_rx_to(priv);
728 }
729
730 static int dma_handle_rx(struct eg20t_port *priv)
731 {
732 struct uart_port *port = &priv->port;
733 struct dma_async_tx_descriptor *desc;
734 struct scatterlist *sg;
735
736 priv = container_of(port, struct eg20t_port, port);
737 sg = &priv->sg_rx;
738
739 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
740
741 sg_dma_len(sg) = priv->trigger_level;
742
743 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
744 sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
745 ~PAGE_MASK);
746
747 sg_dma_address(sg) = priv->rx_buf_dma;
748
749 desc = priv->chan_rx->device->device_prep_slave_sg(priv->chan_rx,
750 sg, 1, DMA_FROM_DEVICE,
751 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
752
753 if (!desc)
754 return 0;
755
756 priv->desc_rx = desc;
757 desc->callback = pch_dma_rx_complete;
758 desc->callback_param = priv;
759 desc->tx_submit(desc);
760 dma_async_issue_pending(priv->chan_rx);
761
762 return PCH_UART_HANDLED_RX_INT;
763 }
764
765 static unsigned int handle_tx(struct eg20t_port *priv)
766 {
767 struct uart_port *port = &priv->port;
768 struct circ_buf *xmit = &port->state->xmit;
769 int fifo_size;
770 int tx_size;
771 int size;
772 int tx_empty;
773
774 if (!priv->start_tx) {
775 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
776 __func__, jiffies);
777 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
778 priv->tx_empty = 1;
779 return 0;
780 }
781
782 fifo_size = max(priv->fifo_size, 1);
783 tx_empty = 1;
784 if (pop_tx_x(priv, xmit->buf)) {
785 pch_uart_hal_write(priv, xmit->buf, 1);
786 port->icount.tx++;
787 tx_empty = 0;
788 fifo_size--;
789 }
790 size = min(xmit->head - xmit->tail, fifo_size);
791 if (size < 0)
792 size = fifo_size;
793
794 tx_size = pop_tx(priv, size);
795 if (tx_size > 0) {
796 port->icount.tx += tx_size;
797 tx_empty = 0;
798 }
799
800 priv->tx_empty = tx_empty;
801
802 if (tx_empty) {
803 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
804 uart_write_wakeup(port);
805 }
806
807 return PCH_UART_HANDLED_TX_INT;
808 }
809
810 static unsigned int dma_handle_tx(struct eg20t_port *priv)
811 {
812 struct uart_port *port = &priv->port;
813 struct circ_buf *xmit = &port->state->xmit;
814 struct scatterlist *sg;
815 int nent;
816 int fifo_size;
817 int tx_empty;
818 struct dma_async_tx_descriptor *desc;
819 int num;
820 int i;
821 int bytes;
822 int size;
823 int rem;
824
825 if (!priv->start_tx) {
826 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
827 __func__, jiffies);
828 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
829 priv->tx_empty = 1;
830 return 0;
831 }
832
833 if (priv->tx_dma_use) {
834 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
835 __func__, jiffies);
836 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
837 priv->tx_empty = 1;
838 return 0;
839 }
840
841 fifo_size = max(priv->fifo_size, 1);
842 tx_empty = 1;
843 if (pop_tx_x(priv, xmit->buf)) {
844 pch_uart_hal_write(priv, xmit->buf, 1);
845 port->icount.tx++;
846 tx_empty = 0;
847 fifo_size--;
848 }
849
850 bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
851 UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
852 xmit->tail, UART_XMIT_SIZE));
853 if (!bytes) {
854 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
855 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
856 uart_write_wakeup(port);
857 return 0;
858 }
859
860 if (bytes > fifo_size) {
861 num = bytes / fifo_size + 1;
862 size = fifo_size;
863 rem = bytes % fifo_size;
864 } else {
865 num = 1;
866 size = bytes;
867 rem = bytes;
868 }
869
870 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
871 __func__, num, size, rem);
872
873 priv->tx_dma_use = 1;
874
875 priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
876
877 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
878 sg = priv->sg_tx_p;
879
880 for (i = 0; i < num; i++, sg++) {
881 if (i == (num - 1))
882 sg_set_page(sg, virt_to_page(xmit->buf),
883 rem, fifo_size * i);
884 else
885 sg_set_page(sg, virt_to_page(xmit->buf),
886 size, fifo_size * i);
887 }
888
889 sg = priv->sg_tx_p;
890 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
891 if (!nent) {
892 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
893 return 0;
894 }
895 priv->nent = nent;
896
897 for (i = 0; i < nent; i++, sg++) {
898 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
899 fifo_size * i;
900 sg_dma_address(sg) = (sg_dma_address(sg) &
901 ~(UART_XMIT_SIZE - 1)) + sg->offset;
902 if (i == (nent - 1))
903 sg_dma_len(sg) = rem;
904 else
905 sg_dma_len(sg) = size;
906 }
907
908 desc = priv->chan_tx->device->device_prep_slave_sg(priv->chan_tx,
909 priv->sg_tx_p, nent, DMA_TO_DEVICE,
910 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
911 if (!desc) {
912 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n",
913 __func__);
914 return 0;
915 }
916 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
917 priv->desc_tx = desc;
918 desc->callback = pch_dma_tx_complete;
919 desc->callback_param = priv;
920
921 desc->tx_submit(desc);
922
923 dma_async_issue_pending(priv->chan_tx);
924
925 return PCH_UART_HANDLED_TX_INT;
926 }
927
928 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
929 {
930 u8 fcr = ioread8(priv->membase + UART_FCR);
931
932 /* Reset FIFO */
933 fcr |= UART_FCR_CLEAR_RCVR;
934 iowrite8(fcr, priv->membase + UART_FCR);
935
936 if (lsr & PCH_UART_LSR_ERR)
937 dev_err(&priv->pdev->dev, "Error data in FIFO\n");
938
939 if (lsr & UART_LSR_FE)
940 dev_err(&priv->pdev->dev, "Framing Error\n");
941
942 if (lsr & UART_LSR_PE)
943 dev_err(&priv->pdev->dev, "Parity Error\n");
944
945 if (lsr & UART_LSR_OE)
946 dev_err(&priv->pdev->dev, "Overrun Error\n");
947 }
948
949 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
950 {
951 struct eg20t_port *priv = dev_id;
952 unsigned int handled;
953 u8 lsr;
954 int ret = 0;
955 unsigned int iid;
956 unsigned long flags;
957
958 spin_lock_irqsave(&priv->port.lock, flags);
959 handled = 0;
960 while ((iid = pch_uart_hal_get_iid(priv)) > 1) {
961 switch (iid) {
962 case PCH_UART_IID_RLS: /* Receiver Line Status */
963 lsr = pch_uart_hal_get_line_status(priv);
964 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
965 UART_LSR_PE | UART_LSR_OE)) {
966 pch_uart_err_ir(priv, lsr);
967 ret = PCH_UART_HANDLED_RX_ERR_INT;
968 }
969 break;
970 case PCH_UART_IID_RDR: /* Received Data Ready */
971 if (priv->use_dma) {
972 pch_uart_hal_disable_interrupt(priv,
973 PCH_UART_HAL_RX_INT);
974 ret = dma_handle_rx(priv);
975 if (!ret)
976 pch_uart_hal_enable_interrupt(priv,
977 PCH_UART_HAL_RX_INT);
978 } else {
979 ret = handle_rx(priv);
980 }
981 break;
982 case PCH_UART_IID_RDR_TO: /* Received Data Ready
983 (FIFO Timeout) */
984 ret = handle_rx_to(priv);
985 break;
986 case PCH_UART_IID_THRE: /* Transmitter Holding Register
987 Empty */
988 if (priv->use_dma)
989 ret = dma_handle_tx(priv);
990 else
991 ret = handle_tx(priv);
992 break;
993 case PCH_UART_IID_MS: /* Modem Status */
994 ret = PCH_UART_HANDLED_MS_INT;
995 break;
996 default: /* Never junp to this label */
997 dev_err(priv->port.dev, "%s:iid=%d (%lu)\n", __func__,
998 iid, jiffies);
999 ret = -1;
1000 break;
1001 }
1002 handled |= (unsigned int)ret;
1003 }
1004 if (handled == 0 && iid <= 1) {
1005 if (priv->int_dis_flag)
1006 priv->int_dis_flag = 0;
1007 }
1008
1009 spin_unlock_irqrestore(&priv->port.lock, flags);
1010 return IRQ_RETVAL(handled);
1011 }
1012
1013 /* This function tests whether the transmitter fifo and shifter for the port
1014 described by 'port' is empty. */
1015 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1016 {
1017 struct eg20t_port *priv;
1018 int ret;
1019 priv = container_of(port, struct eg20t_port, port);
1020 if (priv->tx_empty)
1021 ret = TIOCSER_TEMT;
1022 else
1023 ret = 0;
1024
1025 return ret;
1026 }
1027
1028 /* Returns the current state of modem control inputs. */
1029 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1030 {
1031 struct eg20t_port *priv;
1032 u8 modem;
1033 unsigned int ret = 0;
1034
1035 priv = container_of(port, struct eg20t_port, port);
1036 modem = pch_uart_hal_get_modem(priv);
1037
1038 if (modem & UART_MSR_DCD)
1039 ret |= TIOCM_CAR;
1040
1041 if (modem & UART_MSR_RI)
1042 ret |= TIOCM_RNG;
1043
1044 if (modem & UART_MSR_DSR)
1045 ret |= TIOCM_DSR;
1046
1047 if (modem & UART_MSR_CTS)
1048 ret |= TIOCM_CTS;
1049
1050 return ret;
1051 }
1052
1053 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1054 {
1055 u32 mcr = 0;
1056 struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1057
1058 if (mctrl & TIOCM_DTR)
1059 mcr |= UART_MCR_DTR;
1060 if (mctrl & TIOCM_RTS)
1061 mcr |= UART_MCR_RTS;
1062 if (mctrl & TIOCM_LOOP)
1063 mcr |= UART_MCR_LOOP;
1064
1065 if (priv->mcr & UART_MCR_AFE)
1066 mcr |= UART_MCR_AFE;
1067
1068 if (mctrl)
1069 iowrite8(mcr, priv->membase + UART_MCR);
1070 }
1071
1072 static void pch_uart_stop_tx(struct uart_port *port)
1073 {
1074 struct eg20t_port *priv;
1075 priv = container_of(port, struct eg20t_port, port);
1076 priv->start_tx = 0;
1077 priv->tx_dma_use = 0;
1078 }
1079
1080 static void pch_uart_start_tx(struct uart_port *port)
1081 {
1082 struct eg20t_port *priv;
1083
1084 priv = container_of(port, struct eg20t_port, port);
1085
1086 if (priv->use_dma) {
1087 if (priv->tx_dma_use) {
1088 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1089 __func__);
1090 return;
1091 }
1092 }
1093
1094 priv->start_tx = 1;
1095 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1096 }
1097
1098 static void pch_uart_stop_rx(struct uart_port *port)
1099 {
1100 struct eg20t_port *priv;
1101 priv = container_of(port, struct eg20t_port, port);
1102 priv->start_rx = 0;
1103 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
1104 priv->int_dis_flag = 1;
1105 }
1106
1107 /* Enable the modem status interrupts. */
1108 static void pch_uart_enable_ms(struct uart_port *port)
1109 {
1110 struct eg20t_port *priv;
1111 priv = container_of(port, struct eg20t_port, port);
1112 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1113 }
1114
1115 /* Control the transmission of a break signal. */
1116 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1117 {
1118 struct eg20t_port *priv;
1119 unsigned long flags;
1120
1121 priv = container_of(port, struct eg20t_port, port);
1122 spin_lock_irqsave(&port->lock, flags);
1123 pch_uart_hal_set_break(priv, ctl);
1124 spin_unlock_irqrestore(&port->lock, flags);
1125 }
1126
1127 /* Grab any interrupt resources and initialise any low level driver state. */
1128 static int pch_uart_startup(struct uart_port *port)
1129 {
1130 struct eg20t_port *priv;
1131 int ret;
1132 int fifo_size;
1133 int trigger_level;
1134
1135 priv = container_of(port, struct eg20t_port, port);
1136 priv->tx_empty = 1;
1137
1138 if (port->uartclk)
1139 priv->base_baud = port->uartclk;
1140 else
1141 port->uartclk = priv->base_baud;
1142
1143 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1144 ret = pch_uart_hal_set_line(priv, default_baud,
1145 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1146 PCH_UART_HAL_STB1);
1147 if (ret)
1148 return ret;
1149
1150 switch (priv->fifo_size) {
1151 case 256:
1152 fifo_size = PCH_UART_HAL_FIFO256;
1153 break;
1154 case 64:
1155 fifo_size = PCH_UART_HAL_FIFO64;
1156 break;
1157 case 16:
1158 fifo_size = PCH_UART_HAL_FIFO16;
1159 case 1:
1160 default:
1161 fifo_size = PCH_UART_HAL_FIFO_DIS;
1162 break;
1163 }
1164
1165 switch (priv->trigger) {
1166 case PCH_UART_HAL_TRIGGER1:
1167 trigger_level = 1;
1168 break;
1169 case PCH_UART_HAL_TRIGGER_L:
1170 trigger_level = priv->fifo_size / 4;
1171 break;
1172 case PCH_UART_HAL_TRIGGER_M:
1173 trigger_level = priv->fifo_size / 2;
1174 break;
1175 case PCH_UART_HAL_TRIGGER_H:
1176 default:
1177 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1178 break;
1179 }
1180
1181 priv->trigger_level = trigger_level;
1182 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1183 fifo_size, priv->trigger);
1184 if (ret < 0)
1185 return ret;
1186
1187 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1188 KBUILD_MODNAME, priv);
1189 if (ret < 0)
1190 return ret;
1191
1192 if (priv->use_dma)
1193 pch_request_dma(port);
1194
1195 priv->start_rx = 1;
1196 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
1197 uart_update_timeout(port, CS8, default_baud);
1198
1199 return 0;
1200 }
1201
1202 static void pch_uart_shutdown(struct uart_port *port)
1203 {
1204 struct eg20t_port *priv;
1205 int ret;
1206
1207 priv = container_of(port, struct eg20t_port, port);
1208 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1209 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1210 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1211 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1212 if (ret)
1213 dev_err(priv->port.dev,
1214 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1215
1216 if (priv->use_dma_flag)
1217 pch_free_dma(port);
1218
1219 free_irq(priv->port.irq, priv);
1220 }
1221
1222 /* Change the port parameters, including word length, parity, stop
1223 *bits. Update read_status_mask and ignore_status_mask to indicate
1224 *the types of events we are interested in receiving. */
1225 static void pch_uart_set_termios(struct uart_port *port,
1226 struct ktermios *termios, struct ktermios *old)
1227 {
1228 int baud;
1229 int rtn;
1230 unsigned int parity, bits, stb;
1231 struct eg20t_port *priv;
1232 unsigned long flags;
1233
1234 priv = container_of(port, struct eg20t_port, port);
1235 switch (termios->c_cflag & CSIZE) {
1236 case CS5:
1237 bits = PCH_UART_HAL_5BIT;
1238 break;
1239 case CS6:
1240 bits = PCH_UART_HAL_6BIT;
1241 break;
1242 case CS7:
1243 bits = PCH_UART_HAL_7BIT;
1244 break;
1245 default: /* CS8 */
1246 bits = PCH_UART_HAL_8BIT;
1247 break;
1248 }
1249 if (termios->c_cflag & CSTOPB)
1250 stb = PCH_UART_HAL_STB2;
1251 else
1252 stb = PCH_UART_HAL_STB1;
1253
1254 if (termios->c_cflag & PARENB) {
1255 if (!(termios->c_cflag & PARODD))
1256 parity = PCH_UART_HAL_PARITY_ODD;
1257 else
1258 parity = PCH_UART_HAL_PARITY_EVEN;
1259
1260 } else {
1261 parity = PCH_UART_HAL_PARITY_NONE;
1262 }
1263
1264 /* Only UART0 has auto hardware flow function */
1265 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1266 priv->mcr |= UART_MCR_AFE;
1267 else
1268 priv->mcr &= ~UART_MCR_AFE;
1269
1270 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1271
1272 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1273
1274 spin_lock_irqsave(&port->lock, flags);
1275
1276 uart_update_timeout(port, termios->c_cflag, baud);
1277 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1278 if (rtn)
1279 goto out;
1280
1281 /* Don't rewrite B0 */
1282 if (tty_termios_baud_rate(termios))
1283 tty_termios_encode_baud_rate(termios, baud, baud);
1284
1285 out:
1286 spin_unlock_irqrestore(&port->lock, flags);
1287 }
1288
1289 static const char *pch_uart_type(struct uart_port *port)
1290 {
1291 return KBUILD_MODNAME;
1292 }
1293
1294 static void pch_uart_release_port(struct uart_port *port)
1295 {
1296 struct eg20t_port *priv;
1297
1298 priv = container_of(port, struct eg20t_port, port);
1299 pci_iounmap(priv->pdev, priv->membase);
1300 pci_release_regions(priv->pdev);
1301 }
1302
1303 static int pch_uart_request_port(struct uart_port *port)
1304 {
1305 struct eg20t_port *priv;
1306 int ret;
1307 void __iomem *membase;
1308
1309 priv = container_of(port, struct eg20t_port, port);
1310 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1311 if (ret < 0)
1312 return -EBUSY;
1313
1314 membase = pci_iomap(priv->pdev, 1, 0);
1315 if (!membase) {
1316 pci_release_regions(priv->pdev);
1317 return -EBUSY;
1318 }
1319 priv->membase = port->membase = membase;
1320
1321 return 0;
1322 }
1323
1324 static void pch_uart_config_port(struct uart_port *port, int type)
1325 {
1326 struct eg20t_port *priv;
1327
1328 priv = container_of(port, struct eg20t_port, port);
1329 if (type & UART_CONFIG_TYPE) {
1330 port->type = priv->port_type;
1331 pch_uart_request_port(port);
1332 }
1333 }
1334
1335 static int pch_uart_verify_port(struct uart_port *port,
1336 struct serial_struct *serinfo)
1337 {
1338 struct eg20t_port *priv;
1339
1340 priv = container_of(port, struct eg20t_port, port);
1341 if (serinfo->flags & UPF_LOW_LATENCY) {
1342 dev_info(priv->port.dev,
1343 "PCH UART : Use PIO Mode (without DMA)\n");
1344 priv->use_dma = 0;
1345 serinfo->flags &= ~UPF_LOW_LATENCY;
1346 } else {
1347 #ifndef CONFIG_PCH_DMA
1348 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1349 __func__);
1350 return -EOPNOTSUPP;
1351 #endif
1352 priv->use_dma = 1;
1353 priv->use_dma_flag = 1;
1354 dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n");
1355 }
1356
1357 return 0;
1358 }
1359
1360 static struct uart_ops pch_uart_ops = {
1361 .tx_empty = pch_uart_tx_empty,
1362 .set_mctrl = pch_uart_set_mctrl,
1363 .get_mctrl = pch_uart_get_mctrl,
1364 .stop_tx = pch_uart_stop_tx,
1365 .start_tx = pch_uart_start_tx,
1366 .stop_rx = pch_uart_stop_rx,
1367 .enable_ms = pch_uart_enable_ms,
1368 .break_ctl = pch_uart_break_ctl,
1369 .startup = pch_uart_startup,
1370 .shutdown = pch_uart_shutdown,
1371 .set_termios = pch_uart_set_termios,
1372 /* .pm = pch_uart_pm, Not supported yet */
1373 /* .set_wake = pch_uart_set_wake, Not supported yet */
1374 .type = pch_uart_type,
1375 .release_port = pch_uart_release_port,
1376 .request_port = pch_uart_request_port,
1377 .config_port = pch_uart_config_port,
1378 .verify_port = pch_uart_verify_port
1379 };
1380
1381 static struct uart_driver pch_uart_driver = {
1382 .owner = THIS_MODULE,
1383 .driver_name = KBUILD_MODNAME,
1384 .dev_name = PCH_UART_DRIVER_DEVICE,
1385 .major = 0,
1386 .minor = 0,
1387 .nr = PCH_UART_NR,
1388 };
1389
1390 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1391 const struct pci_device_id *id)
1392 {
1393 struct eg20t_port *priv;
1394 int ret;
1395 unsigned int iobase;
1396 unsigned int mapbase;
1397 unsigned char *rxbuf;
1398 int fifosize, base_baud;
1399 int port_type;
1400 struct pch_uart_driver_data *board;
1401 const char *board_name;
1402
1403 board = &drv_dat[id->driver_data];
1404 port_type = board->port_type;
1405
1406 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1407 if (priv == NULL)
1408 goto init_port_alloc_err;
1409
1410 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1411 if (!rxbuf)
1412 goto init_port_free_txbuf;
1413
1414 base_baud = 1843200; /* 1.8432MHz */
1415
1416 /* quirk for CM-iTC board */
1417 board_name = dmi_get_system_info(DMI_BOARD_NAME);
1418 if (board_name && strstr(board_name, "CM-iTC"))
1419 base_baud = 192000000; /* 192.0MHz */
1420
1421 switch (port_type) {
1422 case PORT_UNKNOWN:
1423 fifosize = 256; /* EG20T/ML7213: UART0 */
1424 break;
1425 case PORT_8250:
1426 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/
1427 break;
1428 default:
1429 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1430 goto init_port_hal_free;
1431 }
1432
1433 pci_enable_msi(pdev);
1434
1435 iobase = pci_resource_start(pdev, 0);
1436 mapbase = pci_resource_start(pdev, 1);
1437 priv->mapbase = mapbase;
1438 priv->iobase = iobase;
1439 priv->pdev = pdev;
1440 priv->tx_empty = 1;
1441 priv->rxbuf.buf = rxbuf;
1442 priv->rxbuf.size = PAGE_SIZE;
1443
1444 priv->fifo_size = fifosize;
1445 priv->base_baud = base_baud;
1446 priv->port_type = PORT_MAX_8250 + port_type + 1;
1447 priv->port.dev = &pdev->dev;
1448 priv->port.iobase = iobase;
1449 priv->port.membase = NULL;
1450 priv->port.mapbase = mapbase;
1451 priv->port.irq = pdev->irq;
1452 priv->port.iotype = UPIO_PORT;
1453 priv->port.ops = &pch_uart_ops;
1454 priv->port.flags = UPF_BOOT_AUTOCONF;
1455 priv->port.fifosize = fifosize;
1456 priv->port.line = board->line_no;
1457 priv->trigger = PCH_UART_HAL_TRIGGER_M;
1458
1459 spin_lock_init(&priv->port.lock);
1460
1461 pci_set_drvdata(pdev, priv);
1462 pch_uart_hal_request(pdev, fifosize, base_baud);
1463
1464 ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1465 if (ret < 0)
1466 goto init_port_hal_free;
1467
1468 return priv;
1469
1470 init_port_hal_free:
1471 free_page((unsigned long)rxbuf);
1472 init_port_free_txbuf:
1473 kfree(priv);
1474 init_port_alloc_err:
1475
1476 return NULL;
1477 }
1478
1479 static void pch_uart_exit_port(struct eg20t_port *priv)
1480 {
1481 uart_remove_one_port(&pch_uart_driver, &priv->port);
1482 pci_set_drvdata(priv->pdev, NULL);
1483 free_page((unsigned long)priv->rxbuf.buf);
1484 }
1485
1486 static void pch_uart_pci_remove(struct pci_dev *pdev)
1487 {
1488 struct eg20t_port *priv;
1489
1490 priv = (struct eg20t_port *)pci_get_drvdata(pdev);
1491
1492 pci_disable_msi(pdev);
1493 pch_uart_exit_port(priv);
1494 pci_disable_device(pdev);
1495 kfree(priv);
1496 return;
1497 }
1498 #ifdef CONFIG_PM
1499 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1500 {
1501 struct eg20t_port *priv = pci_get_drvdata(pdev);
1502
1503 uart_suspend_port(&pch_uart_driver, &priv->port);
1504
1505 pci_save_state(pdev);
1506 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1507 return 0;
1508 }
1509
1510 static int pch_uart_pci_resume(struct pci_dev *pdev)
1511 {
1512 struct eg20t_port *priv = pci_get_drvdata(pdev);
1513 int ret;
1514
1515 pci_set_power_state(pdev, PCI_D0);
1516 pci_restore_state(pdev);
1517
1518 ret = pci_enable_device(pdev);
1519 if (ret) {
1520 dev_err(&pdev->dev,
1521 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1522 return ret;
1523 }
1524
1525 uart_resume_port(&pch_uart_driver, &priv->port);
1526
1527 return 0;
1528 }
1529 #else
1530 #define pch_uart_pci_suspend NULL
1531 #define pch_uart_pci_resume NULL
1532 #endif
1533
1534 static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = {
1535 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1536 .driver_data = pch_et20t_uart0},
1537 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1538 .driver_data = pch_et20t_uart1},
1539 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1540 .driver_data = pch_et20t_uart2},
1541 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1542 .driver_data = pch_et20t_uart3},
1543 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1544 .driver_data = pch_ml7213_uart0},
1545 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1546 .driver_data = pch_ml7213_uart1},
1547 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1548 .driver_data = pch_ml7213_uart2},
1549 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1550 .driver_data = pch_ml7223_uart0},
1551 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1552 .driver_data = pch_ml7223_uart1},
1553 {0,},
1554 };
1555
1556 static int __devinit pch_uart_pci_probe(struct pci_dev *pdev,
1557 const struct pci_device_id *id)
1558 {
1559 int ret;
1560 struct eg20t_port *priv;
1561
1562 ret = pci_enable_device(pdev);
1563 if (ret < 0)
1564 goto probe_error;
1565
1566 priv = pch_uart_init_port(pdev, id);
1567 if (!priv) {
1568 ret = -EBUSY;
1569 goto probe_disable_device;
1570 }
1571 pci_set_drvdata(pdev, priv);
1572
1573 return ret;
1574
1575 probe_disable_device:
1576 pci_disable_msi(pdev);
1577 pci_disable_device(pdev);
1578 probe_error:
1579 return ret;
1580 }
1581
1582 static struct pci_driver pch_uart_pci_driver = {
1583 .name = "pch_uart",
1584 .id_table = pch_uart_pci_id,
1585 .probe = pch_uart_pci_probe,
1586 .remove = __devexit_p(pch_uart_pci_remove),
1587 .suspend = pch_uart_pci_suspend,
1588 .resume = pch_uart_pci_resume,
1589 };
1590
1591 static int __init pch_uart_module_init(void)
1592 {
1593 int ret;
1594
1595 /* register as UART driver */
1596 ret = uart_register_driver(&pch_uart_driver);
1597 if (ret < 0)
1598 return ret;
1599
1600 /* register as PCI driver */
1601 ret = pci_register_driver(&pch_uart_pci_driver);
1602 if (ret < 0)
1603 uart_unregister_driver(&pch_uart_driver);
1604
1605 return ret;
1606 }
1607 module_init(pch_uart_module_init);
1608
1609 static void __exit pch_uart_module_exit(void)
1610 {
1611 pci_unregister_driver(&pch_uart_pci_driver);
1612 uart_unregister_driver(&pch_uart_driver);
1613 }
1614 module_exit(pch_uart_module_exit);
1615
1616 MODULE_LICENSE("GPL v2");
1617 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1618 module_param(default_baud, uint, S_IRUGO);
linux-next