Add linux-next specific files for 20110831
[linux-2.6/next.git] / drivers / usb / gadget / s3c-hsudc.c
blob25829b4398da9b2f28a591bb03952e02124da660
1 /* linux/drivers/usb/gadget/s3c-hsudc.c
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
6 * S3C24XX USB 2.0 High-speed USB controller gadget driver
8 * The S3C24XX USB 2.0 high-speed USB controller supports upto 9 endpoints.
9 * Each endpoint can be configured as either in or out endpoint. Endpoints
10 * can be configured for Bulk or Interrupt transfer mode.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/spinlock.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/delay.h>
24 #include <linux/io.h>
25 #include <linux/slab.h>
26 #include <linux/clk.h>
27 #include <linux/usb/ch9.h>
28 #include <linux/usb/gadget.h>
29 #include <linux/usb/otg.h>
30 #include <linux/prefetch.h>
32 #include <mach/regs-s3c2443-clock.h>
33 #include <plat/udc.h>
35 #define S3C_HSUDC_REG(x) (x)
37 /* Non-Indexed Registers */
38 #define S3C_IR S3C_HSUDC_REG(0x00) /* Index Register */
39 #define S3C_EIR S3C_HSUDC_REG(0x04) /* EP Intr Status */
40 #define S3C_EIR_EP0 (1<<0)
41 #define S3C_EIER S3C_HSUDC_REG(0x08) /* EP Intr Enable */
42 #define S3C_FAR S3C_HSUDC_REG(0x0c) /* Gadget Address */
43 #define S3C_FNR S3C_HSUDC_REG(0x10) /* Frame Number */
44 #define S3C_EDR S3C_HSUDC_REG(0x14) /* EP Direction */
45 #define S3C_TR S3C_HSUDC_REG(0x18) /* Test Register */
46 #define S3C_SSR S3C_HSUDC_REG(0x1c) /* System Status */
47 #define S3C_SSR_DTZIEN_EN (0xff8f)
48 #define S3C_SSR_ERR (0xff80)
49 #define S3C_SSR_VBUSON (1 << 8)
50 #define S3C_SSR_HSP (1 << 4)
51 #define S3C_SSR_SDE (1 << 3)
52 #define S3C_SSR_RESUME (1 << 2)
53 #define S3C_SSR_SUSPEND (1 << 1)
54 #define S3C_SSR_RESET (1 << 0)
55 #define S3C_SCR S3C_HSUDC_REG(0x20) /* System Control */
56 #define S3C_SCR_DTZIEN_EN (1 << 14)
57 #define S3C_SCR_RRD_EN (1 << 5)
58 #define S3C_SCR_SUS_EN (1 << 1)
59 #define S3C_SCR_RST_EN (1 << 0)
60 #define S3C_EP0SR S3C_HSUDC_REG(0x24) /* EP0 Status */
61 #define S3C_EP0SR_EP0_LWO (1 << 6)
62 #define S3C_EP0SR_STALL (1 << 4)
63 #define S3C_EP0SR_TX_SUCCESS (1 << 1)
64 #define S3C_EP0SR_RX_SUCCESS (1 << 0)
65 #define S3C_EP0CR S3C_HSUDC_REG(0x28) /* EP0 Control */
66 #define S3C_BR(_x) S3C_HSUDC_REG(0x60 + (_x * 4))
68 /* Indexed Registers */
69 #define S3C_ESR S3C_HSUDC_REG(0x2c) /* EPn Status */
70 #define S3C_ESR_FLUSH (1 << 6)
71 #define S3C_ESR_STALL (1 << 5)
72 #define S3C_ESR_LWO (1 << 4)
73 #define S3C_ESR_PSIF_ONE (1 << 2)
74 #define S3C_ESR_PSIF_TWO (2 << 2)
75 #define S3C_ESR_TX_SUCCESS (1 << 1)
76 #define S3C_ESR_RX_SUCCESS (1 << 0)
77 #define S3C_ECR S3C_HSUDC_REG(0x30) /* EPn Control */
78 #define S3C_ECR_DUEN (1 << 7)
79 #define S3C_ECR_FLUSH (1 << 6)
80 #define S3C_ECR_STALL (1 << 1)
81 #define S3C_ECR_IEMS (1 << 0)
82 #define S3C_BRCR S3C_HSUDC_REG(0x34) /* Read Count */
83 #define S3C_BWCR S3C_HSUDC_REG(0x38) /* Write Count */
84 #define S3C_MPR S3C_HSUDC_REG(0x3c) /* Max Pkt Size */
86 #define WAIT_FOR_SETUP (0)
87 #define DATA_STATE_XMIT (1)
88 #define DATA_STATE_RECV (2)
90 /**
91 * struct s3c_hsudc_ep - Endpoint representation used by driver.
92 * @ep: USB gadget layer representation of device endpoint.
93 * @name: Endpoint name (as required by ep autoconfiguration).
94 * @dev: Reference to the device controller to which this EP belongs.
95 * @desc: Endpoint descriptor obtained from the gadget driver.
96 * @queue: Transfer request queue for the endpoint.
97 * @stopped: Maintains state of endpoint, set if EP is halted.
98 * @bEndpointAddress: EP address (including direction bit).
99 * @fifo: Base address of EP FIFO.
101 struct s3c_hsudc_ep {
102 struct usb_ep ep;
103 char name[20];
104 struct s3c_hsudc *dev;
105 const struct usb_endpoint_descriptor *desc;
106 struct list_head queue;
107 u8 stopped;
108 u8 wedge;
109 u8 bEndpointAddress;
110 void __iomem *fifo;
114 * struct s3c_hsudc_req - Driver encapsulation of USB gadget transfer request.
115 * @req: Reference to USB gadget transfer request.
116 * @queue: Used for inserting this request to the endpoint request queue.
118 struct s3c_hsudc_req {
119 struct usb_request req;
120 struct list_head queue;
124 * struct s3c_hsudc - Driver's abstraction of the device controller.
125 * @gadget: Instance of usb_gadget which is referenced by gadget driver.
126 * @driver: Reference to currenty active gadget driver.
127 * @dev: The device reference used by probe function.
128 * @lock: Lock to synchronize the usage of Endpoints (EP's are indexed).
129 * @regs: Remapped base address of controller's register space.
130 * @mem_rsrc: Device memory resource used for remapping device register space.
131 * irq: IRQ number used by the controller.
132 * uclk: Reference to the controller clock.
133 * ep0state: Current state of EP0.
134 * ep: List of endpoints supported by the controller.
136 struct s3c_hsudc {
137 struct usb_gadget gadget;
138 struct usb_gadget_driver *driver;
139 struct device *dev;
140 struct s3c24xx_hsudc_platdata *pd;
141 struct otg_transceiver *transceiver;
142 spinlock_t lock;
143 void __iomem *regs;
144 struct resource *mem_rsrc;
145 int irq;
146 struct clk *uclk;
147 int ep0state;
148 struct s3c_hsudc_ep ep[];
151 #define ep_maxpacket(_ep) ((_ep)->ep.maxpacket)
152 #define ep_is_in(_ep) ((_ep)->bEndpointAddress & USB_DIR_IN)
153 #define ep_index(_ep) ((_ep)->bEndpointAddress & \
154 USB_ENDPOINT_NUMBER_MASK)
156 static struct s3c_hsudc *the_controller;
157 static const char driver_name[] = "s3c-udc";
158 static const char ep0name[] = "ep0-control";
160 static inline struct s3c_hsudc_req *our_req(struct usb_request *req)
162 return container_of(req, struct s3c_hsudc_req, req);
165 static inline struct s3c_hsudc_ep *our_ep(struct usb_ep *ep)
167 return container_of(ep, struct s3c_hsudc_ep, ep);
170 static inline struct s3c_hsudc *to_hsudc(struct usb_gadget *gadget)
172 return container_of(gadget, struct s3c_hsudc, gadget);
175 static inline void set_index(struct s3c_hsudc *hsudc, int ep_addr)
177 ep_addr &= USB_ENDPOINT_NUMBER_MASK;
178 writel(ep_addr, hsudc->regs + S3C_IR);
181 static inline void __orr32(void __iomem *ptr, u32 val)
183 writel(readl(ptr) | val, ptr);
186 static void s3c_hsudc_init_phy(void)
188 u32 cfg;
190 cfg = readl(S3C2443_PWRCFG) | S3C2443_PWRCFG_USBPHY;
191 writel(cfg, S3C2443_PWRCFG);
193 cfg = readl(S3C2443_URSTCON);
194 cfg |= (S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST);
195 writel(cfg, S3C2443_URSTCON);
196 mdelay(1);
198 cfg = readl(S3C2443_URSTCON);
199 cfg &= ~(S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST);
200 writel(cfg, S3C2443_URSTCON);
202 cfg = readl(S3C2443_PHYCTRL);
203 cfg &= ~(S3C2443_PHYCTRL_CLKSEL | S3C2443_PHYCTRL_DSPORT);
204 cfg |= (S3C2443_PHYCTRL_EXTCLK | S3C2443_PHYCTRL_PLLSEL);
205 writel(cfg, S3C2443_PHYCTRL);
207 cfg = readl(S3C2443_PHYPWR);
208 cfg &= ~(S3C2443_PHYPWR_FSUSPEND | S3C2443_PHYPWR_PLL_PWRDN |
209 S3C2443_PHYPWR_XO_ON | S3C2443_PHYPWR_PLL_REFCLK |
210 S3C2443_PHYPWR_ANALOG_PD);
211 cfg |= S3C2443_PHYPWR_COMMON_ON;
212 writel(cfg, S3C2443_PHYPWR);
214 cfg = readl(S3C2443_UCLKCON);
215 cfg |= (S3C2443_UCLKCON_DETECT_VBUS | S3C2443_UCLKCON_FUNC_CLKEN |
216 S3C2443_UCLKCON_TCLKEN);
217 writel(cfg, S3C2443_UCLKCON);
220 static void s3c_hsudc_uninit_phy(void)
222 u32 cfg;
224 cfg = readl(S3C2443_PWRCFG) & ~S3C2443_PWRCFG_USBPHY;
225 writel(cfg, S3C2443_PWRCFG);
227 writel(S3C2443_PHYPWR_FSUSPEND, S3C2443_PHYPWR);
229 cfg = readl(S3C2443_UCLKCON) & ~S3C2443_UCLKCON_FUNC_CLKEN;
230 writel(cfg, S3C2443_UCLKCON);
234 * s3c_hsudc_complete_request - Complete a transfer request.
235 * @hsep: Endpoint to which the request belongs.
236 * @hsreq: Transfer request to be completed.
237 * @status: Transfer completion status for the transfer request.
239 static void s3c_hsudc_complete_request(struct s3c_hsudc_ep *hsep,
240 struct s3c_hsudc_req *hsreq, int status)
242 unsigned int stopped = hsep->stopped;
243 struct s3c_hsudc *hsudc = hsep->dev;
245 list_del_init(&hsreq->queue);
246 hsreq->req.status = status;
248 if (!ep_index(hsep)) {
249 hsudc->ep0state = WAIT_FOR_SETUP;
250 hsep->bEndpointAddress &= ~USB_DIR_IN;
253 hsep->stopped = 1;
254 spin_unlock(&hsudc->lock);
255 if (hsreq->req.complete != NULL)
256 hsreq->req.complete(&hsep->ep, &hsreq->req);
257 spin_lock(&hsudc->lock);
258 hsep->stopped = stopped;
262 * s3c_hsudc_nuke_ep - Terminate all requests queued for a endpoint.
263 * @hsep: Endpoint for which queued requests have to be terminated.
264 * @status: Transfer completion status for the transfer request.
266 static void s3c_hsudc_nuke_ep(struct s3c_hsudc_ep *hsep, int status)
268 struct s3c_hsudc_req *hsreq;
270 while (!list_empty(&hsep->queue)) {
271 hsreq = list_entry(hsep->queue.next,
272 struct s3c_hsudc_req, queue);
273 s3c_hsudc_complete_request(hsep, hsreq, status);
278 * s3c_hsudc_stop_activity - Stop activity on all endpoints.
279 * @hsudc: Device controller for which EP activity is to be stopped.
280 * @driver: Reference to the gadget driver which is currently active.
282 * All the endpoints are stopped and any pending transfer requests if any on
283 * the endpoint are terminated.
285 static void s3c_hsudc_stop_activity(struct s3c_hsudc *hsudc,
286 struct usb_gadget_driver *driver)
288 struct s3c_hsudc_ep *hsep;
289 int epnum;
291 hsudc->gadget.speed = USB_SPEED_UNKNOWN;
293 for (epnum = 0; epnum < hsudc->pd->epnum; epnum++) {
294 hsep = &hsudc->ep[epnum];
295 hsep->stopped = 1;
296 s3c_hsudc_nuke_ep(hsep, -ESHUTDOWN);
299 spin_unlock(&hsudc->lock);
300 driver->disconnect(&hsudc->gadget);
301 spin_lock(&hsudc->lock);
305 * s3c_hsudc_read_setup_pkt - Read the received setup packet from EP0 fifo.
306 * @hsudc: Device controller from which setup packet is to be read.
307 * @buf: The buffer into which the setup packet is read.
309 * The setup packet received in the EP0 fifo is read and stored into a
310 * given buffer address.
313 static void s3c_hsudc_read_setup_pkt(struct s3c_hsudc *hsudc, u16 *buf)
315 int count;
317 count = readl(hsudc->regs + S3C_BRCR);
318 while (count--)
319 *buf++ = (u16)readl(hsudc->regs + S3C_BR(0));
321 writel(S3C_EP0SR_RX_SUCCESS, hsudc->regs + S3C_EP0SR);
325 * s3c_hsudc_write_fifo - Write next chunk of transfer data to EP fifo.
326 * @hsep: Endpoint to which the data is to be written.
327 * @hsreq: Transfer request from which the next chunk of data is written.
329 * Write the next chunk of data from a transfer request to the endpoint FIFO.
330 * If the transfer request completes, 1 is returned, otherwise 0 is returned.
332 static int s3c_hsudc_write_fifo(struct s3c_hsudc_ep *hsep,
333 struct s3c_hsudc_req *hsreq)
335 u16 *buf;
336 u32 max = ep_maxpacket(hsep);
337 u32 count, length;
338 bool is_last;
339 void __iomem *fifo = hsep->fifo;
341 buf = hsreq->req.buf + hsreq->req.actual;
342 prefetch(buf);
344 length = hsreq->req.length - hsreq->req.actual;
345 length = min(length, max);
346 hsreq->req.actual += length;
348 writel(length, hsep->dev->regs + S3C_BWCR);
349 for (count = 0; count < length; count += 2)
350 writel(*buf++, fifo);
352 if (count != max) {
353 is_last = true;
354 } else {
355 if (hsreq->req.length != hsreq->req.actual || hsreq->req.zero)
356 is_last = false;
357 else
358 is_last = true;
361 if (is_last) {
362 s3c_hsudc_complete_request(hsep, hsreq, 0);
363 return 1;
366 return 0;
370 * s3c_hsudc_read_fifo - Read the next chunk of data from EP fifo.
371 * @hsep: Endpoint from which the data is to be read.
372 * @hsreq: Transfer request to which the next chunk of data read is written.
374 * Read the next chunk of data from the endpoint FIFO and a write it to the
375 * transfer request buffer. If the transfer request completes, 1 is returned,
376 * otherwise 0 is returned.
378 static int s3c_hsudc_read_fifo(struct s3c_hsudc_ep *hsep,
379 struct s3c_hsudc_req *hsreq)
381 struct s3c_hsudc *hsudc = hsep->dev;
382 u32 csr, offset;
383 u16 *buf, word;
384 u32 buflen, rcnt, rlen;
385 void __iomem *fifo = hsep->fifo;
386 u32 is_short = 0;
388 offset = (ep_index(hsep)) ? S3C_ESR : S3C_EP0SR;
389 csr = readl(hsudc->regs + offset);
390 if (!(csr & S3C_ESR_RX_SUCCESS))
391 return -EINVAL;
393 buf = hsreq->req.buf + hsreq->req.actual;
394 prefetchw(buf);
395 buflen = hsreq->req.length - hsreq->req.actual;
397 rcnt = readl(hsudc->regs + S3C_BRCR);
398 rlen = (csr & S3C_ESR_LWO) ? (rcnt * 2 - 1) : (rcnt * 2);
400 hsreq->req.actual += min(rlen, buflen);
401 is_short = (rlen < hsep->ep.maxpacket);
403 while (rcnt-- != 0) {
404 word = (u16)readl(fifo);
405 if (buflen) {
406 *buf++ = word;
407 buflen--;
408 } else {
409 hsreq->req.status = -EOVERFLOW;
413 writel(S3C_ESR_RX_SUCCESS, hsudc->regs + offset);
415 if (is_short || hsreq->req.actual == hsreq->req.length) {
416 s3c_hsudc_complete_request(hsep, hsreq, 0);
417 return 1;
420 return 0;
424 * s3c_hsudc_epin_intr - Handle in-endpoint interrupt.
425 * @hsudc - Device controller for which the interrupt is to be handled.
426 * @ep_idx - Endpoint number on which an interrupt is pending.
428 * Handles interrupt for a in-endpoint. The interrupts that are handled are
429 * stall and data transmit complete interrupt.
431 static void s3c_hsudc_epin_intr(struct s3c_hsudc *hsudc, u32 ep_idx)
433 struct s3c_hsudc_ep *hsep = &hsudc->ep[ep_idx];
434 struct s3c_hsudc_req *hsreq;
435 u32 csr;
437 csr = readl((u32)hsudc->regs + S3C_ESR);
438 if (csr & S3C_ESR_STALL) {
439 writel(S3C_ESR_STALL, hsudc->regs + S3C_ESR);
440 return;
443 if (csr & S3C_ESR_TX_SUCCESS) {
444 writel(S3C_ESR_TX_SUCCESS, hsudc->regs + S3C_ESR);
445 if (list_empty(&hsep->queue))
446 return;
448 hsreq = list_entry(hsep->queue.next,
449 struct s3c_hsudc_req, queue);
450 if ((s3c_hsudc_write_fifo(hsep, hsreq) == 0) &&
451 (csr & S3C_ESR_PSIF_TWO))
452 s3c_hsudc_write_fifo(hsep, hsreq);
457 * s3c_hsudc_epout_intr - Handle out-endpoint interrupt.
458 * @hsudc - Device controller for which the interrupt is to be handled.
459 * @ep_idx - Endpoint number on which an interrupt is pending.
461 * Handles interrupt for a out-endpoint. The interrupts that are handled are
462 * stall, flush and data ready interrupt.
464 static void s3c_hsudc_epout_intr(struct s3c_hsudc *hsudc, u32 ep_idx)
466 struct s3c_hsudc_ep *hsep = &hsudc->ep[ep_idx];
467 struct s3c_hsudc_req *hsreq;
468 u32 csr;
470 csr = readl((u32)hsudc->regs + S3C_ESR);
471 if (csr & S3C_ESR_STALL) {
472 writel(S3C_ESR_STALL, hsudc->regs + S3C_ESR);
473 return;
476 if (csr & S3C_ESR_FLUSH) {
477 __orr32(hsudc->regs + S3C_ECR, S3C_ECR_FLUSH);
478 return;
481 if (csr & S3C_ESR_RX_SUCCESS) {
482 if (list_empty(&hsep->queue))
483 return;
485 hsreq = list_entry(hsep->queue.next,
486 struct s3c_hsudc_req, queue);
487 if (((s3c_hsudc_read_fifo(hsep, hsreq)) == 0) &&
488 (csr & S3C_ESR_PSIF_TWO))
489 s3c_hsudc_read_fifo(hsep, hsreq);
493 /** s3c_hsudc_set_halt - Set or clear a endpoint halt.
494 * @_ep: Endpoint on which halt has to be set or cleared.
495 * @value: 1 for setting halt on endpoint, 0 to clear halt.
497 * Set or clear endpoint halt. If halt is set, the endpoint is stopped.
498 * If halt is cleared, for in-endpoints, if there are any pending
499 * transfer requests, transfers are started.
501 static int s3c_hsudc_set_halt(struct usb_ep *_ep, int value)
503 struct s3c_hsudc_ep *hsep = our_ep(_ep);
504 struct s3c_hsudc *hsudc = hsep->dev;
505 struct s3c_hsudc_req *hsreq;
506 unsigned long irqflags;
507 u32 ecr;
508 u32 offset;
510 if (value && ep_is_in(hsep) && !list_empty(&hsep->queue))
511 return -EAGAIN;
513 spin_lock_irqsave(&hsudc->lock, irqflags);
514 set_index(hsudc, ep_index(hsep));
515 offset = (ep_index(hsep)) ? S3C_ECR : S3C_EP0CR;
516 ecr = readl(hsudc->regs + offset);
518 if (value) {
519 ecr |= S3C_ECR_STALL;
520 if (ep_index(hsep))
521 ecr |= S3C_ECR_FLUSH;
522 hsep->stopped = 1;
523 } else {
524 ecr &= ~S3C_ECR_STALL;
525 hsep->stopped = hsep->wedge = 0;
527 writel(ecr, hsudc->regs + offset);
529 if (ep_is_in(hsep) && !list_empty(&hsep->queue) && !value) {
530 hsreq = list_entry(hsep->queue.next,
531 struct s3c_hsudc_req, queue);
532 if (hsreq)
533 s3c_hsudc_write_fifo(hsep, hsreq);
536 spin_unlock_irqrestore(&hsudc->lock, irqflags);
537 return 0;
540 /** s3c_hsudc_set_wedge - Sets the halt feature with the clear requests ignored
541 * @_ep: Endpoint on which wedge has to be set.
543 * Sets the halt feature with the clear requests ignored.
545 static int s3c_hsudc_set_wedge(struct usb_ep *_ep)
547 struct s3c_hsudc_ep *hsep = our_ep(_ep);
549 if (!hsep)
550 return -EINVAL;
552 hsep->wedge = 1;
553 return usb_ep_set_halt(_ep);
556 /** s3c_hsudc_handle_reqfeat - Handle set feature or clear feature requests.
557 * @_ep: Device controller on which the set/clear feature needs to be handled.
558 * @ctrl: Control request as received on the endpoint 0.
560 * Handle set feature or clear feature control requests on the control endpoint.
562 static int s3c_hsudc_handle_reqfeat(struct s3c_hsudc *hsudc,
563 struct usb_ctrlrequest *ctrl)
565 struct s3c_hsudc_ep *hsep;
566 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
567 u8 ep_num = ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK;
569 if (ctrl->bRequestType == USB_RECIP_ENDPOINT) {
570 hsep = &hsudc->ep[ep_num];
571 switch (le16_to_cpu(ctrl->wValue)) {
572 case USB_ENDPOINT_HALT:
573 if (set || (!set && !hsep->wedge))
574 s3c_hsudc_set_halt(&hsep->ep, set);
575 return 0;
579 return -ENOENT;
583 * s3c_hsudc_process_req_status - Handle get status control request.
584 * @hsudc: Device controller on which get status request has be handled.
585 * @ctrl: Control request as received on the endpoint 0.
587 * Handle get status control request received on control endpoint.
589 static void s3c_hsudc_process_req_status(struct s3c_hsudc *hsudc,
590 struct usb_ctrlrequest *ctrl)
592 struct s3c_hsudc_ep *hsep0 = &hsudc->ep[0];
593 struct s3c_hsudc_req hsreq;
594 struct s3c_hsudc_ep *hsep;
595 __le16 reply;
596 u8 epnum;
598 switch (ctrl->bRequestType & USB_RECIP_MASK) {
599 case USB_RECIP_DEVICE:
600 reply = cpu_to_le16(0);
601 break;
603 case USB_RECIP_INTERFACE:
604 reply = cpu_to_le16(0);
605 break;
607 case USB_RECIP_ENDPOINT:
608 epnum = le16_to_cpu(ctrl->wIndex) & USB_ENDPOINT_NUMBER_MASK;
609 hsep = &hsudc->ep[epnum];
610 reply = cpu_to_le16(hsep->stopped ? 1 : 0);
611 break;
614 INIT_LIST_HEAD(&hsreq.queue);
615 hsreq.req.length = 2;
616 hsreq.req.buf = &reply;
617 hsreq.req.actual = 0;
618 hsreq.req.complete = NULL;
619 s3c_hsudc_write_fifo(hsep0, &hsreq);
623 * s3c_hsudc_process_setup - Process control request received on endpoint 0.
624 * @hsudc: Device controller on which control request has been received.
626 * Read the control request received on endpoint 0, decode it and handle
627 * the request.
629 static void s3c_hsudc_process_setup(struct s3c_hsudc *hsudc)
631 struct s3c_hsudc_ep *hsep = &hsudc->ep[0];
632 struct usb_ctrlrequest ctrl = {0};
633 int ret;
635 s3c_hsudc_nuke_ep(hsep, -EPROTO);
636 s3c_hsudc_read_setup_pkt(hsudc, (u16 *)&ctrl);
638 if (ctrl.bRequestType & USB_DIR_IN) {
639 hsep->bEndpointAddress |= USB_DIR_IN;
640 hsudc->ep0state = DATA_STATE_XMIT;
641 } else {
642 hsep->bEndpointAddress &= ~USB_DIR_IN;
643 hsudc->ep0state = DATA_STATE_RECV;
646 switch (ctrl.bRequest) {
647 case USB_REQ_SET_ADDRESS:
648 if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
649 break;
650 hsudc->ep0state = WAIT_FOR_SETUP;
651 return;
653 case USB_REQ_GET_STATUS:
654 if ((ctrl.bRequestType & USB_TYPE_MASK) != USB_TYPE_STANDARD)
655 break;
656 s3c_hsudc_process_req_status(hsudc, &ctrl);
657 return;
659 case USB_REQ_SET_FEATURE:
660 case USB_REQ_CLEAR_FEATURE:
661 if ((ctrl.bRequestType & USB_TYPE_MASK) != USB_TYPE_STANDARD)
662 break;
663 s3c_hsudc_handle_reqfeat(hsudc, &ctrl);
664 hsudc->ep0state = WAIT_FOR_SETUP;
665 return;
668 if (hsudc->driver) {
669 spin_unlock(&hsudc->lock);
670 ret = hsudc->driver->setup(&hsudc->gadget, &ctrl);
671 spin_lock(&hsudc->lock);
673 if (ctrl.bRequest == USB_REQ_SET_CONFIGURATION) {
674 hsep->bEndpointAddress &= ~USB_DIR_IN;
675 hsudc->ep0state = WAIT_FOR_SETUP;
678 if (ret < 0) {
679 dev_err(hsudc->dev, "setup failed, returned %d\n",
680 ret);
681 s3c_hsudc_set_halt(&hsep->ep, 1);
682 hsudc->ep0state = WAIT_FOR_SETUP;
683 hsep->bEndpointAddress &= ~USB_DIR_IN;
688 /** s3c_hsudc_handle_ep0_intr - Handle endpoint 0 interrupt.
689 * @hsudc: Device controller on which endpoint 0 interrupt has occured.
691 * Handle endpoint 0 interrupt when it occurs. EP0 interrupt could occur
692 * when a stall handshake is sent to host or data is sent/received on
693 * endpoint 0.
695 static void s3c_hsudc_handle_ep0_intr(struct s3c_hsudc *hsudc)
697 struct s3c_hsudc_ep *hsep = &hsudc->ep[0];
698 struct s3c_hsudc_req *hsreq;
699 u32 csr = readl(hsudc->regs + S3C_EP0SR);
700 u32 ecr;
702 if (csr & S3C_EP0SR_STALL) {
703 ecr = readl(hsudc->regs + S3C_EP0CR);
704 ecr &= ~(S3C_ECR_STALL | S3C_ECR_FLUSH);
705 writel(ecr, hsudc->regs + S3C_EP0CR);
707 writel(S3C_EP0SR_STALL, hsudc->regs + S3C_EP0SR);
708 hsep->stopped = 0;
710 s3c_hsudc_nuke_ep(hsep, -ECONNABORTED);
711 hsudc->ep0state = WAIT_FOR_SETUP;
712 hsep->bEndpointAddress &= ~USB_DIR_IN;
713 return;
716 if (csr & S3C_EP0SR_TX_SUCCESS) {
717 writel(S3C_EP0SR_TX_SUCCESS, hsudc->regs + S3C_EP0SR);
718 if (ep_is_in(hsep)) {
719 if (list_empty(&hsep->queue))
720 return;
722 hsreq = list_entry(hsep->queue.next,
723 struct s3c_hsudc_req, queue);
724 s3c_hsudc_write_fifo(hsep, hsreq);
728 if (csr & S3C_EP0SR_RX_SUCCESS) {
729 if (hsudc->ep0state == WAIT_FOR_SETUP)
730 s3c_hsudc_process_setup(hsudc);
731 else {
732 if (!ep_is_in(hsep)) {
733 if (list_empty(&hsep->queue))
734 return;
735 hsreq = list_entry(hsep->queue.next,
736 struct s3c_hsudc_req, queue);
737 s3c_hsudc_read_fifo(hsep, hsreq);
744 * s3c_hsudc_ep_enable - Enable a endpoint.
745 * @_ep: The endpoint to be enabled.
746 * @desc: Endpoint descriptor.
748 * Enables a endpoint when called from the gadget driver. Endpoint stall if
749 * any is cleared, transfer type is configured and endpoint interrupt is
750 * enabled.
752 static int s3c_hsudc_ep_enable(struct usb_ep *_ep,
753 const struct usb_endpoint_descriptor *desc)
755 struct s3c_hsudc_ep *hsep;
756 struct s3c_hsudc *hsudc;
757 unsigned long flags;
758 u32 ecr = 0;
760 hsep = container_of(_ep, struct s3c_hsudc_ep, ep);
761 if (!_ep || !desc || hsep->desc || _ep->name == ep0name
762 || desc->bDescriptorType != USB_DT_ENDPOINT
763 || hsep->bEndpointAddress != desc->bEndpointAddress
764 || ep_maxpacket(hsep) < usb_endpoint_maxp(desc))
765 return -EINVAL;
767 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
768 && usb_endpoint_maxp(desc) != ep_maxpacket(hsep))
769 || !desc->wMaxPacketSize)
770 return -ERANGE;
772 hsudc = hsep->dev;
773 if (!hsudc->driver || hsudc->gadget.speed == USB_SPEED_UNKNOWN)
774 return -ESHUTDOWN;
776 spin_lock_irqsave(&hsudc->lock, flags);
778 set_index(hsudc, hsep->bEndpointAddress);
779 ecr |= ((usb_endpoint_xfer_int(desc)) ? S3C_ECR_IEMS : S3C_ECR_DUEN);
780 writel(ecr, hsudc->regs + S3C_ECR);
782 hsep->stopped = hsep->wedge = 0;
783 hsep->desc = desc;
784 hsep->ep.maxpacket = usb_endpoint_maxp(desc);
786 s3c_hsudc_set_halt(_ep, 0);
787 __set_bit(ep_index(hsep), hsudc->regs + S3C_EIER);
789 spin_unlock_irqrestore(&hsudc->lock, flags);
790 return 0;
794 * s3c_hsudc_ep_disable - Disable a endpoint.
795 * @_ep: The endpoint to be disabled.
796 * @desc: Endpoint descriptor.
798 * Disables a endpoint when called from the gadget driver.
800 static int s3c_hsudc_ep_disable(struct usb_ep *_ep)
802 struct s3c_hsudc_ep *hsep = our_ep(_ep);
803 struct s3c_hsudc *hsudc = hsep->dev;
804 unsigned long flags;
806 if (!_ep || !hsep->desc)
807 return -EINVAL;
809 spin_lock_irqsave(&hsudc->lock, flags);
811 set_index(hsudc, hsep->bEndpointAddress);
812 __clear_bit(ep_index(hsep), hsudc->regs + S3C_EIER);
814 s3c_hsudc_nuke_ep(hsep, -ESHUTDOWN);
816 hsep->desc = 0;
817 hsep->stopped = 1;
819 spin_unlock_irqrestore(&hsudc->lock, flags);
820 return 0;
824 * s3c_hsudc_alloc_request - Allocate a new request.
825 * @_ep: Endpoint for which request is allocated (not used).
826 * @gfp_flags: Flags used for the allocation.
828 * Allocates a single transfer request structure when called from gadget driver.
830 static struct usb_request *s3c_hsudc_alloc_request(struct usb_ep *_ep,
831 gfp_t gfp_flags)
833 struct s3c_hsudc_req *hsreq;
835 hsreq = kzalloc(sizeof *hsreq, gfp_flags);
836 if (!hsreq)
837 return 0;
839 INIT_LIST_HEAD(&hsreq->queue);
840 return &hsreq->req;
844 * s3c_hsudc_free_request - Deallocate a request.
845 * @ep: Endpoint for which request is deallocated (not used).
846 * @_req: Request to be deallocated.
848 * Allocates a single transfer request structure when called from gadget driver.
850 static void s3c_hsudc_free_request(struct usb_ep *ep, struct usb_request *_req)
852 struct s3c_hsudc_req *hsreq;
854 hsreq = container_of(_req, struct s3c_hsudc_req, req);
855 WARN_ON(!list_empty(&hsreq->queue));
856 kfree(hsreq);
860 * s3c_hsudc_queue - Queue a transfer request for the endpoint.
861 * @_ep: Endpoint for which the request is queued.
862 * @_req: Request to be queued.
863 * @gfp_flags: Not used.
865 * Start or enqueue a request for a endpoint when called from gadget driver.
867 static int s3c_hsudc_queue(struct usb_ep *_ep, struct usb_request *_req,
868 gfp_t gfp_flags)
870 struct s3c_hsudc_req *hsreq;
871 struct s3c_hsudc_ep *hsep;
872 struct s3c_hsudc *hsudc;
873 unsigned long flags;
874 u32 offset;
875 u32 csr;
877 hsreq = container_of(_req, struct s3c_hsudc_req, req);
878 if ((!_req || !_req->complete || !_req->buf ||
879 !list_empty(&hsreq->queue)))
880 return -EINVAL;
882 hsep = container_of(_ep, struct s3c_hsudc_ep, ep);
883 hsudc = hsep->dev;
884 if (!hsudc->driver || hsudc->gadget.speed == USB_SPEED_UNKNOWN)
885 return -ESHUTDOWN;
887 spin_lock_irqsave(&hsudc->lock, flags);
888 set_index(hsudc, hsep->bEndpointAddress);
890 _req->status = -EINPROGRESS;
891 _req->actual = 0;
893 if (!ep_index(hsep) && _req->length == 0) {
894 hsudc->ep0state = WAIT_FOR_SETUP;
895 s3c_hsudc_complete_request(hsep, hsreq, 0);
896 spin_unlock_irqrestore(&hsudc->lock, flags);
897 return 0;
900 if (list_empty(&hsep->queue) && !hsep->stopped) {
901 offset = (ep_index(hsep)) ? S3C_ESR : S3C_EP0SR;
902 if (ep_is_in(hsep)) {
903 csr = readl((u32)hsudc->regs + offset);
904 if (!(csr & S3C_ESR_TX_SUCCESS) &&
905 (s3c_hsudc_write_fifo(hsep, hsreq) == 1))
906 hsreq = 0;
907 } else {
908 csr = readl((u32)hsudc->regs + offset);
909 if ((csr & S3C_ESR_RX_SUCCESS)
910 && (s3c_hsudc_read_fifo(hsep, hsreq) == 1))
911 hsreq = 0;
915 if (hsreq != 0)
916 list_add_tail(&hsreq->queue, &hsep->queue);
918 spin_unlock_irqrestore(&hsudc->lock, flags);
919 return 0;
923 * s3c_hsudc_dequeue - Dequeue a transfer request from an endpoint.
924 * @_ep: Endpoint from which the request is dequeued.
925 * @_req: Request to be dequeued.
927 * Dequeue a request from a endpoint when called from gadget driver.
929 static int s3c_hsudc_dequeue(struct usb_ep *_ep, struct usb_request *_req)
931 struct s3c_hsudc_ep *hsep = our_ep(_ep);
932 struct s3c_hsudc *hsudc = hsep->dev;
933 struct s3c_hsudc_req *hsreq;
934 unsigned long flags;
936 hsep = container_of(_ep, struct s3c_hsudc_ep, ep);
937 if (!_ep || hsep->ep.name == ep0name)
938 return -EINVAL;
940 spin_lock_irqsave(&hsudc->lock, flags);
942 list_for_each_entry(hsreq, &hsep->queue, queue) {
943 if (&hsreq->req == _req)
944 break;
946 if (&hsreq->req != _req) {
947 spin_unlock_irqrestore(&hsudc->lock, flags);
948 return -EINVAL;
951 set_index(hsudc, hsep->bEndpointAddress);
952 s3c_hsudc_complete_request(hsep, hsreq, -ECONNRESET);
954 spin_unlock_irqrestore(&hsudc->lock, flags);
955 return 0;
958 static struct usb_ep_ops s3c_hsudc_ep_ops = {
959 .enable = s3c_hsudc_ep_enable,
960 .disable = s3c_hsudc_ep_disable,
961 .alloc_request = s3c_hsudc_alloc_request,
962 .free_request = s3c_hsudc_free_request,
963 .queue = s3c_hsudc_queue,
964 .dequeue = s3c_hsudc_dequeue,
965 .set_halt = s3c_hsudc_set_halt,
966 .set_wedge = s3c_hsudc_set_wedge,
970 * s3c_hsudc_initep - Initialize a endpoint to default state.
971 * @hsudc - Reference to the device controller.
972 * @hsep - Endpoint to be initialized.
973 * @epnum - Address to be assigned to the endpoint.
975 * Initialize a endpoint with default configuration.
977 static void s3c_hsudc_initep(struct s3c_hsudc *hsudc,
978 struct s3c_hsudc_ep *hsep, int epnum)
980 char *dir;
982 if ((epnum % 2) == 0) {
983 dir = "out";
984 } else {
985 dir = "in";
986 hsep->bEndpointAddress = USB_DIR_IN;
989 hsep->bEndpointAddress |= epnum;
990 if (epnum)
991 snprintf(hsep->name, sizeof(hsep->name), "ep%d%s", epnum, dir);
992 else
993 snprintf(hsep->name, sizeof(hsep->name), "%s", ep0name);
995 INIT_LIST_HEAD(&hsep->queue);
996 INIT_LIST_HEAD(&hsep->ep.ep_list);
997 if (epnum)
998 list_add_tail(&hsep->ep.ep_list, &hsudc->gadget.ep_list);
1000 hsep->dev = hsudc;
1001 hsep->ep.name = hsep->name;
1002 hsep->ep.maxpacket = epnum ? 512 : 64;
1003 hsep->ep.ops = &s3c_hsudc_ep_ops;
1004 hsep->fifo = hsudc->regs + S3C_BR(epnum);
1005 hsep->desc = 0;
1006 hsep->stopped = 0;
1007 hsep->wedge = 0;
1009 set_index(hsudc, epnum);
1010 writel(hsep->ep.maxpacket, hsudc->regs + S3C_MPR);
1014 * s3c_hsudc_setup_ep - Configure all endpoints to default state.
1015 * @hsudc: Reference to device controller.
1017 * Configures all endpoints to default state.
1019 static void s3c_hsudc_setup_ep(struct s3c_hsudc *hsudc)
1021 int epnum;
1023 hsudc->ep0state = WAIT_FOR_SETUP;
1024 INIT_LIST_HEAD(&hsudc->gadget.ep_list);
1025 for (epnum = 0; epnum < hsudc->pd->epnum; epnum++)
1026 s3c_hsudc_initep(hsudc, &hsudc->ep[epnum], epnum);
1030 * s3c_hsudc_reconfig - Reconfigure the device controller to default state.
1031 * @hsudc: Reference to device controller.
1033 * Reconfigures the device controller registers to a default state.
1035 static void s3c_hsudc_reconfig(struct s3c_hsudc *hsudc)
1037 writel(0xAA, hsudc->regs + S3C_EDR);
1038 writel(1, hsudc->regs + S3C_EIER);
1039 writel(0, hsudc->regs + S3C_TR);
1040 writel(S3C_SCR_DTZIEN_EN | S3C_SCR_RRD_EN | S3C_SCR_SUS_EN |
1041 S3C_SCR_RST_EN, hsudc->regs + S3C_SCR);
1042 writel(0, hsudc->regs + S3C_EP0CR);
1044 s3c_hsudc_setup_ep(hsudc);
1048 * s3c_hsudc_irq - Interrupt handler for device controller.
1049 * @irq: Not used.
1050 * @_dev: Reference to the device controller.
1052 * Interrupt handler for the device controller. This handler handles controller
1053 * interrupts and endpoint interrupts.
1055 static irqreturn_t s3c_hsudc_irq(int irq, void *_dev)
1057 struct s3c_hsudc *hsudc = _dev;
1058 struct s3c_hsudc_ep *hsep;
1059 u32 ep_intr;
1060 u32 sys_status;
1061 u32 ep_idx;
1063 spin_lock(&hsudc->lock);
1065 sys_status = readl(hsudc->regs + S3C_SSR);
1066 ep_intr = readl(hsudc->regs + S3C_EIR) & 0x3FF;
1068 if (!ep_intr && !(sys_status & S3C_SSR_DTZIEN_EN)) {
1069 spin_unlock(&hsudc->lock);
1070 return IRQ_HANDLED;
1073 if (sys_status) {
1074 if (sys_status & S3C_SSR_VBUSON)
1075 writel(S3C_SSR_VBUSON, hsudc->regs + S3C_SSR);
1077 if (sys_status & S3C_SSR_ERR)
1078 writel(S3C_SSR_ERR, hsudc->regs + S3C_SSR);
1080 if (sys_status & S3C_SSR_SDE) {
1081 writel(S3C_SSR_SDE, hsudc->regs + S3C_SSR);
1082 hsudc->gadget.speed = (sys_status & S3C_SSR_HSP) ?
1083 USB_SPEED_HIGH : USB_SPEED_FULL;
1086 if (sys_status & S3C_SSR_SUSPEND) {
1087 writel(S3C_SSR_SUSPEND, hsudc->regs + S3C_SSR);
1088 if (hsudc->gadget.speed != USB_SPEED_UNKNOWN
1089 && hsudc->driver && hsudc->driver->suspend)
1090 hsudc->driver->suspend(&hsudc->gadget);
1093 if (sys_status & S3C_SSR_RESUME) {
1094 writel(S3C_SSR_RESUME, hsudc->regs + S3C_SSR);
1095 if (hsudc->gadget.speed != USB_SPEED_UNKNOWN
1096 && hsudc->driver && hsudc->driver->resume)
1097 hsudc->driver->resume(&hsudc->gadget);
1100 if (sys_status & S3C_SSR_RESET) {
1101 writel(S3C_SSR_RESET, hsudc->regs + S3C_SSR);
1102 for (ep_idx = 0; ep_idx < hsudc->pd->epnum; ep_idx++) {
1103 hsep = &hsudc->ep[ep_idx];
1104 hsep->stopped = 1;
1105 s3c_hsudc_nuke_ep(hsep, -ECONNRESET);
1107 s3c_hsudc_reconfig(hsudc);
1108 hsudc->ep0state = WAIT_FOR_SETUP;
1112 if (ep_intr & S3C_EIR_EP0) {
1113 writel(S3C_EIR_EP0, hsudc->regs + S3C_EIR);
1114 set_index(hsudc, 0);
1115 s3c_hsudc_handle_ep0_intr(hsudc);
1118 ep_intr >>= 1;
1119 ep_idx = 1;
1120 while (ep_intr) {
1121 if (ep_intr & 1) {
1122 hsep = &hsudc->ep[ep_idx];
1123 set_index(hsudc, ep_idx);
1124 writel(1 << ep_idx, hsudc->regs + S3C_EIR);
1125 if (ep_is_in(hsep))
1126 s3c_hsudc_epin_intr(hsudc, ep_idx);
1127 else
1128 s3c_hsudc_epout_intr(hsudc, ep_idx);
1130 ep_intr >>= 1;
1131 ep_idx++;
1134 spin_unlock(&hsudc->lock);
1135 return IRQ_HANDLED;
1138 static int s3c_hsudc_start(struct usb_gadget_driver *driver,
1139 int (*bind)(struct usb_gadget *))
1141 struct s3c_hsudc *hsudc = the_controller;
1142 int ret;
1144 if (!driver
1145 || (driver->speed != USB_SPEED_FULL &&
1146 driver->speed != USB_SPEED_HIGH)
1147 || !bind
1148 || !driver->unbind || !driver->disconnect || !driver->setup)
1149 return -EINVAL;
1151 if (!hsudc)
1152 return -ENODEV;
1154 if (hsudc->driver)
1155 return -EBUSY;
1157 hsudc->driver = driver;
1158 hsudc->gadget.dev.driver = &driver->driver;
1159 hsudc->gadget.speed = USB_SPEED_UNKNOWN;
1160 ret = device_add(&hsudc->gadget.dev);
1161 if (ret) {
1162 dev_err(hsudc->dev, "failed to probe gadget device");
1163 return ret;
1166 ret = bind(&hsudc->gadget);
1167 if (ret) {
1168 dev_err(hsudc->dev, "%s: bind failed\n", hsudc->gadget.name);
1169 device_del(&hsudc->gadget.dev);
1171 hsudc->driver = NULL;
1172 hsudc->gadget.dev.driver = NULL;
1173 return ret;
1176 /* connect to bus through transceiver */
1177 if (hsudc->transceiver) {
1178 ret = otg_set_peripheral(hsudc->transceiver, &hsudc->gadget);
1179 if (ret) {
1180 dev_err(hsudc->dev, "%s: can't bind to transceiver\n",
1181 hsudc->gadget.name);
1182 driver->unbind(&hsudc->gadget);
1184 device_del(&hsudc->gadget.dev);
1186 hsudc->driver = NULL;
1187 hsudc->gadget.dev.driver = NULL;
1188 return ret;
1192 enable_irq(hsudc->irq);
1193 dev_info(hsudc->dev, "bound driver %s\n", driver->driver.name);
1195 s3c_hsudc_reconfig(hsudc);
1196 s3c_hsudc_init_phy();
1197 if (hsudc->pd->gpio_init)
1198 hsudc->pd->gpio_init();
1200 return 0;
1203 static int s3c_hsudc_stop(struct usb_gadget_driver *driver)
1205 struct s3c_hsudc *hsudc = the_controller;
1206 unsigned long flags;
1208 if (!hsudc)
1209 return -ENODEV;
1211 if (!driver || driver != hsudc->driver || !driver->unbind)
1212 return -EINVAL;
1214 spin_lock_irqsave(&hsudc->lock, flags);
1215 hsudc->driver = 0;
1216 s3c_hsudc_uninit_phy();
1217 if (hsudc->pd->gpio_uninit)
1218 hsudc->pd->gpio_uninit();
1219 s3c_hsudc_stop_activity(hsudc, driver);
1220 spin_unlock_irqrestore(&hsudc->lock, flags);
1222 if (hsudc->transceiver)
1223 (void) otg_set_peripheral(hsudc->transceiver, NULL);
1225 driver->unbind(&hsudc->gadget);
1226 device_del(&hsudc->gadget.dev);
1227 disable_irq(hsudc->irq);
1229 dev_info(hsudc->dev, "unregistered gadget driver '%s'\n",
1230 driver->driver.name);
1231 return 0;
1234 static inline u32 s3c_hsudc_read_frameno(struct s3c_hsudc *hsudc)
1236 return readl(hsudc->regs + S3C_FNR) & 0x3FF;
1239 static int s3c_hsudc_gadget_getframe(struct usb_gadget *gadget)
1241 return s3c_hsudc_read_frameno(to_hsudc(gadget));
1244 static struct usb_gadget_ops s3c_hsudc_gadget_ops = {
1245 .get_frame = s3c_hsudc_gadget_getframe,
1246 .start = s3c_hsudc_start,
1247 .stop = s3c_hsudc_stop,
1250 static int s3c_hsudc_probe(struct platform_device *pdev)
1252 struct device *dev = &pdev->dev;
1253 struct resource *res;
1254 struct s3c_hsudc *hsudc;
1255 struct s3c24xx_hsudc_platdata *pd = pdev->dev.platform_data;
1256 int ret;
1258 hsudc = kzalloc(sizeof(struct s3c_hsudc) +
1259 sizeof(struct s3c_hsudc_ep) * pd->epnum,
1260 GFP_KERNEL);
1261 if (!hsudc) {
1262 dev_err(dev, "cannot allocate memory\n");
1263 return -ENOMEM;
1266 the_controller = hsudc;
1267 platform_set_drvdata(pdev, dev);
1268 hsudc->dev = dev;
1269 hsudc->pd = pdev->dev.platform_data;
1271 hsudc->transceiver = otg_get_transceiver();
1273 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1274 if (!res) {
1275 dev_err(dev, "unable to obtain driver resource data\n");
1276 ret = -ENODEV;
1277 goto err_res;
1280 hsudc->mem_rsrc = request_mem_region(res->start, resource_size(res),
1281 dev_name(&pdev->dev));
1282 if (!hsudc->mem_rsrc) {
1283 dev_err(dev, "failed to reserve register area\n");
1284 ret = -ENODEV;
1285 goto err_res;
1288 hsudc->regs = ioremap(res->start, resource_size(res));
1289 if (!hsudc->regs) {
1290 dev_err(dev, "error mapping device register area\n");
1291 ret = -EBUSY;
1292 goto err_remap;
1295 spin_lock_init(&hsudc->lock);
1297 device_initialize(&hsudc->gadget.dev);
1298 dev_set_name(&hsudc->gadget.dev, "gadget");
1300 hsudc->gadget.is_dualspeed = 1;
1301 hsudc->gadget.ops = &s3c_hsudc_gadget_ops;
1302 hsudc->gadget.name = dev_name(dev);
1303 hsudc->gadget.dev.parent = dev;
1304 hsudc->gadget.dev.dma_mask = dev->dma_mask;
1305 hsudc->gadget.ep0 = &hsudc->ep[0].ep;
1307 hsudc->gadget.is_otg = 0;
1308 hsudc->gadget.is_a_peripheral = 0;
1310 s3c_hsudc_setup_ep(hsudc);
1312 ret = platform_get_irq(pdev, 0);
1313 if (ret < 0) {
1314 dev_err(dev, "unable to obtain IRQ number\n");
1315 goto err_irq;
1317 hsudc->irq = ret;
1319 ret = request_irq(hsudc->irq, s3c_hsudc_irq, 0, driver_name, hsudc);
1320 if (ret < 0) {
1321 dev_err(dev, "irq request failed\n");
1322 goto err_irq;
1325 hsudc->uclk = clk_get(&pdev->dev, "usb-device");
1326 if (IS_ERR(hsudc->uclk)) {
1327 dev_err(dev, "failed to find usb-device clock source\n");
1328 ret = PTR_ERR(hsudc->uclk);
1329 goto err_clk;
1331 clk_enable(hsudc->uclk);
1333 local_irq_disable();
1335 disable_irq(hsudc->irq);
1336 local_irq_enable();
1338 ret = usb_add_gadget_udc(&pdev->dev, &hsudc->gadget);
1339 if (ret)
1340 goto err_add_udc;
1342 return 0;
1343 err_add_udc:
1344 clk_disable(hsudc->uclk);
1345 clk_put(hsudc->uclk);
1346 err_clk:
1347 free_irq(hsudc->irq, hsudc);
1348 err_irq:
1349 iounmap(hsudc->regs);
1351 err_remap:
1352 release_resource(hsudc->mem_rsrc);
1353 kfree(hsudc->mem_rsrc);
1355 err_res:
1356 kfree(hsudc);
1357 return ret;
1360 static struct platform_driver s3c_hsudc_driver = {
1361 .driver = {
1362 .owner = THIS_MODULE,
1363 .name = "s3c-hsudc",
1365 .probe = s3c_hsudc_probe,
1367 MODULE_ALIAS("platform:s3c-hsudc");
1369 static int __init s3c_hsudc_modinit(void)
1371 return platform_driver_register(&s3c_hsudc_driver);
1374 static void __exit s3c_hsudc_modexit(void)
1376 platform_driver_unregister(&s3c_hsudc_driver);
1379 module_init(s3c_hsudc_modinit);
1380 module_exit(s3c_hsudc_modexit);
1382 MODULE_DESCRIPTION("Samsung S3C24XX USB high-speed controller driver");
1383 MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com>");
1384 MODULE_LICENSE("GPL");