drivers/usb/host/ehci.h

   1 /*
   2  * Copyright (c) 2001-2002 by David Brownell
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the
   6  * Free Software Foundation; either version 2 of the License, or (at your
   7  * option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  11  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software Foundation,
  16  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17  */
  18
  19 #ifndef __LINUX_EHCI_HCD_H
  20 #define __LINUX_EHCI_HCD_H
  21
  22 /* definitions used for the EHCI driver */
  23
  24 /*
  25  * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
  26  * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
  27  * the host controller implementation.
  28  *
  29  * To facilitate the strongest possible byte-order checking from "sparse"
  30  * and so on, we use __leXX unless that's not practical.
  31  */
  32 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
  33 typedef __u32 __bitwise __hc32;
  34 typedef __u16 __bitwise __hc16;
  35 #else
  36 #define __hc32  __le32
  37 #define __hc16  __le16
  38 #endif
  39
  40 /* statistics can be kept for tuning/monitoring */
  41 struct ehci_stats {
  42         /* irq usage */
  43         unsigned long           normal;
  44         unsigned long           error;
  45         unsigned long           reclaim;
  46         unsigned long           lost_iaa;
  47
  48         /* termination of urbs from core */
  49         unsigned long           complete;
  50         unsigned long           unlink;
  51 };
  52
  53 /* ehci_hcd->lock guards shared data against other CPUs:
  54  *   ehci_hcd:  async, reclaim, periodic (and shadow), ...
  55  *   usb_host_endpoint: hcpriv
  56  *   ehci_qh:   qh_next, qtd_list
  57  *   ehci_qtd:  qtd_list
  58  *
  59  * Also, hold this lock when talking to HC registers or
  60  * when updating hw_* fields in shared qh/qtd/... structures.
  61  */
  62
  63 #define EHCI_MAX_ROOT_PORTS     15              /* see HCS_N_PORTS */
  64
  65 enum ehci_rh_state {
  66         EHCI_RH_HALTED,
  67         EHCI_RH_SUSPENDED,
  68         EHCI_RH_RUNNING
  69 };
  70
  71 struct ehci_hcd {                       /* one per controller */
  72         /* glue to PCI and HCD framework */
  73         struct ehci_caps __iomem *caps;
  74         struct ehci_regs __iomem *regs;
  75         struct ehci_dbg_port __iomem *debug;
  76
  77         __u32                   hcs_params;     /* cached register copy */
  78         spinlock_t              lock;
  79         enum ehci_rh_state      rh_state;
  80
  81         /* async schedule support */
  82         struct ehci_qh          *async;
  83         struct ehci_qh          *dummy;         /* For AMD quirk use */
  84         struct ehci_qh          *reclaim;
  85         struct ehci_qh          *qh_scan_next;
  86         unsigned                scanning : 1;
  87
  88         /* periodic schedule support */
  89 #define DEFAULT_I_TDPS          1024            /* some HCs can do less */
  90         unsigned                periodic_size;
  91         __hc32                  *periodic;      /* hw periodic table */
  92         dma_addr_t              periodic_dma;
  93         unsigned                i_thresh;       /* uframes HC might cache */
  94
  95         union ehci_shadow       *pshadow;       /* mirror hw periodic table */
  96         int                     next_uframe;    /* scan periodic, start here */
  97         unsigned                periodic_sched; /* periodic activity count */
  98         unsigned                uframe_periodic_max; /* max periodic time per uframe */
  99
 100
 101         /* list of itds & sitds completed while clock_frame was still active */
 102         struct list_head        cached_itd_list;
 103         struct list_head        cached_sitd_list;
 104         unsigned                clock_frame;
 105
 106         /* per root hub port */
 107         unsigned long           reset_done [EHCI_MAX_ROOT_PORTS];
 108
 109         /* bit vectors (one bit per port) */
 110         unsigned long           bus_suspended;          /* which ports were
 111                         already suspended at the start of a bus suspend */
 112         unsigned long           companion_ports;        /* which ports are
 113                         dedicated to the companion controller */
 114         unsigned long           owned_ports;            /* which ports are
 115                         owned by the companion during a bus suspend */
 116         unsigned long           port_c_suspend;         /* which ports have
 117                         the change-suspend feature turned on */
 118         unsigned long           suspended_ports;        /* which ports are
 119                         suspended */
 120
 121         /* per-HC memory pools (could be per-bus, but ...) */
 122         struct dma_pool         *qh_pool;       /* qh per active urb */
 123         struct dma_pool         *qtd_pool;      /* one or more per qh */
 124         struct dma_pool         *itd_pool;      /* itd per iso urb */
 125         struct dma_pool         *sitd_pool;     /* sitd per split iso urb */
 126
 127         struct timer_list       iaa_watchdog;
 128         struct timer_list       watchdog;
 129         unsigned long           actions;
 130         unsigned                periodic_stamp;
 131         unsigned                random_frame;
 132         unsigned long           next_statechange;
 133         ktime_t                 last_periodic_enable;
 134         u32                     command;
 135
 136         /* SILICON QUIRKS */
 137         unsigned                no_selective_suspend:1;
 138         unsigned                has_fsl_port_bug:1; /* FreeScale */
 139         unsigned                big_endian_mmio:1;
 140         unsigned                big_endian_desc:1;
 141         unsigned                big_endian_capbase:1;
 142         unsigned                has_amcc_usb23:1;
 143         unsigned                need_io_watchdog:1;
 144         unsigned                broken_periodic:1;
 145         unsigned                amd_pll_fix:1;
 146         unsigned                fs_i_thresh:1;  /* Intel iso scheduling */
 147         unsigned                use_dummy_qh:1; /* AMD Frame List table quirk*/
 148         unsigned                has_synopsys_hc_bug:1; /* Synopsys HC */
 149
 150         /* required for usb32 quirk */
 151         #define OHCI_CTRL_HCFS          (3 << 6)
 152         #define OHCI_USB_OPER           (2 << 6)
 153         #define OHCI_USB_SUSPEND        (3 << 6)
 154
 155         #define OHCI_HCCTRL_OFFSET      0x4
 156         #define OHCI_HCCTRL_LEN         0x4
 157         __hc32                  *ohci_hcctrl_reg;
 158         unsigned                has_hostpc:1;
 159         unsigned                has_lpm:1;  /* support link power management */
 160         unsigned                has_ppcd:1; /* support per-port change bits */
 161         u8                      sbrn;           /* packed release number */
 162
 163         /* irq statistics */
 164 #ifdef EHCI_STATS
 165         struct ehci_stats       stats;
 166 #       define COUNT(x) do { (x)++; } while (0)
 167 #else
 168 #       define COUNT(x) do {} while (0)
 169 #endif
 170
 171         /* debug files */
 172 #ifdef DEBUG
 173         struct dentry           *debug_dir;
 174 #endif
 175         /*
 176          * OTG controllers and transceivers need software interaction
 177          */
 178         struct otg_transceiver  *transceiver;
 179 };
 180
 181 /* convert between an HCD pointer and the corresponding EHCI_HCD */
 182 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
 183 {
 184         return (struct ehci_hcd *) (hcd->hcd_priv);
 185 }
 186 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
 187 {
 188         return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
 189 }
 190
 191
 192 static inline void
 193 iaa_watchdog_start(struct ehci_hcd *ehci)
 194 {
 195         WARN_ON(timer_pending(&ehci->iaa_watchdog));
 196         mod_timer(&ehci->iaa_watchdog,
 197                         jiffies + msecs_to_jiffies(EHCI_IAA_MSECS));
 198 }
 199
 200 static inline void iaa_watchdog_done(struct ehci_hcd *ehci)
 201 {
 202         del_timer(&ehci->iaa_watchdog);
 203 }
 204
 205 enum ehci_timer_action {
 206         TIMER_IO_WATCHDOG,
 207         TIMER_ASYNC_SHRINK,
 208         TIMER_ASYNC_OFF,
 209 };
 210
 211 static inline void
 212 timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
 213 {
 214         clear_bit (action, &ehci->actions);
 215 }
 216
 217 static void free_cached_lists(struct ehci_hcd *ehci);
 218
 219 /*-------------------------------------------------------------------------*/
 220
 221 #include <linux/usb/ehci_def.h>
 222
 223 /*-------------------------------------------------------------------------*/
 224
 225 #define QTD_NEXT(ehci, dma)     cpu_to_hc32(ehci, (u32)dma)
 226
 227 /*
 228  * EHCI Specification 0.95 Section 3.5
 229  * QTD: describe data transfer components (buffer, direction, ...)
 230  * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
 231  *
 232  * These are associated only with "QH" (Queue Head) structures,
 233  * used with control, bulk, and interrupt transfers.
 234  */
 235 struct ehci_qtd {
 236         /* first part defined by EHCI spec */
 237         __hc32                  hw_next;        /* see EHCI 3.5.1 */
 238         __hc32                  hw_alt_next;    /* see EHCI 3.5.2 */
 239         __hc32                  hw_token;       /* see EHCI 3.5.3 */
 240 #define QTD_TOGGLE      (1 << 31)       /* data toggle */
 241 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
 242 #define QTD_IOC         (1 << 15)       /* interrupt on complete */
 243 #define QTD_CERR(tok)   (((tok)>>10) & 0x3)
 244 #define QTD_PID(tok)    (((tok)>>8) & 0x3)
 245 #define QTD_STS_ACTIVE  (1 << 7)        /* HC may execute this */
 246 #define QTD_STS_HALT    (1 << 6)        /* halted on error */
 247 #define QTD_STS_DBE     (1 << 5)        /* data buffer error (in HC) */
 248 #define QTD_STS_BABBLE  (1 << 4)        /* device was babbling (qtd halted) */
 249 #define QTD_STS_XACT    (1 << 3)        /* device gave illegal response */
 250 #define QTD_STS_MMF     (1 << 2)        /* incomplete split transaction */
 251 #define QTD_STS_STS     (1 << 1)        /* split transaction state */
 252 #define QTD_STS_PING    (1 << 0)        /* issue PING? */
 253
 254 #define ACTIVE_BIT(ehci)        cpu_to_hc32(ehci, QTD_STS_ACTIVE)
 255 #define HALT_BIT(ehci)          cpu_to_hc32(ehci, QTD_STS_HALT)
 256 #define STATUS_BIT(ehci)        cpu_to_hc32(ehci, QTD_STS_STS)
 257
 258         __hc32                  hw_buf [5];        /* see EHCI 3.5.4 */
 259         __hc32                  hw_buf_hi [5];        /* Appendix B */
 260
 261         /* the rest is HCD-private */
 262         dma_addr_t              qtd_dma;                /* qtd address */
 263         struct list_head        qtd_list;               /* sw qtd list */
 264         struct urb              *urb;                   /* qtd's urb */
 265         size_t                  length;                 /* length of buffer */
 266 } __attribute__ ((aligned (32)));
 267
 268 /* mask NakCnt+T in qh->hw_alt_next */
 269 #define QTD_MASK(ehci)  cpu_to_hc32 (ehci, ~0x1f)
 270
 271 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
 272
 273 /*-------------------------------------------------------------------------*/
 274
 275 /* type tag from {qh,itd,sitd,fstn}->hw_next */
 276 #define Q_NEXT_TYPE(ehci,dma)   ((dma) & cpu_to_hc32(ehci, 3 << 1))
 277
 278 /*
 279  * Now the following defines are not converted using the
 280  * cpu_to_le32() macro anymore, since we have to support
 281  * "dynamic" switching between be and le support, so that the driver
 282  * can be used on one system with SoC EHCI controller using big-endian
 283  * descriptors as well as a normal little-endian PCI EHCI controller.
 284  */
 285 /* values for that type tag */
 286 #define Q_TYPE_ITD      (0 << 1)
 287 #define Q_TYPE_QH       (1 << 1)
 288 #define Q_TYPE_SITD     (2 << 1)
 289 #define Q_TYPE_FSTN     (3 << 1)
 290
 291 /* next async queue entry, or pointer to interrupt/periodic QH */
 292 #define QH_NEXT(ehci,dma)       (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH))
 293
 294 /* for periodic/async schedules and qtd lists, mark end of list */
 295 #define EHCI_LIST_END(ehci)     cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
 296
 297 /*
 298  * Entries in periodic shadow table are pointers to one of four kinds
 299  * of data structure.  That's dictated by the hardware; a type tag is
 300  * encoded in the low bits of the hardware's periodic schedule.  Use
 301  * Q_NEXT_TYPE to get the tag.
 302  *
 303  * For entries in the async schedule, the type tag always says "qh".
 304  */
 305 union ehci_shadow {
 306         struct ehci_qh          *qh;            /* Q_TYPE_QH */
 307         struct ehci_itd         *itd;           /* Q_TYPE_ITD */
 308         struct ehci_sitd        *sitd;          /* Q_TYPE_SITD */
 309         struct ehci_fstn        *fstn;          /* Q_TYPE_FSTN */
 310         __hc32                  *hw_next;       /* (all types) */
 311         void                    *ptr;
 312 };
 313
 314 /*-------------------------------------------------------------------------*/
 315
 316 /*
 317  * EHCI Specification 0.95 Section 3.6
 318  * QH: describes control/bulk/interrupt endpoints
 319  * See Fig 3-7 "Queue Head Structure Layout".
 320  *
 321  * These appear in both the async and (for interrupt) periodic schedules.
 322  */
 323
 324 /* first part defined by EHCI spec */
 325 struct ehci_qh_hw {
 326         __hc32                  hw_next;        /* see EHCI 3.6.1 */
 327         __hc32                  hw_info1;       /* see EHCI 3.6.2 */
 328 #define QH_HEAD         0x00008000
 329         __hc32                  hw_info2;        /* see EHCI 3.6.2 */
 330 #define QH_SMASK        0x000000ff
 331 #define QH_CMASK        0x0000ff00
 332 #define QH_HUBADDR      0x007f0000
 333 #define QH_HUBPORT      0x3f800000
 334 #define QH_MULT         0xc0000000
 335         __hc32                  hw_current;     /* qtd list - see EHCI 3.6.4 */
 336
 337         /* qtd overlay (hardware parts of a struct ehci_qtd) */
 338         __hc32                  hw_qtd_next;
 339         __hc32                  hw_alt_next;
 340         __hc32                  hw_token;
 341         __hc32                  hw_buf [5];
 342         __hc32                  hw_buf_hi [5];
 343 } __attribute__ ((aligned(32)));
 344
 345 struct ehci_qh {
 346         struct ehci_qh_hw       *hw;
 347         /* the rest is HCD-private */
 348         dma_addr_t              qh_dma;         /* address of qh */
 349         union ehci_shadow       qh_next;        /* ptr to qh; or periodic */
 350         struct list_head        qtd_list;       /* sw qtd list */
 351         struct ehci_qtd         *dummy;
 352         struct ehci_qh          *reclaim;       /* next to reclaim */
 353
 354         struct ehci_hcd         *ehci;
 355         unsigned long           unlink_time;
 356
 357         /*
 358          * Do NOT use atomic operations for QH refcounting. On some CPUs
 359          * (PPC7448 for example), atomic operations cannot be performed on
 360          * memory that is cache-inhibited (i.e. being used for DMA).
 361          * Spinlocks are used to protect all QH fields.
 362          */
 363         u32                     refcount;
 364         unsigned                stamp;
 365
 366         u8                      needs_rescan;   /* Dequeue during giveback */
 367         u8                      qh_state;
 368 #define QH_STATE_LINKED         1               /* HC sees this */
 369 #define QH_STATE_UNLINK         2               /* HC may still see this */
 370 #define QH_STATE_IDLE           3               /* HC doesn't see this */
 371 #define QH_STATE_UNLINK_WAIT    4               /* LINKED and on reclaim q */
 372 #define QH_STATE_COMPLETING     5               /* don't touch token.HALT */
 373
 374         u8                      xacterrs;       /* XactErr retry counter */
 375 #define QH_XACTERR_MAX          32              /* XactErr retry limit */
 376
 377         /* periodic schedule info */
 378         u8                      usecs;          /* intr bandwidth */
 379         u8                      gap_uf;         /* uframes split/csplit gap */
 380         u8                      c_usecs;        /* ... split completion bw */
 381         u16                     tt_usecs;       /* tt downstream bandwidth */
 382         unsigned short          period;         /* polling interval */
 383         unsigned short          start;          /* where polling starts */
 384 #define NO_FRAME ((unsigned short)~0)                   /* pick new start */
 385
 386         struct usb_device       *dev;           /* access to TT */
 387         unsigned                is_out:1;       /* bulk or intr OUT */
 388         unsigned                clearing_tt:1;  /* Clear-TT-Buf in progress */
 389 };
 390
 391 /*-------------------------------------------------------------------------*/
 392
 393 /* description of one iso transaction (up to 3 KB data if highspeed) */
 394 struct ehci_iso_packet {
 395         /* These will be copied to iTD when scheduling */
 396         u64                     bufp;           /* itd->hw_bufp{,_hi}[pg] |= */
 397         __hc32                  transaction;    /* itd->hw_transaction[i] |= */
 398         u8                      cross;          /* buf crosses pages */
 399         /* for full speed OUT splits */
 400         u32                     buf1;
 401 };
 402
 403 /* temporary schedule data for packets from iso urbs (both speeds)
 404  * each packet is one logical usb transaction to the device (not TT),
 405  * beginning at stream->next_uframe
 406  */
 407 struct ehci_iso_sched {
 408         struct list_head        td_list;
 409         unsigned                span;
 410         struct ehci_iso_packet  packet [0];
 411 };
 412
 413 /*
 414  * ehci_iso_stream - groups all (s)itds for this endpoint.
 415  * acts like a qh would, if EHCI had them for ISO.
 416  */
 417 struct ehci_iso_stream {
 418         /* first field matches ehci_hq, but is NULL */
 419         struct ehci_qh_hw       *hw;
 420
 421         u32                     refcount;
 422         u8                      bEndpointAddress;
 423         u8                      highspeed;
 424         struct list_head        td_list;        /* queued itds/sitds */
 425         struct list_head        free_list;      /* list of unused itds/sitds */
 426         struct usb_device       *udev;
 427         struct usb_host_endpoint *ep;
 428
 429         /* output of (re)scheduling */
 430         int                     next_uframe;
 431         __hc32                  splits;
 432
 433         /* the rest is derived from the endpoint descriptor,
 434          * trusting urb->interval == f(epdesc->bInterval) and
 435          * including the extra info for hw_bufp[0..2]
 436          */
 437         u8                      usecs, c_usecs;
 438         u16                     interval;
 439         u16                     tt_usecs;
 440         u16                     maxp;
 441         u16                     raw_mask;
 442         unsigned                bandwidth;
 443
 444         /* This is used to initialize iTD's hw_bufp fields */
 445         __hc32                  buf0;
 446         __hc32                  buf1;
 447         __hc32                  buf2;
 448
 449         /* this is used to initialize sITD's tt info */
 450         __hc32                  address;
 451 };
 452
 453 /*-------------------------------------------------------------------------*/
 454
 455 /*
 456  * EHCI Specification 0.95 Section 3.3
 457  * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
 458  *
 459  * Schedule records for high speed iso xfers
 460  */
 461 struct ehci_itd {
 462         /* first part defined by EHCI spec */
 463         __hc32                  hw_next;           /* see EHCI 3.3.1 */
 464         __hc32                  hw_transaction [8]; /* see EHCI 3.3.2 */
 465 #define EHCI_ISOC_ACTIVE        (1<<31)        /* activate transfer this slot */
 466 #define EHCI_ISOC_BUF_ERR       (1<<30)        /* Data buffer error */
 467 #define EHCI_ISOC_BABBLE        (1<<29)        /* babble detected */
 468 #define EHCI_ISOC_XACTERR       (1<<28)        /* XactErr - transaction error */
 469 #define EHCI_ITD_LENGTH(tok)    (((tok)>>16) & 0x0fff)
 470 #define EHCI_ITD_IOC            (1 << 15)       /* interrupt on complete */
 471
 472 #define ITD_ACTIVE(ehci)        cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
 473
 474         __hc32                  hw_bufp [7];    /* see EHCI 3.3.3 */
 475         __hc32                  hw_bufp_hi [7]; /* Appendix B */
 476
 477         /* the rest is HCD-private */
 478         dma_addr_t              itd_dma;        /* for this itd */
 479         union ehci_shadow       itd_next;       /* ptr to periodic q entry */
 480
 481         struct urb              *urb;
 482         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 483         struct list_head        itd_list;       /* list of stream's itds */
 484
 485         /* any/all hw_transactions here may be used by that urb */
 486         unsigned                frame;          /* where scheduled */
 487         unsigned                pg;
 488         unsigned                index[8];       /* in urb->iso_frame_desc */
 489 } __attribute__ ((aligned (32)));
 490
 491 /*-------------------------------------------------------------------------*/
 492
 493 /*
 494  * EHCI Specification 0.95 Section 3.4
 495  * siTD, aka split-transaction isochronous Transfer Descriptor
 496  *       ... describe full speed iso xfers through TT in hubs
 497  * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
 498  */
 499 struct ehci_sitd {
 500         /* first part defined by EHCI spec */
 501         __hc32                  hw_next;
 502 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
 503         __hc32                  hw_fullspeed_ep;        /* EHCI table 3-9 */
 504         __hc32                  hw_uframe;              /* EHCI table 3-10 */
 505         __hc32                  hw_results;             /* EHCI table 3-11 */
 506 #define SITD_IOC        (1 << 31)       /* interrupt on completion */
 507 #define SITD_PAGE       (1 << 30)       /* buffer 0/1 */
 508 #define SITD_LENGTH(x)  (0x3ff & ((x)>>16))
 509 #define SITD_STS_ACTIVE (1 << 7)        /* HC may execute this */
 510 #define SITD_STS_ERR    (1 << 6)        /* error from TT */
 511 #define SITD_STS_DBE    (1 << 5)        /* data buffer error (in HC) */
 512 #define SITD_STS_BABBLE (1 << 4)        /* device was babbling */
 513 #define SITD_STS_XACT   (1 << 3)        /* illegal IN response */
 514 #define SITD_STS_MMF    (1 << 2)        /* incomplete split transaction */
 515 #define SITD_STS_STS    (1 << 1)        /* split transaction state */
 516
 517 #define SITD_ACTIVE(ehci)       cpu_to_hc32(ehci, SITD_STS_ACTIVE)
 518
 519         __hc32                  hw_buf [2];             /* EHCI table 3-12 */
 520         __hc32                  hw_backpointer;         /* EHCI table 3-13 */
 521         __hc32                  hw_buf_hi [2];          /* Appendix B */
 522
 523         /* the rest is HCD-private */
 524         dma_addr_t              sitd_dma;
 525         union ehci_shadow       sitd_next;      /* ptr to periodic q entry */
 526
 527         struct urb              *urb;
 528         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 529         struct list_head        sitd_list;      /* list of stream's sitds */
 530         unsigned                frame;
 531         unsigned                index;
 532 } __attribute__ ((aligned (32)));
 533
 534 /*-------------------------------------------------------------------------*/
 535
 536 /*
 537  * EHCI Specification 0.96 Section 3.7
 538  * Periodic Frame Span Traversal Node (FSTN)
 539  *
 540  * Manages split interrupt transactions (using TT) that span frame boundaries
 541  * into uframes 0/1; see 4.12.2.2.  In those uframes, a "save place" FSTN
 542  * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
 543  * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
 544  */
 545 struct ehci_fstn {
 546         __hc32                  hw_next;        /* any periodic q entry */
 547         __hc32                  hw_prev;        /* qh or EHCI_LIST_END */
 548
 549         /* the rest is HCD-private */
 550         dma_addr_t              fstn_dma;
 551         union ehci_shadow       fstn_next;      /* ptr to periodic q entry */
 552 } __attribute__ ((aligned (32)));
 553
 554 /*-------------------------------------------------------------------------*/
 555
 556 /* Prepare the PORTSC wakeup flags during controller suspend/resume */
 557
 558 #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup)      \
 559                 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup);
 560
 561 #define ehci_prepare_ports_for_controller_resume(ehci)                  \
 562                 ehci_adjust_port_wakeup_flags(ehci, false, false);
 563
 564 /*-------------------------------------------------------------------------*/
 565
 566 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
 567
 568 /*
 569  * Some EHCI controllers have a Transaction Translator built into the
 570  * root hub. This is a non-standard feature.  Each controller will need
 571  * to add code to the following inline functions, and call them as
 572  * needed (mostly in root hub code).
 573  */
 574
 575 #define ehci_is_TDI(e)                  (ehci_to_hcd(e)->has_tt)
 576
 577 /* Returns the speed of a device attached to a port on the root hub. */
 578 static inline unsigned int
 579 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
 580 {
 581         if (ehci_is_TDI(ehci)) {
 582                 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
 583                 case 0:
 584                         return 0;
 585                 case 1:
 586                         return USB_PORT_STAT_LOW_SPEED;
 587                 case 2:
 588                 default:
 589                         return USB_PORT_STAT_HIGH_SPEED;
 590                 }
 591         }
 592         return USB_PORT_STAT_HIGH_SPEED;
 593 }
 594
 595 #else
 596
 597 #define ehci_is_TDI(e)                  (0)
 598
 599 #define ehci_port_speed(ehci, portsc)   USB_PORT_STAT_HIGH_SPEED
 600 #endif
 601
 602 /*-------------------------------------------------------------------------*/
 603
 604 #ifdef CONFIG_PPC_83xx
 605 /* Some Freescale processors have an erratum in which the TT
 606  * port number in the queue head was 0..N-1 instead of 1..N.
 607  */
 608 #define ehci_has_fsl_portno_bug(e)              ((e)->has_fsl_port_bug)
 609 #else
 610 #define ehci_has_fsl_portno_bug(e)              (0)
 611 #endif
 612
 613 /*
 614  * While most USB host controllers implement their registers in
 615  * little-endian format, a minority (celleb companion chip) implement
 616  * them in big endian format.
 617  *
 618  * This attempts to support either format at compile time without a
 619  * runtime penalty, or both formats with the additional overhead
 620  * of checking a flag bit.
 621  *
 622  * ehci_big_endian_capbase is a special quirk for controllers that
 623  * implement the HC capability registers as separate registers and not
 624  * as fields of a 32-bit register.
 625  */
 626
 627 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 628 #define ehci_big_endian_mmio(e)         ((e)->big_endian_mmio)
 629 #define ehci_big_endian_capbase(e)      ((e)->big_endian_capbase)
 630 #else
 631 #define ehci_big_endian_mmio(e)         0
 632 #define ehci_big_endian_capbase(e)      0
 633 #endif
 634
 635 /*
 636  * Big-endian read/write functions are arch-specific.
 637  * Other arches can be added if/when they're needed.
 638  */
 639 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
 640 #define readl_be(addr)          __raw_readl((__force unsigned *)addr)
 641 #define writel_be(val, addr)    __raw_writel(val, (__force unsigned *)addr)
 642 #endif
 643
 644 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
 645                 __u32 __iomem * regs)
 646 {
 647 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 648         return ehci_big_endian_mmio(ehci) ?
 649                 readl_be(regs) :
 650                 readl(regs);
 651 #else
 652         return readl(regs);
 653 #endif
 654 }
 655
 656 static inline void ehci_writel(const struct ehci_hcd *ehci,
 657                 const unsigned int val, __u32 __iomem *regs)
 658 {
 659 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 660         ehci_big_endian_mmio(ehci) ?
 661                 writel_be(val, regs) :
 662                 writel(val, regs);
 663 #else
 664         writel(val, regs);
 665 #endif
 666 }
 667
 668 /*
 669  * On certain ppc-44x SoC there is a HW issue, that could only worked around with
 670  * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch.
 671  * Other common bits are dependent on has_amcc_usb23 quirk flag.
 672  */
 673 #ifdef CONFIG_44x
 674 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
 675 {
 676         u32 hc_control;
 677
 678         hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);
 679         if (operational)
 680                 hc_control |= OHCI_USB_OPER;
 681         else
 682                 hc_control |= OHCI_USB_SUSPEND;
 683
 684         writel_be(hc_control, ehci->ohci_hcctrl_reg);
 685         (void) readl_be(ehci->ohci_hcctrl_reg);
 686 }
 687 #else
 688 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
 689 { }
 690 #endif
 691
 692 /*-------------------------------------------------------------------------*/
 693
 694 /*
 695  * The AMCC 440EPx not only implements its EHCI registers in big-endian
 696  * format, but also its DMA data structures (descriptors).
 697  *
 698  * EHCI controllers accessed through PCI work normally (little-endian
 699  * everywhere), so we won't bother supporting a BE-only mode for now.
 700  */
 701 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
 702 #define ehci_big_endian_desc(e)         ((e)->big_endian_desc)
 703
 704 /* cpu to ehci */
 705 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
 706 {
 707         return ehci_big_endian_desc(ehci)
 708                 ? (__force __hc32)cpu_to_be32(x)
 709                 : (__force __hc32)cpu_to_le32(x);
 710 }
 711
 712 /* ehci to cpu */
 713 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
 714 {
 715         return ehci_big_endian_desc(ehci)
 716                 ? be32_to_cpu((__force __be32)x)
 717                 : le32_to_cpu((__force __le32)x);
 718 }
 719
 720 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
 721 {
 722         return ehci_big_endian_desc(ehci)
 723                 ? be32_to_cpup((__force __be32 *)x)
 724                 : le32_to_cpup((__force __le32 *)x);
 725 }
 726
 727 #else
 728
 729 /* cpu to ehci */
 730 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
 731 {
 732         return cpu_to_le32(x);
 733 }
 734
 735 /* ehci to cpu */
 736 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
 737 {
 738         return le32_to_cpu(x);
 739 }
 740
 741 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
 742 {
 743         return le32_to_cpup(x);
 744 }
 745
 746 #endif
 747
 748 /*-------------------------------------------------------------------------*/
 749
 750 #ifndef DEBUG
 751 #define STUB_DEBUG_FILES
 752 #endif  /* DEBUG */
 753
 754 /*-------------------------------------------------------------------------*/
 755
 756 #endif /* __LINUX_EHCI_HCD_H */