include/linux/fsl-diu-fb.h

   1 /*
   2  * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
   3  *
   4  *  Freescale DIU Frame Buffer device driver
   5  *
   6  *  Authors: Hongjun Chen <hong-jun.chen@freescale.com>
   7  *           Paul Widmer <paul.widmer@freescale.com>
   8  *           Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
   9  *           York Sun <yorksun@freescale.com>
  10  *
  11  *   Based on imxfb.c Copyright (C) 2004 S.Hauer, Pengutronix
  12  *
  13  * This program is free software; you can redistribute  it and/or modify it
  14  * under  the terms of  the GNU General  Public License as published by the
  15  * Free Software Foundation;  either version 2 of the  License, or (at your
  16  * option) any later version.
  17  *
  18  */
  19
  20 #ifndef __FSL_DIU_FB_H__
  21 #define __FSL_DIU_FB_H__
  22
  23 /* Arbitrary threshold to determine the allocation method
  24  * See mpc8610fb_set_par(), map_video_memory(), and unmap_video_memory()
  25  */
  26 #define MEM_ALLOC_THRESHOLD (1024*768*4+32)
  27
  28 #include <linux/types.h>
  29
  30 struct mfb_alpha {
  31         int enable;
  32         int alpha;
  33 };
  34
  35 struct mfb_chroma_key {
  36         int enable;
  37         __u8  red_max;
  38         __u8  green_max;
  39         __u8  blue_max;
  40         __u8  red_min;
  41         __u8  green_min;
  42         __u8  blue_min;
  43 };
  44
  45 struct aoi_display_offset {
  46         int x_aoi_d;
  47         int y_aoi_d;
  48 };
  49
  50 #define MFB_SET_CHROMA_KEY      _IOW('M', 1, struct mfb_chroma_key)
  51 #define MFB_SET_BRIGHTNESS      _IOW('M', 3, __u8)
  52
  53 #define MFB_SET_ALPHA           0x80014d00
  54 #define MFB_GET_ALPHA           0x40014d00
  55 #define MFB_SET_AOID            0x80084d04
  56 #define MFB_GET_AOID            0x40084d04
  57 #define MFB_SET_PIXFMT          0x80014d08
  58 #define MFB_GET_PIXFMT          0x40014d08
  59
  60 #define FBIOGET_GWINFO          0x46E0
  61 #define FBIOPUT_GWINFO          0x46E1
  62
  63 #ifdef __KERNEL__
  64 #include <linux/spinlock.h>
  65
  66 /*
  67  * These are the fields of area descriptor(in DDR memory) for every plane
  68  */
  69 struct diu_ad {
  70         /* Word 0(32-bit) in DDR memory */
  71 /*      __u16 comp; */
  72 /*      __u16 pixel_s:2; */
  73 /*      __u16 pallete:1; */
  74 /*      __u16 red_c:2; */
  75 /*      __u16 green_c:2; */
  76 /*      __u16 blue_c:2; */
  77 /*      __u16 alpha_c:3; */
  78 /*      __u16 byte_f:1; */
  79 /*      __u16 res0:3; */
  80
  81         __be32 pix_fmt; /* hard coding pixel format */
  82
  83         /* Word 1(32-bit) in DDR memory */
  84         __le32 addr;
  85
  86         /* Word 2(32-bit) in DDR memory */
  87 /*      __u32 delta_xs:11; */
  88 /*      __u32 res1:1; */
  89 /*      __u32 delta_ys:11; */
  90 /*      __u32 res2:1; */
  91 /*      __u32 g_alpha:8; */
  92         __le32 src_size_g_alpha;
  93
  94         /* Word 3(32-bit) in DDR memory */
  95 /*      __u32 delta_xi:11; */
  96 /*      __u32 res3:5; */
  97 /*      __u32 delta_yi:11; */
  98 /*      __u32 res4:3; */
  99 /*      __u32 flip:2; */
 100         __le32 aoi_size;
 101
 102         /* Word 4(32-bit) in DDR memory */
 103         /*__u32 offset_xi:11;
 104         __u32 res5:5;
 105         __u32 offset_yi:11;
 106         __u32 res6:5;
 107         */
 108         __le32 offset_xyi;
 109
 110         /* Word 5(32-bit) in DDR memory */
 111         /*__u32 offset_xd:11;
 112         __u32 res7:5;
 113         __u32 offset_yd:11;
 114         __u32 res8:5; */
 115         __le32 offset_xyd;
 116
 117
 118         /* Word 6(32-bit) in DDR memory */
 119         __u8 ckmax_r;
 120         __u8 ckmax_g;
 121         __u8 ckmax_b;
 122         __u8 res9;
 123
 124         /* Word 7(32-bit) in DDR memory */
 125         __u8 ckmin_r;
 126         __u8 ckmin_g;
 127         __u8 ckmin_b;
 128         __u8 res10;
 129 /*      __u32 res10:8; */
 130
 131         /* Word 8(32-bit) in DDR memory */
 132         __le32 next_ad;
 133
 134         /* Word 9(32-bit) in DDR memory, just for 64-bit aligned */
 135         __u32 paddr;
 136 } __attribute__ ((packed));
 137
 138 /* DIU register map */
 139 struct diu {
 140         __be32 desc[3];
 141         __be32 gamma;
 142         __be32 pallete;
 143         __be32 cursor;
 144         __be32 curs_pos;
 145         __be32 diu_mode;
 146         __be32 bgnd;
 147         __be32 bgnd_wb;
 148         __be32 disp_size;
 149         __be32 wb_size;
 150         __be32 wb_mem_addr;
 151         __be32 hsyn_para;
 152         __be32 vsyn_para;
 153         __be32 syn_pol;
 154         __be32 thresholds;
 155         __be32 int_status;
 156         __be32 int_mask;
 157         __be32 colorbar[8];
 158         __be32 filling;
 159         __be32 plut;
 160 } __attribute__ ((packed));
 161
 162 struct diu_hw {
 163         struct diu *diu_reg;
 164         spinlock_t reg_lock;
 165
 166         __u32 mode;             /* DIU operation mode */
 167 };
 168
 169 struct diu_addr {
 170         __u8 __iomem *vaddr;    /* Virtual address */
 171         dma_addr_t paddr;       /* Physical address */
 172         __u32      offset;
 173 };
 174
 175 struct diu_pool {
 176         struct diu_addr ad;
 177         struct diu_addr gamma;
 178         struct diu_addr pallete;
 179         struct diu_addr cursor;
 180 };
 181
 182 #define FSL_DIU_BASE_OFFSET     0x2C000 /* Offset of DIU */
 183 #define INT_LCDC                64      /* DIU interrupt number */
 184
 185 #define FSL_AOI_NUM     6       /* 5 AOIs and one dummy AOI */
 186                                 /* 1 for plane 0, 2 for plane 1&2 each */
 187
 188 /* Minimum X and Y resolutions */
 189 #define MIN_XRES        64
 190 #define MIN_YRES        64
 191
 192 /* HW cursor parameters */
 193 #define MAX_CURS                32
 194
 195 /* Modes of operation of DIU */
 196 #define MFB_MODE0       0       /* DIU off */
 197 #define MFB_MODE1       1       /* All three planes output to display */
 198 #define MFB_MODE2       2       /* Plane 1 to display, planes 2+3 written back*/
 199 #define MFB_MODE3       3       /* All three planes written back to memory */
 200 #define MFB_MODE4       4       /* Color bar generation */
 201
 202 /* INT_STATUS/INT_MASK field descriptions */
 203 #define INT_VSYNC       0x01    /* Vsync interrupt  */
 204 #define INT_VSYNC_WB    0x02    /* Vsync interrupt for write back operation */
 205 #define INT_UNDRUN      0x04    /* Under run exception interrupt */
 206 #define INT_PARERR      0x08    /* Display parameters error interrupt */
 207 #define INT_LS_BF_VS    0x10    /* Lines before vsync. interrupt */
 208
 209 /* Panels'operation modes */
 210 #define MFB_TYPE_OUTPUT 0       /* Panel output to display */
 211 #define MFB_TYPE_OFF    1       /* Panel off */
 212 #define MFB_TYPE_WB     2       /* Panel written back to memory */
 213 #define MFB_TYPE_TEST   3       /* Panel generate color bar */
 214
 215 #endif /* __KERNEL__ */
 216 #endif /* __FSL_DIU_FB_H__ */