include/linux/mfd/twl6040.h

   1 /*
   2  * MFD driver for twl6040
   3  *
   4  * Authors:     Jorge Eduardo Candelaria <jorge.candelaria@ti.com>
   5  *              Misael Lopez Cruz <misael.lopez@ti.com>
   6  *
   7  * Copyright:   (C) 2011 Texas Instruments, Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  21  * 02110-1301 USA
  22  *
  23  */
  24
  25 #ifndef __TWL6040_CODEC_H__
  26 #define __TWL6040_CODEC_H__
  27
  28 #include <linux/interrupt.h>
  29 #include <linux/mfd/core.h>
  30
  31 #define TWL6040_REG_ASICID              0x01
  32 #define TWL6040_REG_ASICREV             0x02
  33 #define TWL6040_REG_INTID               0x03
  34 #define TWL6040_REG_INTMR               0x04
  35 #define TWL6040_REG_NCPCTL              0x05
  36 #define TWL6040_REG_LDOCTL              0x06
  37 #define TWL6040_REG_HPPLLCTL            0x07
  38 #define TWL6040_REG_LPPLLCTL            0x08
  39 #define TWL6040_REG_LPPLLDIV            0x09
  40 #define TWL6040_REG_AMICBCTL            0x0A
  41 #define TWL6040_REG_DMICBCTL            0x0B
  42 #define TWL6040_REG_MICLCTL             0x0C
  43 #define TWL6040_REG_MICRCTL             0x0D
  44 #define TWL6040_REG_MICGAIN             0x0E
  45 #define TWL6040_REG_LINEGAIN            0x0F
  46 #define TWL6040_REG_HSLCTL              0x10
  47 #define TWL6040_REG_HSRCTL              0x11
  48 #define TWL6040_REG_HSGAIN              0x12
  49 #define TWL6040_REG_EARCTL              0x13
  50 #define TWL6040_REG_HFLCTL              0x14
  51 #define TWL6040_REG_HFLGAIN             0x15
  52 #define TWL6040_REG_HFRCTL              0x16
  53 #define TWL6040_REG_HFRGAIN             0x17
  54 #define TWL6040_REG_VIBCTLL             0x18
  55 #define TWL6040_REG_VIBDATL             0x19
  56 #define TWL6040_REG_VIBCTLR             0x1A
  57 #define TWL6040_REG_VIBDATR             0x1B
  58 #define TWL6040_REG_HKCTL1              0x1C
  59 #define TWL6040_REG_HKCTL2              0x1D
  60 #define TWL6040_REG_GPOCTL              0x1E
  61 #define TWL6040_REG_ALB                 0x1F
  62 #define TWL6040_REG_DLB                 0x20
  63 #define TWL6040_REG_TRIM1               0x28
  64 #define TWL6040_REG_TRIM2               0x29
  65 #define TWL6040_REG_TRIM3               0x2A
  66 #define TWL6040_REG_HSOTRIM             0x2B
  67 #define TWL6040_REG_HFOTRIM             0x2C
  68 #define TWL6040_REG_ACCCTL              0x2D
  69 #define TWL6040_REG_STATUS              0x2E
  70
  71 #define TWL6040_CACHEREGNUM             (TWL6040_REG_STATUS + 1)
  72
  73 #define TWL6040_VIOREGNUM               18
  74 #define TWL6040_VDDREGNUM               21
  75
  76 /* INTID (0x03) fields */
  77
  78 #define TWL6040_THINT                   0x01
  79 #define TWL6040_PLUGINT                 0x02
  80 #define TWL6040_UNPLUGINT               0x04
  81 #define TWL6040_HOOKINT                 0x08
  82 #define TWL6040_HFINT                   0x10
  83 #define TWL6040_VIBINT                  0x20
  84 #define TWL6040_READYINT                0x40
  85
  86 /* INTMR (0x04) fields */
  87
  88 #define TWL6040_THMSK                   0x01
  89 #define TWL6040_PLUGMSK                 0x02
  90 #define TWL6040_HOOKMSK                 0x08
  91 #define TWL6040_HFMSK                   0x10
  92 #define TWL6040_VIBMSK                  0x20
  93 #define TWL6040_READYMSK                0x40
  94 #define TWL6040_ALLINT_MSK              0x7B
  95
  96 /* NCPCTL (0x05) fields */
  97
  98 #define TWL6040_NCPENA                  0x01
  99 #define TWL6040_NCPOPEN                 0x40
 100
 101 /* LDOCTL (0x06) fields */
 102
 103 #define TWL6040_LSLDOENA                0x01
 104 #define TWL6040_HSLDOENA                0x04
 105 #define TWL6040_REFENA                  0x40
 106 #define TWL6040_OSCENA                  0x80
 107
 108 /* HPPLLCTL (0x07) fields */
 109
 110 #define TWL6040_HPLLENA                 0x01
 111 #define TWL6040_HPLLRST                 0x02
 112 #define TWL6040_HPLLBP                  0x04
 113 #define TWL6040_HPLLSQRENA              0x08
 114 #define TWL6040_MCLK_12000KHZ           (0 << 5)
 115 #define TWL6040_MCLK_19200KHZ           (1 << 5)
 116 #define TWL6040_MCLK_26000KHZ           (2 << 5)
 117 #define TWL6040_MCLK_38400KHZ           (3 << 5)
 118 #define TWL6040_MCLK_MSK                0x60
 119
 120 /* LPPLLCTL (0x08) fields */
 121
 122 #define TWL6040_LPLLENA                 0x01
 123 #define TWL6040_LPLLRST                 0x02
 124 #define TWL6040_LPLLSEL                 0x04
 125 #define TWL6040_LPLLFIN                 0x08
 126 #define TWL6040_HPLLSEL                 0x10
 127
 128 /* HSLCTL (0x10) fields */
 129
 130 #define TWL6040_HSDACMODEL              0x02
 131 #define TWL6040_HSDRVMODEL              0x08
 132
 133 /* HSRCTL (0x11) fields */
 134
 135 #define TWL6040_HSDACMODER              0x02
 136 #define TWL6040_HSDRVMODER              0x08
 137
 138 /* VIBCTLL (0x18) fields */
 139
 140 #define TWL6040_VIBENAL                 0x01
 141 #define TWL6040_VIBCTRLL                0x04
 142 #define TWL6040_VIBCTRLLP               0x08
 143 #define TWL6040_VIBCTRLLN               0x10
 144
 145 /* VIBDATL (0x19) fields */
 146
 147 #define TWL6040_VIBDAT_MAX              0x64
 148
 149 /* VIBCTLR (0x1A) fields */
 150
 151 #define TWL6040_VIBENAR                 0x01
 152 #define TWL6040_VIBCTRLR                0x04
 153 #define TWL6040_VIBCTRLRP               0x08
 154 #define TWL6040_VIBCTRLRN               0x10
 155
 156 /* GPOCTL (0x1E) fields */
 157
 158 #define TWL6040_GPO1                    0x01
 159 #define TWL6040_GPO2                    0x02
 160 #define TWL6040_GPO3                    0x03
 161
 162 /* ACCCTL (0x2D) fields */
 163
 164 #define TWL6040_I2CSEL                  0x01
 165 #define TWL6040_RESETSPLIT              0x04
 166 #define TWL6040_INTCLRMODE              0x08
 167
 168 /* STATUS (0x2E) fields */
 169
 170 #define TWL6040_PLUGCOMP                0x02
 171 #define TWL6040_VIBLOCDET               0x10
 172 #define TWL6040_VIBROCDET               0x20
 173 #define TWL6040_TSHUTDET                0x40
 174
 175 #define TWL6040_CELLS                   2
 176
 177 #define TWL6040_REV_ES1_0               0x00
 178 #define TWL6040_REV_ES1_1               0x01
 179 #define TWL6040_REV_ES1_2               0x02
 180
 181 #define TWL6040_IRQ_TH                  0
 182 #define TWL6040_IRQ_PLUG                1
 183 #define TWL6040_IRQ_HOOK                2
 184 #define TWL6040_IRQ_HF                  3
 185 #define TWL6040_IRQ_VIB                 4
 186 #define TWL6040_IRQ_READY               5
 187
 188 /* PLL selection */
 189 #define TWL6040_SYSCLK_SEL_LPPLL        0
 190 #define TWL6040_SYSCLK_SEL_HPPLL        1
 191
 192 struct twl6040 {
 193         struct device *dev;
 194         struct mutex mutex;
 195         struct mutex io_mutex;
 196         struct mutex irq_mutex;
 197         struct mfd_cell cells[TWL6040_CELLS];
 198         struct completion ready;
 199
 200         int audpwron;
 201         int power_count;
 202         int rev;
 203
 204         int pll;
 205         unsigned int sysclk;
 206
 207         unsigned int irq;
 208         unsigned int irq_base;
 209         u8 irq_masks_cur;
 210         u8 irq_masks_cache;
 211 };
 212
 213 int twl6040_reg_read(struct twl6040 *twl6040, unsigned int reg);
 214 int twl6040_reg_write(struct twl6040 *twl6040, unsigned int reg,
 215                       u8 val);
 216 int twl6040_set_bits(struct twl6040 *twl6040, unsigned int reg,
 217                      u8 mask);
 218 int twl6040_clear_bits(struct twl6040 *twl6040, unsigned int reg,
 219                        u8 mask);
 220 int twl6040_power(struct twl6040 *twl6040, int on);
 221 int twl6040_set_pll(struct twl6040 *twl6040, int pll_id,
 222                     unsigned int freq_in, unsigned int freq_out);
 223 int twl6040_get_pll(struct twl6040 *twl6040);
 224 unsigned int twl6040_get_sysclk(struct twl6040 *twl6040);
 225 int twl6040_irq_init(struct twl6040 *twl6040);
 226 void twl6040_irq_exit(struct twl6040 *twl6040);
 227
 228 #endif  /* End of __TWL6040_CODEC_H__ */