drivers/staging/winbond/wbhal.h

   1 #ifndef __WINBOND_WBHAL_S_H
   2 #define __WINBOND_WBHAL_S_H
   3
   4 #include <linux/types.h>
   5 #include <linux/if_ether.h> /* for ETH_ALEN */
   6
   7 #define HAL_LED_SET_MASK        0x001c
   8 #define HAL_LED_SET_SHIFT       2
   9
  10 /* supported RF type */
  11 #define RF_MAXIM_2825           0
  12 #define RF_MAXIM_2827           1
  13 #define RF_MAXIM_2828           2
  14 #define RF_MAXIM_2829           3
  15 #define RF_MAXIM_V1             15
  16 #define RF_AIROHA_2230          16
  17 #define RF_AIROHA_7230          17
  18 #define RF_AIROHA_2230S         18
  19 #define RF_WB_242               33
  20 #define RF_WB_242_1             34
  21 #define RF_DECIDE_BY_INF        255
  22
  23 /*
  24  * ----------------------------------------------------------------
  25  * The follow define connect to upper layer
  26  *      User must modify for connection between HAL and upper layer
  27  * ----------------------------------------------------------------
  28  */
  29
  30 /*
  31  * ==============================
  32  * Common define
  33  * ==============================
  34  */
  35 /* Bit 5 */
  36 #define HAL_USB_MODE_BURST(_H)                  (_H->SoftwareSet & 0x20)
  37
  38 /* Scan interval */
  39 #define SCAN_MAX_CHNL_TIME                      (50)
  40
  41 /* For TxL2 Frame typr recognise */
  42 #define FRAME_TYPE_802_3_DATA                   0
  43 #define FRAME_TYPE_802_11_MANAGEMENT            1
  44 #define FRAME_TYPE_802_11_MANAGEMENT_CHALLENGE  2
  45 #define FRAME_TYPE_802_11_CONTROL               3
  46 #define FRAME_TYPE_802_11_DATA                  4
  47 #define FRAME_TYPE_PROMISCUOUS                  5
  48
  49 /* The follow definition is used for convert the frame------------ */
  50 #define DOT_11_SEQUENCE_OFFSET                  22 /* Sequence control offset */
  51 #define DOT_3_TYPE_OFFSET                       12
  52 #define DOT_11_MAC_HEADER_SIZE                  24
  53 #define DOT_11_SNAP_SIZE                        6
  54 #define DOT_11_TYPE_OFFSET                      30 /* The start offset of 802.11 Frame. Type encapsulation. */
  55 #define DEFAULT_SIFSTIME                        10
  56 #define DEFAULT_FRAGMENT_THRESHOLD              2346 /* No fragment */
  57 #define DEFAULT_MSDU_LIFE_TIME                  0xffff
  58
  59 #define LONG_PREAMBLE_PLUS_PLCPHEADER_TIME              (144 + 48)
  60 #define SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME             (72 + 24)
  61 #define PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION       (16 + 4 + 6)
  62 #define Tsym                                            4
  63
  64 /*  Frame Type of Bits (2, 3)----------------------------------- */
  65 #define MAC_TYPE_MANAGEMENT                     0x00
  66 #define MAC_TYPE_CONTROL                        0x04
  67 #define MAC_TYPE_DATA                           0x08
  68 #define MASK_FRAGMENT_NUMBER                    0x000F
  69 #define SEQUENCE_NUMBER_SHIFT                   4
  70
  71 #define  HAL_WOL_TYPE_WAKEUP_FRAME              0x01
  72 #define  HAL_WOL_TYPE_MAGIC_PACKET              0x02
  73
  74 #define HAL_KEYTYPE_WEP40                       0
  75 #define HAL_KEYTYPE_WEP104                      1
  76 #define HAL_KEYTYPE_TKIP                        2 /* 128 bit key */
  77 #define HAL_KEYTYPE_AES_CCMP                    3 /* 128 bit key */
  78
  79 /* For VM state */
  80 enum {
  81         VM_STOP = 0,
  82         VM_RUNNING,
  83         VM_COMPLETED
  84 };
  85
  86 /*
  87  * ================================
  88  * Normal Key table format
  89  * ================================
  90  */
  91
  92 /* The order of KEY index is MAPPING_KEY_START_INDEX > GROUP_KEY_START_INDEX */
  93 #define MAX_KEY_TABLE                   24 /* 24 entry for storing key data */
  94 #define GROUP_KEY_START_INDEX           4
  95 #define MAPPING_KEY_START_INDEX         8
  96
  97 /*
  98  * =========================================
  99  * Descriptor
 100  * =========================================
 101  */
 102 #define MAX_DESCRIPTOR_BUFFER_INDEX     8 /* Have to multiple of 2 */
 103 #define FLAG_ERROR_TX_MASK              0x000000bf
 104 #define FLAG_ERROR_RX_MASK              0x0000083f
 105
 106 #define FLAG_BAND_RX_MASK               0x10000000 /* Bit 28 */
 107
 108 struct R00_descriptor {
 109         union {
 110                 u32     value;
 111 #ifdef _BIG_ENDIAN_
 112                 struct {
 113                         u32     R00_packet_or_buffer_status:1;
 114                         u32     R00_packet_in_fifo:1;
 115                         u32     R00_RESERVED:2;
 116                         u32     R00_receive_byte_count:12;
 117                         u32     R00_receive_time_index:16;
 118                 };
 119 #else
 120                 struct {
 121                         u32     R00_receive_time_index:16;
 122                         u32     R00_receive_byte_count:12;
 123                         u32     R00_RESERVED:2;
 124                         u32     R00_packet_in_fifo:1;
 125                         u32     R00_packet_or_buffer_status:1;
 126                 };
 127 #endif
 128         };
 129 };
 130
 131 struct T00_descriptor {
 132         union {
 133                 u32     value;
 134 #ifdef _BIG_ENDIAN_
 135                 struct {
 136                         u32     T00_first_mpdu:1; /* for hardware use */
 137                         u32     T00_last_mpdu:1; /* for hardware use */
 138                         u32     T00_IsLastMpdu:1;/* 0:not 1:Yes for software used */
 139                         u32     T00_IgnoreResult:1;/* The same mechanism with T00 setting. */
 140                         u32     T00_RESERVED_ID:2;/* 3 bit ID reserved */
 141                         u32     T00_tx_packet_id:4;
 142                         u32     T00_RESERVED:4;
 143                         u32     T00_header_length:6;
 144                         u32     T00_frame_length:12;
 145                 };
 146 #else
 147                 struct {
 148                         u32     T00_frame_length:12;
 149                         u32     T00_header_length:6;
 150                         u32     T00_RESERVED:4;
 151                         u32     T00_tx_packet_id:4;
 152                         u32     T00_RESERVED_ID:2; /* 3 bit ID reserved */
 153                         u32     T00_IgnoreResult:1; /* The same mechanism with T00 setting. */
 154                         u32     T00_IsLastMpdu:1; /* 0:not 1:Yes for software used */
 155                         u32     T00_last_mpdu:1; /* for hardware use */
 156                         u32     T00_first_mpdu:1; /* for hardware use */
 157                 };
 158 #endif
 159         };
 160 };
 161
 162 struct R01_descriptor {
 163         union {
 164                 u32     value;
 165 #ifdef _BIG_ENDIAN_
 166                 struct {
 167                         u32     R01_RESERVED:3;
 168                         u32     R01_mod_type:1;
 169                         u32     R01_pre_type:1;
 170                         u32     R01_data_rate:3;
 171                         u32     R01_AGC_state:8;
 172                         u32     R01_LNA_state:2;
 173                         u32     R01_decryption_method:2;
 174                         u32     R01_mic_error:1;
 175                         u32     R01_replay:1;
 176                         u32     R01_broadcast_frame:1;
 177                         u32     R01_multicast_frame:1;
 178                         u32     R01_directed_frame:1;
 179                         u32     R01_receive_frame_antenna_selection:1;
 180                         u32     R01_frame_receive_during_atim_window:1;
 181                         u32     R01_protocol_version_error:1;
 182                         u32     R01_authentication_frame_icv_error:1;
 183                         u32     R01_null_key_to_authentication_frame:1;
 184                         u32     R01_icv_error:1;
 185                         u32     R01_crc_error:1;
 186                 };
 187 #else
 188                 struct {
 189                         u32     R01_crc_error:1;
 190                         u32     R01_icv_error:1;
 191                         u32     R01_null_key_to_authentication_frame:1;
 192                         u32     R01_authentication_frame_icv_error:1;
 193                         u32     R01_protocol_version_error:1;
 194                         u32     R01_frame_receive_during_atim_window:1;
 195                         u32     R01_receive_frame_antenna_selection:1;
 196                         u32     R01_directed_frame:1;
 197                         u32     R01_multicast_frame:1;
 198                         u32     R01_broadcast_frame:1;
 199                         u32     R01_replay:1;
 200                         u32     R01_mic_error:1;
 201                         u32     R01_decryption_method:2;
 202                         u32     R01_LNA_state:2;
 203                         u32     R01_AGC_state:8;
 204                         u32     R01_data_rate:3;
 205                         u32     R01_pre_type:1;
 206                         u32     R01_mod_type:1;
 207                         u32     R01_RESERVED:3;
 208                 };
 209 #endif
 210         };
 211 };
 212
 213 struct T01_descriptor {
 214         union {
 215                 u32     value;
 216 #ifdef _BIG_ENDIAN_
 217                 struct {
 218                         u32     T01_rts_cts_duration:16;
 219                         u32     T01_fall_back_rate:3;
 220                         u32     T01_add_rts:1;
 221                         u32     T01_add_cts:1;
 222                         u32     T01_modulation_type:1;
 223                         u32     T01_plcp_header_length:1;
 224                         u32     T01_transmit_rate:3;
 225                         u32     T01_wep_id:2;
 226                         u32     T01_add_challenge_text:1;
 227                         u32     T01_inhibit_crc:1;
 228                         u32     T01_loop_back_wep_mode:1;
 229                         u32     T01_retry_abort_ebable:1;
 230                 };
 231 #else
 232                 struct {
 233                         u32     T01_retry_abort_ebable:1;
 234                         u32     T01_loop_back_wep_mode:1;
 235                         u32     T01_inhibit_crc:1;
 236                         u32     T01_add_challenge_text:1;
 237                         u32     T01_wep_id:2;
 238                         u32     T01_transmit_rate:3;
 239                         u32     T01_plcp_header_length:1;
 240                         u32     T01_modulation_type:1;
 241                         u32     T01_add_cts:1;
 242                         u32     T01_add_rts:1;
 243                         u32     T01_fall_back_rate:3;
 244                         u32     T01_rts_cts_duration:16;
 245                 };
 246 #endif
 247         };
 248 };
 249
 250 struct T02_descriptor {
 251         union {
 252                 u32     value;
 253 #ifdef _BIG_ENDIAN_
 254                 struct {
 255                         u32     T02_IsLastMpdu:1; /* The same mechanism with T00 setting */
 256                         u32     T02_IgnoreResult:1; /* The same mechanism with T00 setting. */
 257                         u32     T02_RESERVED_ID:2; /* The same mechanism with T00 setting */
 258                         u32     T02_Tx_PktID:4;
 259                         u32     T02_MPDU_Cnt:4;
 260                         u32     T02_RTS_Cnt:4;
 261                         u32     T02_RESERVED:7;
 262                         u32     T02_transmit_complete:1;
 263                         u32     T02_transmit_abort_due_to_TBTT:1;
 264                         u32     T02_effective_transmission_rate:1;
 265                         u32     T02_transmit_without_encryption_due_to_wep_on_false:1;
 266                         u32     T02_discard_due_to_null_wep_key:1;
 267                         u32     T02_RESERVED_1:1;
 268                         u32     T02_out_of_MaxTxMSDULiftTime:1;
 269                         u32     T02_transmit_abort:1;
 270                         u32     T02_transmit_fail:1;
 271                 };
 272 #else
 273                 struct {
 274                         u32     T02_transmit_fail:1;
 275                         u32     T02_transmit_abort:1;
 276                         u32     T02_out_of_MaxTxMSDULiftTime:1;
 277                         u32     T02_RESERVED_1:1;
 278                         u32     T02_discard_due_to_null_wep_key:1;
 279                         u32     T02_transmit_without_encryption_due_to_wep_on_false:1;
 280                         u32     T02_effective_transmission_rate:1;
 281                         u32     T02_transmit_abort_due_to_TBTT:1;
 282                         u32     T02_transmit_complete:1;
 283                         u32     T02_RESERVED:7;
 284                         u32     T02_RTS_Cnt:4;
 285                         u32     T02_MPDU_Cnt:4;
 286                         u32     T02_Tx_PktID:4;
 287                         u32     T02_RESERVED_ID:2; /* The same mechanism with T00 setting */
 288                         u32     T02_IgnoreResult:1; /* The same mechanism with T00 setting. */
 289                         u32     T02_IsLastMpdu:1; /* The same mechanism with T00 setting */
 290                 };
 291 #endif
 292         };
 293 };
 294
 295 struct wb35_descriptor { /* Skip length = 8 DWORD */
 296         /* ID for descriptor ---, The field doesn't be cleard in the operation of Descriptor definition */
 297         u8      Descriptor_ID;
 298         /* ----------------------The above region doesn't be cleared by DESCRIPTOR_RESET------ */
 299         u8      RESERVED[3];
 300
 301         u16     FragmentThreshold;
 302         u8      InternalUsed; /* Only can be used by operation of descriptor definition */
 303         u8      Type; /* 0: 802.3 1:802.11 data frame 2:802.11 management frame */
 304
 305         u8      PreambleMode;/* 0: short 1:long */
 306         u8      TxRate;
 307         u8      FragmentCount;
 308         u8      EapFix; /* For speed up key install */
 309
 310         /* For R00 and T00 ------------------------------ */
 311         union {
 312                 struct R00_descriptor   R00;
 313                 struct T00_descriptor   T00;
 314         };
 315
 316         /* For R01 and T01 ------------------------------ */
 317         union {
 318                 struct R01_descriptor   R01;
 319                 struct T01_descriptor   T01;
 320         };
 321
 322         /* For R02 and T02 ------------------------------ */
 323         union {
 324                 u32             R02;
 325                 struct T02_descriptor   T02;
 326         };
 327
 328         /* For R03 and T03 ------------------------------ */
 329         /* For software used */
 330         union {
 331                 u32     R03;
 332                 u32     T03;
 333                 struct {
 334                         u8      buffer_number;
 335                         u8      buffer_start_index;
 336                         u16     buffer_total_size;
 337                 };
 338         };
 339
 340         /* For storing the buffer */
 341         u16     buffer_size[MAX_DESCRIPTOR_BUFFER_INDEX];
 342         void    *buffer_address[MAX_DESCRIPTOR_BUFFER_INDEX];
 343 };
 344
 345 #define MAX_TXVGA_EEPROM                9       /* How many word(u16) of EEPROM will be used for TxVGA */
 346 #define MAX_RF_PARAMETER                32
 347
 348 struct txvga_for_50 {
 349         u8      ChanNo;
 350         u8      TxVgaValue;
 351 };
 352
 353 /*
 354  * ==============================================
 355  * Device related include
 356  * ==============================================
 357  */
 358
 359 #include "wb35reg_s.h"
 360 #include "wb35tx_s.h"
 361 #include "wb35rx_s.h"
 362
 363 /* For Hal using ============================================ */
 364 struct hw_data {
 365         /* For compatible with 33 */
 366         u32     revision;
 367         u32     BB3c_cal; /* The value for Tx calibration comes from EEPROM */
 368         u32     BB54_cal; /* The value for Rx calibration comes from EEPROM */
 369
 370         /* For surprise remove */
 371         u32     SurpriseRemove; /* 0: Normal 1: Surprise remove */
 372         u8      IsKeyPreSet;
 373         u8      CalOneTime;
 374
 375         u8      VCO_trim;
 376
 377         u32     FragCount;
 378         u32     DMAFix; /* V1_DMA_FIX The variable can be removed if driver want to save mem space for V2. */
 379
 380         /*
 381          * ===============================================
 382          * Definition for MAC address
 383          * ===============================================
 384          */
 385         u8      PermanentMacAddress[ETH_ALEN + 2]; /* The Ethernet addr that are stored in EEPROM. + 2 to 8-byte alignment */
 386         u8      CurrentMacAddress[ETH_ALEN + 2]; /* The Enthernet addr that are in used. + 2 to 8-byte alignment */
 387
 388         /*
 389          * =========================================
 390          * Definition for 802.11
 391          * =========================================
 392          */
 393         u8      *bssid_pointer; /* Used by hal_get_bssid for return value */
 394         u8      bssid[8]; /* Only 6 byte will be used. 8 byte is required for read buffer */
 395         u8      ssid[32]; /* maximum ssid length is 32 byte */
 396
 397         u16     AID;
 398         u8      ssid_length;
 399         u8      Channel;
 400
 401         u16     ListenInterval;
 402         u16     CapabilityInformation;
 403
 404         u16     BeaconPeriod;
 405         u16     ProbeDelay;
 406
 407         u8      bss_type;/* 0: IBSS_NET or 1:ESS_NET */
 408         u8      preamble;/* 0: short preamble, 1: long preamble */
 409         u8      slot_time_select; /* 9 or 20 value */
 410         u8      phy_type; /* Phy select */
 411
 412         u32     phy_para[MAX_RF_PARAMETER];
 413         u32     phy_number;
 414
 415         u32     CurrentRadioSw; /* 0:On 1:Off */
 416         u32     CurrentRadioHw; /* 0:On 1:Off */
 417
 418         u8      *power_save_point; /* Used by hal_get_power_save_mode for return value */
 419         u8      cwmin;
 420         u8      desired_power_save;
 421         u8      dtim; /* Is running dtim */
 422         u8      mapping_key_replace_index; /* In Key table, the next index be replaced */
 423
 424         u16     MaxReceiveLifeTime;
 425         u16     FragmentThreshold;
 426         u16     FragmentThreshold_tmp;
 427         u16     cwmax;
 428
 429         u8      Key_slot[MAX_KEY_TABLE][8]; /* Ownership record for key slot. For Alignment */
 430         u32     Key_content[MAX_KEY_TABLE][12]; /* 10DW for each entry + 2 for burst command (Off and On valid bit) */
 431         u8      CurrentDefaultKeyIndex;
 432         u32     CurrentDefaultKeyLength;
 433
 434         /*
 435          * ==================================================
 436          * Variable for each module
 437          * ==================================================
 438          */
 439         struct usb_device       *udev;
 440         struct wb35_reg         reg;    /* Need Wb35Reg.h */
 441         struct wb35_tx          Wb35Tx; /* Need Wb35Tx.h */
 442         struct wb35_rx          Wb35Rx; /* Need Wb35Rx.h */
 443
 444         struct timer_list       LEDTimer; /* For LED */
 445
 446         u32                     LEDpoint; /* For LED */
 447
 448         u32                     dto_tx_retry_count;
 449         u32                     dto_tx_frag_count;
 450         u32                     rx_ok_count[13]; /* index=0: total rx ok */
 451         u32                     rx_err_count[13]; /* index=0: total rx err */
 452
 453         /* for Tx debug */
 454         u32                     tx_TBTT_start_count;
 455         u32                     tx_ETR_count;
 456         u32                     tx_WepOn_false_count;
 457         u32                     tx_Null_key_count;
 458         u32                     tx_retry_count[8];
 459
 460         u8                      PowerIndexFromEEPROM; /* For 2412MHz */
 461         u8                      power_index;
 462         u8                      IsWaitJoinComplete; /* TRUE: set join request */
 463         u8                      band;
 464
 465         u16                     SoftwareSet;
 466         u16                     Reserved_s;
 467
 468         u32                     IsInitOK; /* 0: Driver starting 1: Driver init OK */
 469
 470         /* For Phy calibration */
 471         s32                     iq_rsdl_gain_tx_d2;
 472         s32                     iq_rsdl_phase_tx_d2;
 473         u32                     txvga_setting_for_cal;
 474
 475         u8                      TxVgaSettingInEEPROM[(((MAX_TXVGA_EEPROM * 2) + 3) & ~0x03)]; /* For EEPROM value */
 476         u8                      TxVgaFor24[16]; /* Max is 14, 2 for alignment */
 477         struct txvga_for_50             TxVgaFor50[36]; /* 35 channels in 5G. 35x2 = 70 byte. 2 for alignments */
 478
 479         u16                     Scan_Interval;
 480         u16                     RESERVED6;
 481
 482         /* LED control */
 483         u32             LED_control;
 484         /*
 485          * LED_control 4 byte: Gray_Led_1[3] Gray_Led_0[2] Led[1] Led[0]
 486          * Gray_Led
 487          *              For Led gray setting
 488          * Led
 489          *              0: normal control,
 490          *                      LED behavior will decide by EEPROM setting
 491          *              1: Turn off specific LED
 492          *              2: Always on specific LED
 493          *              3: slow blinking specific LED
 494          *              4: fast blinking specific LED
 495          *              5: WPS led control is set. Led0 is Red, Led1 id Green
 496          *
 497          * Led[1] is parameter for WPS LED mode
 498          *              1:InProgress
 499          *              2: Error
 500          *              3: Session overlap
 501          *              4: Success control
 502          */
 503         u32             LED_LinkOn;     /* Turn LED on control */
 504         u32             LED_Scanning;   /* Let LED in scan process control */
 505         u32             LED_Blinking;   /* Temp variable for shining */
 506         u32             RxByteCountLast;
 507         u32             TxByteCountLast;
 508
 509         /* For global timer */
 510         u32             time_count;     /* TICK_TIME_100ms 1 = 100ms */
 511 };
 512
 513 #endif