sound/soc/soc-io.c

   1 /*
   2  * soc-io.c  --  ASoC register I/O helpers
   3  *
   4  * Copyright 2009-2011 Wolfson Microelectronics PLC.
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *  This program is free software; you can redistribute  it and/or modify it
   9  *  under  the terms of  the GNU General  Public License as published by the
  10  *  Free Software Foundation;  either version 2 of the  License, or (at your
  11  *  option) any later version.
  12  */
  13
  14 #include <linux/i2c.h>
  15 #include <linux/spi/spi.h>
  16 #include <sound/soc.h>
  17
  18 #include <trace/events/asoc.h>
  19
  20 #ifdef CONFIG_SPI_MASTER
  21 static int do_spi_write(void *control, const char *data, int len)
  22 {
  23         struct spi_device *spi = control;
  24         int ret;
  25
  26         ret = spi_write(spi, data, len);
  27         if (ret < 0)
  28                 return ret;
  29
  30         return len;
  31 }
  32 #endif
  33
  34 static int do_hw_write(struct snd_soc_codec *codec, unsigned int reg,
  35                        unsigned int value, const void *data, int len)
  36 {
  37         int ret;
  38
  39         if (!snd_soc_codec_volatile_register(codec, reg) &&
  40             reg < codec->driver->reg_cache_size &&
  41             !codec->cache_bypass) {
  42                 ret = snd_soc_cache_write(codec, reg, value);
  43                 if (ret < 0)
  44                         return -1;
  45         }
  46
  47         if (codec->cache_only) {
  48                 codec->cache_sync = 1;
  49                 return 0;
  50         }
  51
  52         ret = codec->hw_write(codec->control_data, data, len);
  53         if (ret == len)
  54                 return 0;
  55         if (ret < 0)
  56                 return ret;
  57         else
  58                 return -EIO;
  59 }
  60
  61 static unsigned int hw_read(struct snd_soc_codec *codec, unsigned int reg)
  62 {
  63         int ret;
  64         unsigned int val;
  65
  66         if (reg >= codec->driver->reg_cache_size ||
  67             snd_soc_codec_volatile_register(codec, reg) ||
  68             codec->cache_bypass) {
  69                 if (codec->cache_only)
  70                         return -1;
  71
  72                 BUG_ON(!codec->hw_read);
  73                 return codec->hw_read(codec, reg);
  74         }
  75
  76         ret = snd_soc_cache_read(codec, reg, &val);
  77         if (ret < 0)
  78                 return -1;
  79         return val;
  80 }
  81
  82 static int snd_soc_4_12_write(struct snd_soc_codec *codec, unsigned int reg,
  83                               unsigned int value)
  84 {
  85         u16 data;
  86
  87         data = cpu_to_be16((reg << 12) | (value & 0xffffff));
  88
  89         return do_hw_write(codec, reg, value, &data, 2);
  90 }
  91
  92 static int snd_soc_7_9_write(struct snd_soc_codec *codec, unsigned int reg,
  93                              unsigned int value)
  94 {
  95         u16 data;
  96
  97         data = cpu_to_be16((reg << 9) | (value & 0x1ff));
  98
  99         return do_hw_write(codec, reg, value, &data, 2);
 100 }
 101
 102 static int snd_soc_8_8_write(struct snd_soc_codec *codec, unsigned int reg,
 103                              unsigned int value)
 104 {
 105         u8 data[2];
 106
 107         reg &= 0xff;
 108         data[0] = reg;
 109         data[1] = value & 0xff;
 110
 111         return do_hw_write(codec, reg, value, data, 2);
 112 }
 113
 114 static int snd_soc_8_16_write(struct snd_soc_codec *codec, unsigned int reg,
 115                               unsigned int value)
 116 {
 117         u8 data[3];
 118         u16 val = cpu_to_be16(value);
 119
 120         data[0] = reg;
 121         memcpy(&data[1], &val, sizeof(val));
 122
 123         return do_hw_write(codec, reg, value, data, 3);
 124 }
 125
 126 #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
 127 static unsigned int do_i2c_read(struct snd_soc_codec *codec,
 128                                 void *reg, int reglen,
 129                                 void *data, int datalen)
 130 {
 131         struct i2c_msg xfer[2];
 132         int ret;
 133         struct i2c_client *client = codec->control_data;
 134
 135         /* Write register */
 136         xfer[0].addr = client->addr;
 137         xfer[0].flags = 0;
 138         xfer[0].len = reglen;
 139         xfer[0].buf = reg;
 140
 141         /* Read data */
 142         xfer[1].addr = client->addr;
 143         xfer[1].flags = I2C_M_RD;
 144         xfer[1].len = datalen;
 145         xfer[1].buf = data;
 146
 147         ret = i2c_transfer(client->adapter, xfer, 2);
 148         if (ret == 2)
 149                 return 0;
 150         else if (ret < 0)
 151                 return ret;
 152         else
 153                 return -EIO;
 154 }
 155 #endif
 156
 157 #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
 158 static unsigned int snd_soc_8_8_read_i2c(struct snd_soc_codec *codec,
 159                                          unsigned int r)
 160 {
 161         u8 reg = r;
 162         u8 data;
 163         int ret;
 164
 165         ret = do_i2c_read(codec, &reg, 1, &data, 1);
 166         if (ret < 0)
 167                 return 0;
 168         return data;
 169 }
 170 #else
 171 #define snd_soc_8_8_read_i2c NULL
 172 #endif
 173
 174 #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
 175 static unsigned int snd_soc_8_16_read_i2c(struct snd_soc_codec *codec,
 176                                           unsigned int r)
 177 {
 178         u8 reg = r;
 179         u16 data;
 180         int ret;
 181
 182         ret = do_i2c_read(codec, &reg, 1, &data, 2);
 183         if (ret < 0)
 184                 return 0;
 185         return (data >> 8) | ((data & 0xff) << 8);
 186 }
 187 #else
 188 #define snd_soc_8_16_read_i2c NULL
 189 #endif
 190
 191 #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
 192 static unsigned int snd_soc_16_8_read_i2c(struct snd_soc_codec *codec,
 193                                           unsigned int r)
 194 {
 195         u16 reg = r;
 196         u8 data;
 197         int ret;
 198
 199         ret = do_i2c_read(codec, &reg, 2, &data, 1);
 200         if (ret < 0)
 201                 return 0;
 202         return data;
 203 }
 204 #else
 205 #define snd_soc_16_8_read_i2c NULL
 206 #endif
 207
 208 static int snd_soc_16_8_write(struct snd_soc_codec *codec, unsigned int reg,
 209                               unsigned int value)
 210 {
 211         u8 data[3];
 212         u16 rval = cpu_to_be16(reg);
 213
 214         memcpy(data, &rval, sizeof(rval));
 215         data[2] = value;
 216
 217         return do_hw_write(codec, reg, value, data, 3);
 218 }
 219
 220 #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
 221 static unsigned int snd_soc_16_16_read_i2c(struct snd_soc_codec *codec,
 222                                            unsigned int r)
 223 {
 224         u16 reg = cpu_to_be16(r);
 225         u16 data;
 226         int ret;
 227
 228         ret = do_i2c_read(codec, &reg, 2, &data, 2);
 229         if (ret < 0)
 230                 return 0;
 231         return be16_to_cpu(data);
 232 }
 233 #else
 234 #define snd_soc_16_16_read_i2c NULL
 235 #endif
 236
 237 static int snd_soc_16_16_write(struct snd_soc_codec *codec, unsigned int reg,
 238                                unsigned int value)
 239 {
 240         u16 data[2];
 241
 242         data[0] = cpu_to_be16(reg);
 243         data[1] = cpu_to_be16(value);
 244
 245         return do_hw_write(codec, reg, value, data, sizeof(data));
 246 }
 247
 248 /* Primitive bulk write support for soc-cache.  The data pointed to by
 249  * `data' needs to already be in the form the hardware expects
 250  * including any leading register specific data.  Any data written
 251  * through this function will not go through the cache as it only
 252  * handles writing to volatile or out of bounds registers.
 253  */
 254 static int snd_soc_hw_bulk_write_raw(struct snd_soc_codec *codec, unsigned int reg,
 255                                      const void *data, size_t len)
 256 {
 257         int ret;
 258
 259         /* To ensure that we don't get out of sync with the cache, check
 260          * whether the base register is volatile or if we've directly asked
 261          * to bypass the cache.  Out of bounds registers are considered
 262          * volatile.
 263          */
 264         if (!codec->cache_bypass
 265             && !snd_soc_codec_volatile_register(codec, reg)
 266             && reg < codec->driver->reg_cache_size)
 267                 return -EINVAL;
 268
 269         switch (codec->control_type) {
 270 #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
 271         case SND_SOC_I2C:
 272                 ret = i2c_master_send(to_i2c_client(codec->dev), data, len);
 273                 break;
 274 #endif
 275 #if defined(CONFIG_SPI_MASTER)
 276         case SND_SOC_SPI:
 277                 ret = spi_write(to_spi_device(codec->dev), data, len);
 278                 break;
 279 #endif
 280         default:
 281                 BUG();
 282         }
 283
 284         if (ret == len)
 285                 return 0;
 286         if (ret < 0)
 287                 return ret;
 288         else
 289                 return -EIO;
 290 }
 291
 292 static struct {
 293         int addr_bits;
 294         int data_bits;
 295         int (*write)(struct snd_soc_codec *codec, unsigned int, unsigned int);
 296         unsigned int (*read)(struct snd_soc_codec *, unsigned int);
 297         unsigned int (*i2c_read)(struct snd_soc_codec *, unsigned int);
 298 } io_types[] = {
 299         {
 300                 .addr_bits = 4, .data_bits = 12,
 301                 .write = snd_soc_4_12_write,
 302         },
 303         {
 304                 .addr_bits = 7, .data_bits = 9,
 305                 .write = snd_soc_7_9_write,
 306         },
 307         {
 308                 .addr_bits = 8, .data_bits = 8,
 309                 .write = snd_soc_8_8_write,
 310                 .i2c_read = snd_soc_8_8_read_i2c,
 311         },
 312         {
 313                 .addr_bits = 8, .data_bits = 16,
 314                 .write = snd_soc_8_16_write,
 315                 .i2c_read = snd_soc_8_16_read_i2c,
 316         },
 317         {
 318                 .addr_bits = 16, .data_bits = 8,
 319                 .write = snd_soc_16_8_write,
 320                 .i2c_read = snd_soc_16_8_read_i2c,
 321         },
 322         {
 323                 .addr_bits = 16, .data_bits = 16,
 324                 .write = snd_soc_16_16_write,
 325                 .i2c_read = snd_soc_16_16_read_i2c,
 326         },
 327 };
 328
 329 /**
 330  * snd_soc_codec_set_cache_io: Set up standard I/O functions.
 331  *
 332  * @codec: CODEC to configure.
 333  * @addr_bits: Number of bits of register address data.
 334  * @data_bits: Number of bits of data per register.
 335  * @control: Control bus used.
 336  *
 337  * Register formats are frequently shared between many I2C and SPI
 338  * devices.  In order to promote code reuse the ASoC core provides
 339  * some standard implementations of CODEC read and write operations
 340  * which can be set up using this function.
 341  *
 342  * The caller is responsible for allocating and initialising the
 343  * actual cache.
 344  *
 345  * Note that at present this code cannot be used by CODECs with
 346  * volatile registers.
 347  */
 348 int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec,
 349                                int addr_bits, int data_bits,
 350                                enum snd_soc_control_type control)
 351 {
 352         int i;
 353
 354         for (i = 0; i < ARRAY_SIZE(io_types); i++)
 355                 if (io_types[i].addr_bits == addr_bits &&
 356                     io_types[i].data_bits == data_bits)
 357                         break;
 358         if (i == ARRAY_SIZE(io_types)) {
 359                 printk(KERN_ERR
 360                        "No I/O functions for %d bit address %d bit data\n",
 361                        addr_bits, data_bits);
 362                 return -EINVAL;
 363         }
 364
 365         codec->write = io_types[i].write;
 366         codec->read = hw_read;
 367         codec->bulk_write_raw = snd_soc_hw_bulk_write_raw;
 368
 369         switch (control) {
 370         case SND_SOC_I2C:
 371 #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
 372                 codec->hw_write = (hw_write_t)i2c_master_send;
 373 #endif
 374                 if (io_types[i].i2c_read)
 375                         codec->hw_read = io_types[i].i2c_read;
 376
 377                 codec->control_data = container_of(codec->dev,
 378                                                    struct i2c_client,
 379                                                    dev);
 380                 break;
 381
 382         case SND_SOC_SPI:
 383 #ifdef CONFIG_SPI_MASTER
 384                 codec->hw_write = do_spi_write;
 385 #endif
 386
 387                 codec->control_data = container_of(codec->dev,
 388                                                    struct spi_device,
 389                                                    dev);
 390                 break;
 391         }
 392
 393         return 0;
 394 }
 395 EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io);
 396